Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	324	1		T7	5		T8	8		T9	2
all_values[1]	324	1		T7	5		T8	8		T9	2
all_values[2]	324	1		T7	5		T8	8		T9	2
all_values[3]	324	1		T7	5		T8	8		T9	2
all_values[4]	324	1		T7	5		T8	8		T9	2
all_values[5]	324	1		T7	5		T8	8		T9	2
all_values[6]	324	1		T7	5		T8	8		T9	2
all_values[7]	324	1		T7	5		T8	8		T9	2
all_values[8]	324	1		T7	5		T8	8		T9	2
all_values[9]	324	1		T7	5		T8	8		T9	2
all_values[10]	324	1		T7	5		T8	8		T9	2
all_values[11]	324	1		T7	5		T8	8		T9	2
all_values[12]	324	1		T7	5		T8	8		T9	2
all_values[13]	324	1		T7	5		T8	8		T9	2
all_values[14]	324	1		T7	5		T8	8		T9	2
all_values[15]	324	1		T7	5		T8	8		T9	2
all_values[16]	324	1		T7	5		T8	8		T9	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3138	1		T7	44		T8	86		T9	34
auto[1]	2370	1		T7	41		T8	50		T27	75

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1387	1		T7	7		T8	14		T9	34
auto[1]	4121	1		T7	78		T8	122		T27	126

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	59	1		T8	1		T9	2		T10	2
all_values[0]	auto[0]	auto[1]	100	1		T7	1		T8	4		T27	3
all_values[0]	auto[1]	auto[0]	27	1		T8	1		T29	1		T18	1
all_values[0]	auto[1]	auto[1]	138	1		T7	4		T8	2		T27	3
all_values[1]	auto[0]	auto[0]	54	1		T9	2		T10	2		T12	2
all_values[1]	auto[0]	auto[1]	114	1		T7	2		T8	2		T27	4
all_values[1]	auto[1]	auto[0]	21	1		T8	1		T27	1		T60	2
all_values[1]	auto[1]	auto[1]	135	1		T7	3		T8	5		T27	3
all_values[2]	auto[0]	auto[0]	57	1		T9	2		T10	2		T12	2
all_values[2]	auto[0]	auto[1]	135	1		T7	3		T8	5		T27	3
all_values[2]	auto[1]	auto[0]	21	1		T8	1		T28	1		T61	1
all_values[2]	auto[1]	auto[1]	111	1		T7	2		T8	2		T27	5
all_values[3]	auto[0]	auto[0]	71	1		T8	3		T9	2		T10	2
all_values[3]	auto[0]	auto[1]	118	1		T7	3		T8	4		T27	1
all_values[3]	auto[1]	auto[0]	33	1		T8	1		T18	1		T37	1
all_values[3]	auto[1]	auto[1]	102	1		T7	2		T27	7		T28	6
all_values[4]	auto[0]	auto[0]	60	1		T9	2		T10	2		T12	2
all_values[4]	auto[0]	auto[1]	122	1		T8	8		T27	6		T28	6
all_values[4]	auto[1]	auto[0]	27	1		T27	2		T28	1		T29	4
all_values[4]	auto[1]	auto[1]	115	1		T7	5		T28	1		T18	3
all_values[5]	auto[0]	auto[0]	55	1		T9	2		T10	2		T12	2
all_values[5]	auto[0]	auto[1]	96	1		T8	5		T27	3		T28	3
all_values[5]	auto[1]	auto[0]	23	1		T27	1		T28	1		T18	1
all_values[5]	auto[1]	auto[1]	150	1		T7	5		T8	3		T27	4
all_values[6]	auto[0]	auto[0]	61	1		T9	2		T10	2		T27	1
all_values[6]	auto[0]	auto[1]	127	1		T7	4		T8	7		T27	3
all_values[6]	auto[1]	auto[0]	16	1		T27	2		T18	1		T62	3
all_values[6]	auto[1]	auto[1]	120	1		T7	1		T8	1		T27	2
all_values[7]	auto[0]	auto[0]	65	1		T7	4		T9	2		T10	2
all_values[7]	auto[0]	auto[1]	119	1		T8	3		T27	3		T28	6
all_values[7]	auto[1]	auto[0]	19	1		T7	1		T39	2		T63	2
all_values[7]	auto[1]	auto[1]	121	1		T8	5		T27	5		T28	2
all_values[8]	auto[0]	auto[0]	56	1		T9	2		T10	2		T12	2
all_values[8]	auto[0]	auto[1]	127	1		T7	5		T8	5		T27	3
all_values[8]	auto[1]	auto[0]	18	1		T8	1		T27	1		T28	1
all_values[8]	auto[1]	auto[1]	123	1		T8	2		T27	4		T28	2
all_values[9]	auto[0]	auto[0]	60	1		T9	2		T10	2		T12	2
all_values[9]	auto[0]	auto[1]	126	1		T8	7		T27	1		T28	2
all_values[9]	auto[1]	auto[0]	14	1		T28	1		T29	1		T18	1
all_values[9]	auto[1]	auto[1]	124	1		T7	5		T8	1		T27	7
all_values[10]	auto[0]	auto[0]	59	1		T8	2		T9	2		T10	2
all_values[10]	auto[0]	auto[1]	158	1		T7	2		T8	5		T27	4
all_values[10]	auto[1]	auto[0]	17	1		T28	2		T37	2		T39	1
all_values[10]	auto[1]	auto[1]	90	1		T7	3		T8	1		T27	4
all_values[11]	auto[0]	auto[0]	63	1		T9	2		T10	2		T12	2
all_values[11]	auto[0]	auto[1]	126	1		T7	4		T8	3		T27	3
all_values[11]	auto[1]	auto[0]	27	1		T18	1		T37	5		T61	1
all_values[11]	auto[1]	auto[1]	108	1		T7	1		T8	5		T27	5
all_values[12]	auto[0]	auto[0]	70	1		T7	1		T8	1		T9	2
all_values[12]	auto[0]	auto[1]	125	1		T27	3		T28	4		T29	2
all_values[12]	auto[1]	auto[0]	19	1		T39	2		T63	3		T64	1
all_values[12]	auto[1]	auto[1]	110	1		T7	4		T8	7		T27	5
all_values[13]	auto[0]	auto[0]	63	1		T8	1		T9	2		T10	2
all_values[13]	auto[0]	auto[1]	134	1		T7	4		T8	5		T27	7
all_values[13]	auto[1]	auto[0]	25	1		T7	1		T29	4		T65	1
all_values[13]	auto[1]	auto[1]	102	1		T8	2		T27	1		T28	2
all_values[14]	auto[0]	auto[0]	65	1		T9	2		T10	2		T12	2
all_values[14]	auto[0]	auto[1]	127	1		T7	5		T8	5		T27	6
all_values[14]	auto[1]	auto[0]	10	1		T29	3		T63	1		T65	1
all_values[14]	auto[1]	auto[1]	122	1		T8	3		T27	2		T28	1
all_values[15]	auto[0]	auto[0]	57	1		T8	1		T9	2		T10	2
all_values[15]	auto[0]	auto[1]	126	1		T7	4		T8	4		T27	4
all_values[15]	auto[1]	auto[0]	17	1		T39	2		T63	1		T66	1
all_values[15]	auto[1]	auto[1]	124	1		T7	1		T8	3		T27	4
all_values[16]	auto[0]	auto[0]	62	1		T9	2		T10	2		T12	2
all_values[16]	auto[0]	auto[1]	121	1		T7	2		T8	5		T27	1
all_values[16]	auto[1]	auto[0]	16	1		T29	1		T18	1		T37	1
all_values[16]	auto[1]	auto[1]	125	1		T7	3		T8	3		T27	7