Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.09	90.03	75.61	95.05	3.12	87.16	92.01	96.65

Total tests in report: 157

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
51.37	51.37	66.55	66.55	58.80	58.80	73.44	73.44	0.00	0.00	71.90	71.90	66.60	66.60	22.30	22.30	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1998167417
63.00	11.63	88.77	22.21	70.83	12.03	81.83	8.39	3.12	3.12	86.29	14.40	87.50	20.90	22.68	0.37	/workspace/coverage/default/2.usbdev_sec_cm.817694076
70.81	7.80	89.50	0.73	72.47	1.64	90.22	8.39	3.12	0.00	86.29	0.00	87.50	0.00	66.54	43.87	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.1898781956
73.17	2.36	89.50	0.00	73.69	1.23	92.58	2.37	3.12	0.00	86.34	0.04	88.32	0.82	78.62	12.08	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1222032842
74.21	1.04	89.50	0.00	73.69	0.00	92.80	0.22	3.12	0.00	86.34	0.00	88.32	0.00	85.69	7.06	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.1393104998
75.13	0.92	89.75	0.25	73.82	0.13	94.19	1.40	3.12	0.00	86.85	0.52	90.78	2.46	87.36	1.67	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3609447206
75.66	0.53	89.78	0.02	73.93	0.10	94.19	0.00	3.12	0.00	86.90	0.04	90.78	0.00	90.89	3.53	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.164502744
76.15	0.50	90.22	0.44	74.97	1.05	94.84	0.65	3.12	0.00	87.03	0.13	92.01	1.23	90.89	0.00	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2392212233
76.53	0.37	90.22	0.00	74.97	0.00	94.84	0.00	3.12	0.00	87.03	0.00	92.01	0.00	93.49	2.60	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3342982702
76.69	0.16	90.22	0.00	74.97	0.00	94.84	0.00	3.12	0.00	87.03	0.00	92.01	0.00	94.61	1.12	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.675768856
76.79	0.11	90.22	0.00	74.97	0.00	94.84	0.00	3.12	0.00	87.03	0.00	92.01	0.00	95.35	0.74	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.422676067
76.87	0.08	90.22	0.00	74.97	0.00	94.84	0.00	3.12	0.00	87.03	0.00	92.01	0.00	95.91	0.56	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.723700432
76.92	0.05	90.22	0.00	75.03	0.05	95.05	0.22	3.12	0.00	87.11	0.09	92.01	0.00	95.91	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.584481021
76.96	0.04	90.22	0.00	75.31	0.28	95.05	0.00	3.12	0.00	87.11	0.00	92.01	0.00	95.91	0.00	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4149117976
77.00	0.04	90.22	0.00	75.54	0.23	95.05	0.00	3.12	0.00	87.16	0.04	92.01	0.00	95.91	0.00	/workspace/coverage/default/3.usbdev_sec_cm.3420797019
77.03	0.03	90.41	0.19	75.54	0.00	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	95.91	0.00	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3539824195
77.05	0.03	90.41	0.00	75.54	0.00	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.10	0.19	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2294636948
77.08	0.03	90.41	0.00	75.54	0.00	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.28	0.19	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1797930877
77.11	0.03	90.41	0.00	75.54	0.00	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.47	0.19	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.3023894945
77.13	0.03	90.41	0.00	75.54	0.00	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.65	0.19	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4282550341
77.15	0.01	90.41	0.00	75.61	0.08	95.05	0.00	3.12	0.00	87.16	0.00	92.01	0.00	96.65	0.00	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1895906447

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4182360929
/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2007453247
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2097399539
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.239443338
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3482350611
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2885936508
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3339162899
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2711325892
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.311410081
/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.638521697
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3679585132
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.380791653
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3101551546
/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3626777176
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2681094216
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.791659845
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.1497199272
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3311963049
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3397796101
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2647073569
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1013457801
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1538003961
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3850544995
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2096458580
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3301513756
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.4094305367
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2094190255
/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.637327135
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.121134779
/workspace/coverage/cover_reg_top/13.usbdev_intr_test.2745651314
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2985213952
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3393566579
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2436939011
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.381698359
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.590013045
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3471136625
/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3732827941
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.348182465
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1149765942
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3918947556
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1398079473
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1779277676
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1119735791
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3484590686
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1592458257
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2733053122
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3996430280
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2236052529
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4053061575
/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4212868577
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3084011648
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1712583264
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.284065308
/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3256250931
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2623805195
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3142497509
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2370012247
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.662193031
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3655363775
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3423664126
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2132851548
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1281554507
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.492429783
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3808319507
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2577639466
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3782046461
/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1593372877
/workspace/coverage/cover_reg_top/20.usbdev_intr_test.2589467980
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.4187980221
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.388621052
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.334552805
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.2997191508
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2746684916
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.251775811
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3941138066
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2994537877
/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1239919062
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3176260044
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2952429462
/workspace/coverage/cover_reg_top/3.usbdev_intr_test.799482106
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1894066610
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.279986311
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2873846063
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.766511126
/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1667914905
/workspace/coverage/cover_reg_top/30.usbdev_intr_test.3914002818
/workspace/coverage/cover_reg_top/31.usbdev_intr_test.2117301095
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.2256993824
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.3862729635
/workspace/coverage/cover_reg_top/35.usbdev_intr_test.2304329492
/workspace/coverage/cover_reg_top/36.usbdev_intr_test.2583392957
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.1963584756
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3902101296
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1200226007
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2150267008
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3585069359
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2358199781
/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.416070821
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.384138786
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.85864345
/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1299331960
/workspace/coverage/cover_reg_top/40.usbdev_intr_test.3865865647
/workspace/coverage/cover_reg_top/41.usbdev_intr_test.3654744199
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.489486034
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1856360753
/workspace/coverage/cover_reg_top/44.usbdev_intr_test.1969520086
/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2389689951
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.2288069675
/workspace/coverage/cover_reg_top/47.usbdev_intr_test.239681159
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.1277867184
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.3284939613
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2841390820
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2013762641
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1739503577
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1713689459
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3752623277
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2310998976
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3788995278
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2663815793
/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.500848089
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1874857829
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3773575820
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1142725788
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.285582176
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1111878529
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.390805991
/workspace/coverage/cover_reg_top/8.usbdev_intr_test.2917805836
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.797724254
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.793255790
/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2841244295
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2688223944
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1682476210
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1008726821
/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1641748418
/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.910126565
/workspace/coverage/default/0.usbdev_sec_cm.3799311697

Total test records in report: 157

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.usbdev_sec_cm.817694076	Jan 17 01:20:43 PM PST 24	Jan 17 01:20:45 PM PST 24	158446541 ps
T2	/workspace/coverage/default/0.usbdev_sec_cm.3799311697	Jan 17 01:20:42 PM PST 24	Jan 17 01:20:44 PM PST 24	102937833 ps
T3	/workspace/coverage/default/3.usbdev_sec_cm.3420797019	Jan 17 01:20:45 PM PST 24	Jan 17 01:20:46 PM PST 24	161248989 ps
T4	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1998167417	Jan 17 12:29:24 PM PST 24	Jan 17 12:29:33 PM PST 24	98269121 ps
T5	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3101551546	Jan 17 12:29:07 PM PST 24	Jan 17 12:29:13 PM PST 24	257900754 ps
T6	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.311410081	Jan 17 12:29:21 PM PST 24	Jan 17 12:29:25 PM PST 24	207798948 ps
T7	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3902101296	Jan 17 12:30:00 PM PST 24	Jan 17 12:30:02 PM PST 24	26178076 ps
T8	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.2117301095	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:33 PM PST 24	30047637 ps
T9	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1222032842	Jan 17 12:29:27 PM PST 24	Jan 17 12:29:34 PM PST 24	302974146 ps
T10	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.766511126	Jan 17 12:29:27 PM PST 24	Jan 17 12:29:33 PM PST 24	101600771 ps
T19	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2013762641	Jan 17 12:29:22 PM PST 24	Jan 17 12:29:24 PM PST 24	41896354 ps
T20	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.121134779	Jan 17 12:29:32 PM PST 24	Jan 17 12:29:35 PM PST 24	41162436 ps
T11	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3084011648	Jan 17 12:29:47 PM PST 24	Jan 17 12:29:48 PM PST 24	36310669 ps
T27	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.2256993824	Jan 17 12:29:51 PM PST 24	Jan 17 12:29:52 PM PST 24	24416392 ps
T21	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3609447206	Jan 17 12:30:17 PM PST 24	Jan 17 12:30:20 PM PST 24	168623290 ps
T22	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.797724254	Jan 17 12:29:31 PM PST 24	Jan 17 12:29:35 PM PST 24	145846227 ps
T12	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4053061575	Jan 17 12:29:41 PM PST 24	Jan 17 12:29:45 PM PST 24	302192944 ps
T30	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3142497509	Jan 17 12:29:52 PM PST 24	Jan 17 12:29:54 PM PST 24	77213456 ps
T28	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.1898781956	Jan 17 12:29:44 PM PST 24	Jan 17 12:29:45 PM PST 24	21688406 ps
T29	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.675768856	Jan 17 12:29:54 PM PST 24	Jan 17 12:29:55 PM PST 24	29575593 ps
T31	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4182360929	Jan 17 12:29:15 PM PST 24	Jan 17 12:29:18 PM PST 24	171827159 ps
T13	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2647073569	Jan 17 12:29:43 PM PST 24	Jan 17 12:29:44 PM PST 24	41553322 ps
T17	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2392212233	Jan 17 12:29:38 PM PST 24	Jan 17 12:29:40 PM PST 24	24897732 ps
T18	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1856360753	Jan 17 12:29:51 PM PST 24	Jan 17 12:29:52 PM PST 24	55438015 ps
T14	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.416070821	Jan 17 12:29:14 PM PST 24	Jan 17 12:29:17 PM PST 24	253958465 ps
T43	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.381698359	Jan 17 12:29:52 PM PST 24	Jan 17 12:29:53 PM PST 24	34891693 ps
T15	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2132851548	Jan 17 12:29:39 PM PST 24	Jan 17 12:29:41 PM PST 24	41774068 ps
T16	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3397796101	Jan 17 12:29:37 PM PST 24	Jan 17 12:29:39 PM PST 24	149755261 ps
T37	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.2304329492	Jan 17 12:29:42 PM PST 24	Jan 17 12:29:43 PM PST 24	26720295 ps
T26	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1299331960	Jan 17 12:29:27 PM PST 24	Jan 17 12:29:34 PM PST 24	289531702 ps
T38	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1281554507	Jan 17 12:29:09 PM PST 24	Jan 17 12:29:12 PM PST 24	40643610 ps
T39	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.3862729635	Jan 17 12:29:49 PM PST 24	Jan 17 12:29:51 PM PST 24	31892901 ps
T32	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1641748418	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:34 PM PST 24	102111638 ps
T40	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2310998976	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:33 PM PST 24	36226303 ps
T44	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2236052529	Jan 17 12:29:28 PM PST 24	Jan 17 12:29:33 PM PST 24	71726667 ps
T57	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1797930877	Jan 17 12:29:26 PM PST 24	Jan 17 12:29:33 PM PST 24	61761925 ps
T33	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3626777176	Jan 17 12:29:14 PM PST 24	Jan 17 12:29:17 PM PST 24	81005542 ps
T61	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.1393104998	Jan 17 12:29:51 PM PST 24	Jan 17 12:29:53 PM PST 24	27426629 ps
T77	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2681094216	Jan 17 12:29:29 PM PST 24	Jan 17 12:29:33 PM PST 24	44403183 ps
T34	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3655363775	Jan 17 12:29:37 PM PST 24	Jan 17 12:29:40 PM PST 24	251058195 ps
T63	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2370012247	Jan 17 12:29:29 PM PST 24	Jan 17 12:29:32 PM PST 24	25142713 ps
T35	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2663815793	Jan 17 12:29:20 PM PST 24	Jan 17 12:29:24 PM PST 24	57174800 ps
T78	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2885936508	Jan 17 12:29:27 PM PST 24	Jan 17 12:29:44 PM PST 24	203016998 ps
T36	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2711325892	Jan 17 12:29:28 PM PST 24	Jan 17 12:29:33 PM PST 24	51752633 ps
T45	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3773575820	Jan 17 12:29:34 PM PST 24	Jan 17 12:29:36 PM PST 24	112859033 ps
T42	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.910126565	Jan 17 12:29:35 PM PST 24	Jan 17 12:29:39 PM PST 24	138611760 ps
T41	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3850544995	Jan 17 12:29:39 PM PST 24	Jan 17 12:29:42 PM PST 24	130004780 ps
T79	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.793255790	Jan 17 12:29:32 PM PST 24	Jan 17 12:29:36 PM PST 24	49595237 ps
T60	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3585069359	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:32 PM PST 24	31638683 ps
T80	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3176260044	Jan 17 12:29:32 PM PST 24	Jan 17 12:29:35 PM PST 24	42906514 ps
T81	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2733053122	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:33 PM PST 24	32970481 ps
T65	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.2583392957	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:32 PM PST 24	24393039 ps
T66	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.2288069675	Jan 17 12:29:41 PM PST 24	Jan 17 12:29:42 PM PST 24	24453436 ps
T46	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.390805991	Jan 17 12:29:29 PM PST 24	Jan 17 12:29:32 PM PST 24	68913596 ps
T82	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.3654744199	Jan 17 12:29:55 PM PST 24	Jan 17 12:29:57 PM PST 24	102267617 ps
T56	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1593372877	Jan 17 12:29:23 PM PST 24	Jan 17 12:29:27 PM PST 24	311335046 ps
T83	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.1497199272	Jan 17 12:29:16 PM PST 24	Jan 17 12:29:18 PM PST 24	26787543 ps
T47	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3679585132	Jan 17 12:30:26 PM PST 24	Jan 17 12:30:35 PM PST 24	37314024 ps
T59	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1008726821	Jan 17 12:29:31 PM PST 24	Jan 17 12:29:34 PM PST 24	74684969 ps
T84	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.4094305367	Jan 17 12:29:35 PM PST 24	Jan 17 12:29:36 PM PST 24	19669500 ps
T85	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.85864345	Jan 17 12:29:26 PM PST 24	Jan 17 12:29:33 PM PST 24	123548216 ps
T67	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.1963584756	Jan 17 12:29:37 PM PST 24	Jan 17 12:29:38 PM PST 24	22761631 ps
T54	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.164502744	Jan 17 12:29:28 PM PST 24	Jan 17 12:29:36 PM PST 24	264582081 ps
T64	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.2745651314	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:33 PM PST 24	32634458 ps
T68	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.492429783	Jan 17 12:29:21 PM PST 24	Jan 17 12:29:23 PM PST 24	39498633 ps
T58	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.500848089	Jan 17 12:29:24 PM PST 24	Jan 17 12:29:33 PM PST 24	305250413 ps
T86	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1398079473	Jan 17 12:30:01 PM PST 24	Jan 17 12:30:04 PM PST 24	53148375 ps
T48	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3808319507	Jan 17 12:29:38 PM PST 24	Jan 17 12:29:40 PM PST 24	77291649 ps
T87	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.791659845	Jan 17 12:29:56 PM PST 24	Jan 17 12:29:59 PM PST 24	53553466 ps
T88	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1713689459	Jan 17 12:29:19 PM PST 24	Jan 17 12:29:22 PM PST 24	62089159 ps
T89	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3918947556	Jan 17 12:29:45 PM PST 24	Jan 17 12:29:47 PM PST 24	70118334 ps
T62	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.388621052	Jan 17 12:29:55 PM PST 24	Jan 17 12:29:56 PM PST 24	26471701 ps
T90	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3471136625	Jan 17 12:29:28 PM PST 24	Jan 17 12:29:33 PM PST 24	148851818 ps
T91	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3752623277	Jan 17 12:29:24 PM PST 24	Jan 17 12:29:34 PM PST 24	148221112 ps
T23	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.584481021	Jan 17 12:29:25 PM PST 24	Jan 17 12:29:32 PM PST 24	37389939 ps
T69	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.422676067	Jan 17 12:29:52 PM PST 24	Jan 17 12:29:53 PM PST 24	24970904 ps
T92	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.4187980221	Jan 17 12:29:32 PM PST 24	Jan 17 12:29:34 PM PST 24	22729286 ps
T93	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3342982702	Jan 17 12:29:47 PM PST 24	Jan 17 12:29:48 PM PST 24	133591822 ps
T71	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4212868577	Jan 17 12:29:42 PM PST 24	Jan 17 12:29:45 PM PST 24	261737710 ps
T94	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.251775811	Jan 17 12:29:37 PM PST 24	Jan 17 12:29:39 PM PST 24	22391544 ps
T50	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1149765942	Jan 17 12:29:32 PM PST 24	Jan 17 12:29:35 PM PST 24	32776261 ps
T95	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2436939011	Jan 17 12:29:55 PM PST 24	Jan 17 12:29:57 PM PST 24	57394357 ps
T51	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2358199781	Jan 17 12:29:40 PM PST 24	Jan 17 12:29:43 PM PST 24	182931813 ps
T96	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2389689951	Jan 17 12:29:35 PM PST 24	Jan 17 12:29:37 PM PST 24	26759091 ps
T97	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4149117976	Jan 17 12:29:27 PM PST 24	Jan 17 12:29:34 PM PST 24	226918892 ps
T98	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2952429462	Jan 17 12:29:09 PM PST 24	Jan 17 12:29:12 PM PST 24	33622742 ps
T52	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1682476210	Jan 17 12:29:32 PM PST 24	Jan 17 12:29:34 PM PST 24	31082597 ps
T99	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2097399539	Jan 17 12:29:24 PM PST 24	Jan 17 12:29:32 PM PST 24	63276093 ps
T100	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3393566579	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:35 PM PST 24	316120320 ps
T49	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1712583264	Jan 17 12:29:59 PM PST 24	Jan 17 12:30:02 PM PST 24	89947825 ps
T101	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2096458580	Jan 17 12:29:28 PM PST 24	Jan 17 12:29:33 PM PST 24	35493363 ps
T73	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2294636948	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:35 PM PST 24	302934892 ps
T102	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.3284939613	Jan 17 12:29:33 PM PST 24	Jan 17 12:29:35 PM PST 24	32907808 ps
T103	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1200226007	Jan 17 12:29:39 PM PST 24	Jan 17 12:29:41 PM PST 24	172149265 ps
T104	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2623805195	Jan 17 12:29:36 PM PST 24	Jan 17 12:29:38 PM PST 24	45706374 ps
T105	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1874857829	Jan 17 12:29:26 PM PST 24	Jan 17 12:29:33 PM PST 24	38872412 ps
T106	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2985213952	Jan 17 12:29:31 PM PST 24	Jan 17 12:29:35 PM PST 24	52765889 ps
T107	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.590013045	Jan 17 12:29:47 PM PST 24	Jan 17 12:29:48 PM PST 24	73643936 ps
T53	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1119735791	Jan 17 12:29:48 PM PST 24	Jan 17 12:29:49 PM PST 24	98475709 ps
T108	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3539824195	Jan 17 12:29:47 PM PST 24	Jan 17 12:29:49 PM PST 24	104004061 ps
T109	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3311963049	Jan 17 12:29:59 PM PST 24	Jan 17 12:30:03 PM PST 24	34194976 ps
T55	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.284065308	Jan 17 12:29:55 PM PST 24	Jan 17 12:29:57 PM PST 24	149618414 ps
T110	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.2917805836	Jan 17 12:29:34 PM PST 24	Jan 17 12:29:36 PM PST 24	44564033 ps
T25	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1895906447	Jan 17 12:29:18 PM PST 24	Jan 17 12:29:19 PM PST 24	54213401 ps
T111	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2873846063	Jan 17 12:29:40 PM PST 24	Jan 17 12:29:42 PM PST 24	252768041 ps
T75	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.637327135	Jan 17 12:29:44 PM PST 24	Jan 17 12:29:49 PM PST 24	231886337 ps
T112	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1779277676	Jan 17 12:29:29 PM PST 24	Jan 17 12:29:33 PM PST 24	46829041 ps
T113	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1894066610	Jan 17 12:29:15 PM PST 24	Jan 17 12:29:17 PM PST 24	103477522 ps
T114	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1739503577	Jan 17 12:29:24 PM PST 24	Jan 17 12:29:32 PM PST 24	39692105 ps
T70	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.3914002818	Jan 17 12:29:49 PM PST 24	Jan 17 12:29:50 PM PST 24	119208510 ps
T115	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1538003961	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:33 PM PST 24	75242711 ps
T116	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3423664126	Jan 17 12:29:26 PM PST 24	Jan 17 12:29:33 PM PST 24	163112199 ps
T74	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2841244295	Jan 17 12:29:22 PM PST 24	Jan 17 12:29:26 PM PST 24	212750720 ps
T117	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3996430280	Jan 17 12:29:37 PM PST 24	Jan 17 12:29:39 PM PST 24	68166046 ps
T118	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.384138786	Jan 17 12:29:25 PM PST 24	Jan 17 12:29:33 PM PST 24	173435603 ps
T119	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3339162899	Jan 17 12:29:36 PM PST 24	Jan 17 12:29:39 PM PST 24	98157532 ps
T120	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.285582176	Jan 17 12:29:29 PM PST 24	Jan 17 12:29:33 PM PST 24	208273820 ps
T121	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.239443338	Jan 17 12:29:28 PM PST 24	Jan 17 12:29:32 PM PST 24	27518266 ps
T122	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.2997191508	Jan 17 12:29:57 PM PST 24	Jan 17 12:30:00 PM PST 24	31906756 ps
T123	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2688223944	Jan 17 12:29:35 PM PST 24	Jan 17 12:29:37 PM PST 24	69667520 ps
T124	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3941138066	Jan 17 12:29:44 PM PST 24	Jan 17 12:29:45 PM PST 24	26093954 ps
T125	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3484590686	Jan 17 12:29:48 PM PST 24	Jan 17 12:29:50 PM PST 24	37885484 ps
T126	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2577639466	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:39 PM PST 24	362042850 ps
T127	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1013457801	Jan 17 12:29:36 PM PST 24	Jan 17 12:29:38 PM PST 24	46523891 ps
T128	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.1969520086	Jan 17 12:29:49 PM PST 24	Jan 17 12:29:51 PM PST 24	34370393 ps
T129	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3256250931	Jan 17 12:29:38 PM PST 24	Jan 17 12:29:41 PM PST 24	271376312 ps
T130	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.799482106	Jan 17 12:29:20 PM PST 24	Jan 17 12:29:23 PM PST 24	42167454 ps
T131	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.380791653	Jan 17 12:29:21 PM PST 24	Jan 17 12:29:24 PM PST 24	45816203 ps
T132	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.348182465	Jan 17 12:29:28 PM PST 24	Jan 17 12:29:33 PM PST 24	47311152 ps
T133	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1142725788	Jan 17 12:29:38 PM PST 24	Jan 17 12:29:39 PM PST 24	38346197 ps
T134	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2994537877	Jan 17 12:29:31 PM PST 24	Jan 17 12:29:36 PM PST 24	224973944 ps
T135	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3301513756	Jan 17 12:29:39 PM PST 24	Jan 17 12:29:41 PM PST 24	44272999 ps
T136	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2007453247	Jan 17 12:29:19 PM PST 24	Jan 17 12:29:23 PM PST 24	49637403 ps
T137	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.239681159	Jan 17 12:29:33 PM PST 24	Jan 17 12:29:35 PM PST 24	26970723 ps
T138	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3732827941	Jan 17 12:29:33 PM PST 24	Jan 17 12:29:37 PM PST 24	264267834 ps
T139	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3482350611	Jan 17 12:29:30 PM PST 24	Jan 17 12:29:34 PM PST 24	61559741 ps
T140	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1667914905	Jan 17 12:29:08 PM PST 24	Jan 17 12:29:14 PM PST 24	334947852 ps
T141	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.279986311	Jan 17 12:29:23 PM PST 24	Jan 17 12:29:26 PM PST 24	255720085 ps
T142	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2094190255	Jan 17 12:29:32 PM PST 24	Jan 17 12:29:35 PM PST 24	86196862 ps
T143	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.638521697	Jan 17 12:29:32 PM PST 24	Jan 17 12:29:43 PM PST 24	426905758 ps
T144	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.489486034	Jan 17 12:29:47 PM PST 24	Jan 17 12:29:48 PM PST 24	27722335 ps
T145	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3788995278	Jan 17 12:29:29 PM PST 24	Jan 17 12:29:32 PM PST 24	54830628 ps
T146	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.662193031	Jan 17 12:29:26 PM PST 24	Jan 17 12:29:33 PM PST 24	106662220 ps
T147	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3782046461	Jan 17 12:29:07 PM PST 24	Jan 17 12:29:12 PM PST 24	98370595 ps
T148	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.2589467980	Jan 17 12:29:35 PM PST 24	Jan 17 12:29:36 PM PST 24	104455469 ps
T149	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.3023894945	Jan 17 12:29:28 PM PST 24	Jan 17 12:29:32 PM PST 24	21080253 ps
T150	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2150267008	Jan 17 12:29:08 PM PST 24	Jan 17 12:29:11 PM PST 24	24938734 ps
T76	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4282550341	Jan 17 12:29:34 PM PST 24	Jan 17 12:29:40 PM PST 24	325456889 ps
T151	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2746684916	Jan 17 12:29:43 PM PST 24	Jan 17 12:29:44 PM PST 24	30779430 ps
T24	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1239919062	Jan 17 12:29:28 PM PST 24	Jan 17 12:29:32 PM PST 24	48487091 ps
T72	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.723700432	Jan 17 12:29:23 PM PST 24	Jan 17 12:29:28 PM PST 24	232793296 ps
T152	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.3865865647	Jan 17 12:29:55 PM PST 24	Jan 17 12:29:57 PM PST 24	33882042 ps
T153	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2841390820	Jan 17 12:29:26 PM PST 24	Jan 17 12:29:33 PM PST 24	48505720 ps
T154	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1592458257	Jan 17 12:29:42 PM PST 24	Jan 17 12:29:44 PM PST 24	134084535 ps
T155	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1111878529	Jan 17 12:29:28 PM PST 24	Jan 17 12:29:34 PM PST 24	216495771 ps
T156	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.334552805	Jan 17 12:29:34 PM PST 24	Jan 17 12:29:36 PM PST 24	25803021 ps
T157	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.1277867184	Jan 17 12:29:44 PM PST 24	Jan 17 12:29:45 PM PST 24	27057038 ps

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1998167417
Short name	T4
Test name
Test status
Simulation time	98269121 ps
CPU time	1.79 seconds
Started	Jan 17 12:29:24 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	210480 kb
Host	smart-2edba8fb-e770-4e79-a828-b03b9ea7f5b1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998167417 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.1998167417
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/2.usbdev_sec_cm.817694076
Short name	T1
Test name
Test status
Simulation time	158446541 ps
CPU time	1.01 seconds
Started	Jan 17 01:20:43 PM PST 24
Finished	Jan 17 01:20:45 PM PST 24
Peak memory	221780 kb
Host	smart-2d3a052d-5216-4c3a-99b2-3c7bf582da9a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=817694076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.817694076
Directory	/workspace/2.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.1898781956
Short name	T28
Test name
Test status
Simulation time	21688406 ps
CPU time	0.64 seconds
Started	Jan 17 12:29:44 PM PST 24
Finished	Jan 17 12:29:45 PM PST 24
Peak memory	201172 kb
Host	smart-ce9fc052-8a8f-40dc-87fa-2cf42098a81b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1898781956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1898781956
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1222032842
Short name	T9
Test name
Test status
Simulation time	302974146 ps
CPU time	2.88 seconds
Started	Jan 17 12:29:27 PM PST 24
Finished	Jan 17 12:29:34 PM PST 24
Peak memory	202080 kb
Host	smart-6418492d-7153-4aa5-b732-185e4ed6cef7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1222032842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1222032842
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.1393104998
Short name	T61
Test name
Test status
Simulation time	27426629 ps
CPU time	0.65 seconds
Started	Jan 17 12:29:51 PM PST 24
Finished	Jan 17 12:29:53 PM PST 24
Peak memory	201248 kb
Host	smart-37141882-8223-452d-a4cd-b2d6fc9d60b6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1393104998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1393104998
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3609447206
Short name	T21
Test name
Test status
Simulation time	168623290 ps
CPU time	1.46 seconds
Started	Jan 17 12:30:17 PM PST 24
Finished	Jan 17 12:30:20 PM PST 24
Peak memory	202140 kb
Host	smart-6b065618-8412-4b04-8c71-6eac5b36f50a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609447206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.3609447206
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.164502744
Short name	T54
Test name
Test status
Simulation time	264582081 ps
CPU time	4.12 seconds
Started	Jan 17 12:29:28 PM PST 24
Finished	Jan 17 12:29:36 PM PST 24
Peak memory	201764 kb
Host	smart-b4a4553f-0740-4a79-841b-21f31e1ca67a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=164502744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.164502744
Directory	/workspace/1.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2392212233
Short name	T17
Test name
Test status
Simulation time	24897732 ps
CPU time	0.69 seconds
Started	Jan 17 12:29:38 PM PST 24
Finished	Jan 17 12:29:40 PM PST 24
Peak memory	201948 kb
Host	smart-36caa5d6-dd3c-4657-ba87-c307239b1aa3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392212233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2392212233
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3342982702
Short name	T93
Test name
Test status
Simulation time	133591822 ps
CPU time	0.77 seconds
Started	Jan 17 12:29:47 PM PST 24
Finished	Jan 17 12:29:48 PM PST 24
Peak memory	201412 kb
Host	smart-be2224b5-5dc9-42cc-b361-ff60e31dde00
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3342982702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3342982702
Directory	/workspace/14.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.675768856
Short name	T29
Test name
Test status
Simulation time	29575593 ps
CPU time	0.66 seconds
Started	Jan 17 12:29:54 PM PST 24
Finished	Jan 17 12:29:55 PM PST 24
Peak memory	201268 kb
Host	smart-23b39f55-c2ec-4acb-95d5-4d75d3cef6e8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=675768856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.675768856
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.422676067
Short name	T69
Test name
Test status
Simulation time	24970904 ps
CPU time	0.62 seconds
Started	Jan 17 12:29:52 PM PST 24
Finished	Jan 17 12:29:53 PM PST 24
Peak memory	201240 kb
Host	smart-682b4a53-fab5-4401-9d3c-002956f176a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=422676067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.422676067
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.723700432
Short name	T72
Test name
Test status
Simulation time	232793296 ps
CPU time	4.05 seconds
Started	Jan 17 12:29:23 PM PST 24
Finished	Jan 17 12:29:28 PM PST 24
Peak memory	202256 kb
Host	smart-cff392c9-469d-4881-bc65-c75f0a12374b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=723700432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.723700432
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.584481021
Short name	T23
Test name
Test status
Simulation time	37389939 ps
CPU time	0.77 seconds
Started	Jan 17 12:29:25 PM PST 24
Finished	Jan 17 12:29:32 PM PST 24
Peak memory	201920 kb
Host	smart-a3cde95d-e0a2-48be-a314-bc508a149e02
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584481021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.584481021
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4149117976
Short name	T97
Test name
Test status
Simulation time	226918892 ps
CPU time	2.44 seconds
Started	Jan 17 12:29:27 PM PST 24
Finished	Jan 17 12:29:34 PM PST 24
Peak memory	202260 kb
Host	smart-79b625ab-d7a5-483c-a8ac-2f81eeb31679
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4149117976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.4149117976
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/default/3.usbdev_sec_cm.3420797019
Short name	T3
Test name
Test status
Simulation time	161248989 ps
CPU time	0.96 seconds
Started	Jan 17 01:20:45 PM PST 24
Finished	Jan 17 01:20:46 PM PST 24
Peak memory	220752 kb
Host	smart-7286d981-5ec5-4804-bf9b-848849981155
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3420797019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3420797019
Directory	/workspace/3.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3539824195
Short name	T108
Test name
Test status
Simulation time	104004061 ps
CPU time	1.49 seconds
Started	Jan 17 12:29:47 PM PST 24
Finished	Jan 17 12:29:49 PM PST 24
Peak memory	202172 kb
Host	smart-aada62e9-062c-4e23-88f7-b8ebf941e357
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3539824195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3539824195
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2294636948
Short name	T73
Test name
Test status
Simulation time	302934892 ps
CPU time	3.1 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:35 PM PST 24
Peak memory	202096 kb
Host	smart-d2840200-db96-491a-b009-456eb5846dbc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2294636948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2294636948
Directory	/workspace/0.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1797930877
Short name	T57
Test name
Test status
Simulation time	61761925 ps
CPU time	1.26 seconds
Started	Jan 17 12:29:26 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202156 kb
Host	smart-865fdcd5-2bbe-43e4-9eef-1662ccabb8ea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797930877 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.1797930877
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.3023894945
Short name	T149
Test name
Test status
Simulation time	21080253 ps
CPU time	0.62 seconds
Started	Jan 17 12:29:28 PM PST 24
Finished	Jan 17 12:29:32 PM PST 24
Peak memory	201208 kb
Host	smart-7139b6a1-948f-4d5d-a9af-5d170aa0f3ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3023894945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3023894945
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4282550341
Short name	T76
Test name
Test status
Simulation time	325456889 ps
CPU time	4.31 seconds
Started	Jan 17 12:29:34 PM PST 24
Finished	Jan 17 12:29:40 PM PST 24
Peak memory	202032 kb
Host	smart-b39afad2-88cc-4a74-a436-429ec7d10b41
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4282550341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.4282550341
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1895906447
Short name	T25
Test name
Test status
Simulation time	54213401 ps
CPU time	0.86 seconds
Started	Jan 17 12:29:18 PM PST 24
Finished	Jan 17 12:29:19 PM PST 24
Peak memory	201824 kb
Host	smart-df5bfe3c-1504-43c3-a52b-8c8e9711fa12
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895906447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1895906447
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4182360929
Short name	T31
Test name
Test status
Simulation time	171827159 ps
CPU time	2.08 seconds
Started	Jan 17 12:29:15 PM PST 24
Finished	Jan 17 12:29:18 PM PST 24
Peak memory	201848 kb
Host	smart-12239ac3-87f8-4fef-a74c-8c9f122fdf6e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182360929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.4182360929
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2007453247
Short name	T136
Test name
Test status
Simulation time	49637403 ps
CPU time	1.8 seconds
Started	Jan 17 12:29:19 PM PST 24
Finished	Jan 17 12:29:23 PM PST 24
Peak memory	210340 kb
Host	smart-9df219aa-832a-4d1e-a816-2832abf5b2d5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007453247 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.2007453247
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2097399539
Short name	T99
Test name
Test status
Simulation time	63276093 ps
CPU time	0.87 seconds
Started	Jan 17 12:29:24 PM PST 24
Finished	Jan 17 12:29:32 PM PST 24
Peak memory	202244 kb
Host	smart-257db3b6-8c39-4b1c-bbad-87274bc4ba82
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097399539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2097399539
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.239443338
Short name	T121
Test name
Test status
Simulation time	27518266 ps
CPU time	0.61 seconds
Started	Jan 17 12:29:28 PM PST 24
Finished	Jan 17 12:29:32 PM PST 24
Peak memory	201148 kb
Host	smart-594ca456-821d-464f-af50-f17b8d28d399
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=239443338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.239443338
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3482350611
Short name	T139
Test name
Test status
Simulation time	61559741 ps
CPU time	2.1 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:34 PM PST 24
Peak memory	202088 kb
Host	smart-952eb226-ee4c-4f50-ab7f-32efe31d98b3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3482350611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3482350611
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2885936508
Short name	T78
Test name
Test status
Simulation time	203016998 ps
CPU time	3.75 seconds
Started	Jan 17 12:29:27 PM PST 24
Finished	Jan 17 12:29:44 PM PST 24
Peak memory	202000 kb
Host	smart-c5d55769-49a8-4177-b4a0-ca1d6f48302b
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2885936508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2885936508
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3339162899
Short name	T119
Test name
Test status
Simulation time	98157532 ps
CPU time	1.41 seconds
Started	Jan 17 12:29:36 PM PST 24
Finished	Jan 17 12:29:39 PM PST 24
Peak memory	202116 kb
Host	smart-c383b8c3-ea41-496c-95aa-11d4c3b7051f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339162899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c sr_outstanding.3339162899
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2711325892
Short name	T36
Test name
Test status
Simulation time	51752633 ps
CPU time	1.47 seconds
Started	Jan 17 12:29:28 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	201748 kb
Host	smart-e2283d6d-312e-4e1f-806b-37bd9280e755
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2711325892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2711325892
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.311410081
Short name	T6
Test name
Test status
Simulation time	207798948 ps
CPU time	2.05 seconds
Started	Jan 17 12:29:21 PM PST 24
Finished	Jan 17 12:29:25 PM PST 24
Peak memory	202088 kb
Host	smart-d243044a-6217-4634-8b94-09659434f9ba
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311410081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.311410081
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.638521697
Short name	T143
Test name
Test status
Simulation time	426905758 ps
CPU time	8.5 seconds
Started	Jan 17 12:29:32 PM PST 24
Finished	Jan 17 12:29:43 PM PST 24
Peak memory	202172 kb
Host	smart-e803cf64-32f6-451f-ba5c-385030704d95
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638521697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.638521697
Directory	/workspace/1.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3679585132
Short name	T47
Test name
Test status
Simulation time	37314024 ps
CPU time	0.75 seconds
Started	Jan 17 12:30:26 PM PST 24
Finished	Jan 17 12:30:35 PM PST 24
Peak memory	201884 kb
Host	smart-e028f6f7-ebc7-4a86-91f4-1f24bd1d3881
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679585132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3679585132
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.380791653
Short name	T131
Test name
Test status
Simulation time	45816203 ps
CPU time	1.36 seconds
Started	Jan 17 12:29:21 PM PST 24
Finished	Jan 17 12:29:24 PM PST 24
Peak memory	202120 kb
Host	smart-5ea87f8e-f1f2-4733-bcd6-64c12235465e
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=380791653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.380791653
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3101551546
Short name	T5
Test name
Test status
Simulation time	257900754 ps
CPU time	2.4 seconds
Started	Jan 17 12:29:07 PM PST 24
Finished	Jan 17 12:29:13 PM PST 24
Peak memory	201976 kb
Host	smart-5fd2eee9-cacd-46ac-bcd8-86f6a40424b8
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3101551546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3101551546
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3626777176
Short name	T33
Test name
Test status
Simulation time	81005542 ps
CPU time	2.33 seconds
Started	Jan 17 12:29:14 PM PST 24
Finished	Jan 17 12:29:17 PM PST 24
Peak memory	202132 kb
Host	smart-a3038e02-6c48-4785-9613-7691cbc36929
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3626777176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3626777176
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2681094216
Short name	T77
Test name
Test status
Simulation time	44403183 ps
CPU time	1.18 seconds
Started	Jan 17 12:29:29 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202148 kb
Host	smart-93f58fc6-9e8c-4c09-8f6c-e4133c10b1ca
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681094216 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.2681094216
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.791659845
Short name	T87
Test name
Test status
Simulation time	53553466 ps
CPU time	0.84 seconds
Started	Jan 17 12:29:56 PM PST 24
Finished	Jan 17 12:29:59 PM PST 24
Peak memory	201896 kb
Host	smart-41013059-a930-4703-963a-39e88189dc32
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791659845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.791659845
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.1497199272
Short name	T83
Test name
Test status
Simulation time	26787543 ps
CPU time	0.62 seconds
Started	Jan 17 12:29:16 PM PST 24
Finished	Jan 17 12:29:18 PM PST 24
Peak memory	201244 kb
Host	smart-35004625-4332-451a-b509-6b5a33e3d706
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1497199272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1497199272
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3311963049
Short name	T109
Test name
Test status
Simulation time	34194976 ps
CPU time	0.96 seconds
Started	Jan 17 12:29:59 PM PST 24
Finished	Jan 17 12:30:03 PM PST 24
Peak memory	202164 kb
Host	smart-3c42da5d-0e48-40d4-bf45-7fac75a50179
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311963049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_ csr_outstanding.3311963049
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3397796101
Short name	T16
Test name
Test status
Simulation time	149755261 ps
CPU time	1.59 seconds
Started	Jan 17 12:29:37 PM PST 24
Finished	Jan 17 12:29:39 PM PST 24
Peak memory	202172 kb
Host	smart-82dc340f-5c12-4cbb-9228-3fc83888798e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3397796101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3397796101
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2647073569
Short name	T13
Test name
Test status
Simulation time	41553322 ps
CPU time	0.99 seconds
Started	Jan 17 12:29:43 PM PST 24
Finished	Jan 17 12:29:44 PM PST 24
Peak memory	202164 kb
Host	smart-b85edf55-3ed8-492e-8b36-51f439a51224
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647073569 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.2647073569
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1013457801
Short name	T127
Test name
Test status
Simulation time	46523891 ps
CPU time	0.83 seconds
Started	Jan 17 12:29:36 PM PST 24
Finished	Jan 17 12:29:38 PM PST 24
Peak memory	201824 kb
Host	smart-7c6d253a-d02e-4eff-a9de-eaebe73e7879
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013457801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1013457801
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1538003961
Short name	T115
Test name
Test status
Simulation time	75242711 ps
CPU time	1 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202160 kb
Host	smart-83c4d7bb-d1cd-4f88-8d3c-b308d961ccae
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538003961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_ csr_outstanding.1538003961
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3850544995
Short name	T41
Test name
Test status
Simulation time	130004780 ps
CPU time	1.42 seconds
Started	Jan 17 12:29:39 PM PST 24
Finished	Jan 17 12:29:42 PM PST 24
Peak memory	202056 kb
Host	smart-d5c05cf9-d765-466b-ad07-e81c98834e24
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3850544995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3850544995
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2096458580
Short name	T101
Test name
Test status
Simulation time	35493363 ps
CPU time	1.13 seconds
Started	Jan 17 12:29:28 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202172 kb
Host	smart-d0864598-9bb1-461d-af39-a878ba7459cd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096458580 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.2096458580
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3301513756
Short name	T135
Test name
Test status
Simulation time	44272999 ps
CPU time	0.85 seconds
Started	Jan 17 12:29:39 PM PST 24
Finished	Jan 17 12:29:41 PM PST 24
Peak memory	201976 kb
Host	smart-33bdc823-d082-47e7-b974-26003c28c8c0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301513756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3301513756
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.4094305367
Short name	T84
Test name
Test status
Simulation time	19669500 ps
CPU time	0.63 seconds
Started	Jan 17 12:29:35 PM PST 24
Finished	Jan 17 12:29:36 PM PST 24
Peak memory	201224 kb
Host	smart-6e800d2f-278a-49bd-bdea-f029ebd93bf3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4094305367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.4094305367
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2094190255
Short name	T142
Test name
Test status
Simulation time	86196862 ps
CPU time	1.08 seconds
Started	Jan 17 12:29:32 PM PST 24
Finished	Jan 17 12:29:35 PM PST 24
Peak memory	202196 kb
Host	smart-12c7ae71-bf69-434b-9618-affc115c79a7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094190255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_ csr_outstanding.2094190255
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.637327135
Short name	T75
Test name
Test status
Simulation time	231886337 ps
CPU time	4.53 seconds
Started	Jan 17 12:29:44 PM PST 24
Finished	Jan 17 12:29:49 PM PST 24
Peak memory	202228 kb
Host	smart-a39b94aa-89fe-4d87-827d-46280513345b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=637327135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.637327135
Directory	/workspace/12.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.121134779
Short name	T20
Test name
Test status
Simulation time	41162436 ps
CPU time	1 seconds
Started	Jan 17 12:29:32 PM PST 24
Finished	Jan 17 12:29:35 PM PST 24
Peak memory	202192 kb
Host	smart-36105e5b-ad24-46c5-a51c-5f80384c1faf
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121134779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.121134779
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.2745651314
Short name	T64
Test name
Test status
Simulation time	32634458 ps
CPU time	0.64 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	201224 kb
Host	smart-4e2b609a-2eb3-4380-b6f6-0b6b7c3297e6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2745651314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2745651314
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2985213952
Short name	T106
Test name
Test status
Simulation time	52765889 ps
CPU time	1.35 seconds
Started	Jan 17 12:29:31 PM PST 24
Finished	Jan 17 12:29:35 PM PST 24
Peak memory	202176 kb
Host	smart-fe945d6b-6cb3-40ae-aadf-5eb1b771cef5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985213952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_ csr_outstanding.2985213952
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3393566579
Short name	T100
Test name
Test status
Simulation time	316120320 ps
CPU time	3.05 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:35 PM PST 24
Peak memory	202168 kb
Host	smart-3d8deaca-49a9-438c-a4cb-d5d9f669081b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3393566579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3393566579
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2436939011
Short name	T95
Test name
Test status
Simulation time	57394357 ps
CPU time	1.41 seconds
Started	Jan 17 12:29:55 PM PST 24
Finished	Jan 17 12:29:57 PM PST 24
Peak memory	210684 kb
Host	smart-d6260f61-2905-4eb1-b4ed-fa0141fd715b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436939011 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.2436939011
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.381698359
Short name	T43
Test name
Test status
Simulation time	34891693 ps
CPU time	0.82 seconds
Started	Jan 17 12:29:52 PM PST 24
Finished	Jan 17 12:29:53 PM PST 24
Peak memory	202004 kb
Host	smart-5c105ebb-db77-4a70-b5bf-b54dd192c768
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381698359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.381698359
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.590013045
Short name	T107
Test name
Test status
Simulation time	73643936 ps
CPU time	1.08 seconds
Started	Jan 17 12:29:47 PM PST 24
Finished	Jan 17 12:29:48 PM PST 24
Peak memory	202196 kb
Host	smart-329eebbe-8fb3-406b-88b5-f6899105da4b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590013045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_c sr_outstanding.590013045
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3471136625
Short name	T90
Test name
Test status
Simulation time	148851818 ps
CPU time	1.85 seconds
Started	Jan 17 12:29:28 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202092 kb
Host	smart-9f9b7f9a-28cf-40ea-bc1f-6a2cd61ab22b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3471136625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3471136625
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3732827941
Short name	T138
Test name
Test status
Simulation time	264267834 ps
CPU time	2.74 seconds
Started	Jan 17 12:29:33 PM PST 24
Finished	Jan 17 12:29:37 PM PST 24
Peak memory	202200 kb
Host	smart-28977929-afd0-46cb-8f46-888640d48e94
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3732827941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3732827941
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.348182465
Short name	T132
Test name
Test status
Simulation time	47311152 ps
CPU time	1.62 seconds
Started	Jan 17 12:29:28 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	210400 kb
Host	smart-8436d4fe-6fdb-433a-8456-3471bfe80de7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348182465 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.348182465
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1149765942
Short name	T50
Test name
Test status
Simulation time	32776261 ps
CPU time	0.88 seconds
Started	Jan 17 12:29:32 PM PST 24
Finished	Jan 17 12:29:35 PM PST 24
Peak memory	202092 kb
Host	smart-da9e4799-c88d-4f4b-b4fd-466726f5db64
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149765942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1149765942
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3918947556
Short name	T89
Test name
Test status
Simulation time	70118334 ps
CPU time	1.05 seconds
Started	Jan 17 12:29:45 PM PST 24
Finished	Jan 17 12:29:47 PM PST 24
Peak memory	202176 kb
Host	smart-ee4679e3-f34a-47f7-a43a-cdf3ac970801
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918947556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_ csr_outstanding.3918947556
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1398079473
Short name	T86
Test name
Test status
Simulation time	53148375 ps
CPU time	1.62 seconds
Started	Jan 17 12:30:01 PM PST 24
Finished	Jan 17 12:30:04 PM PST 24
Peak memory	202112 kb
Host	smart-09f66130-167c-4480-85e8-642b3bcadad8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1398079473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1398079473
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1779277676
Short name	T112
Test name
Test status
Simulation time	46829041 ps
CPU time	1.26 seconds
Started	Jan 17 12:29:29 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	210328 kb
Host	smart-8b34fe99-d46c-433e-973e-186780245d11
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779277676 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.1779277676
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1119735791
Short name	T53
Test name
Test status
Simulation time	98475709 ps
CPU time	1.09 seconds
Started	Jan 17 12:29:48 PM PST 24
Finished	Jan 17 12:29:49 PM PST 24
Peak memory	202228 kb
Host	smart-77075561-fc98-43db-b597-62ee229e4ae5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119735791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1119735791
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3484590686
Short name	T125
Test name
Test status
Simulation time	37885484 ps
CPU time	0.98 seconds
Started	Jan 17 12:29:48 PM PST 24
Finished	Jan 17 12:29:50 PM PST 24
Peak memory	202492 kb
Host	smart-d4e1e0c3-867f-4599-8f34-d9339bf28e2f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484590686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.3484590686
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1592458257
Short name	T154
Test name
Test status
Simulation time	134084535 ps
CPU time	1.81 seconds
Started	Jan 17 12:29:42 PM PST 24
Finished	Jan 17 12:29:44 PM PST 24
Peak memory	202152 kb
Host	smart-3eecacd1-7140-432a-bd6a-d63d3a9f792a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1592458257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1592458257
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2733053122
Short name	T81
Test name
Test status
Simulation time	32970481 ps
CPU time	1.26 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	210380 kb
Host	smart-634ae9e0-1e4f-43bb-b17d-b6be4e41f522
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733053122 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.2733053122
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3996430280
Short name	T117
Test name
Test status
Simulation time	68166046 ps
CPU time	0.91 seconds
Started	Jan 17 12:29:37 PM PST 24
Finished	Jan 17 12:29:39 PM PST 24
Peak memory	202324 kb
Host	smart-22ad222e-2804-47e3-a3c1-170cde186d27
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996430280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3996430280
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2236052529
Short name	T44
Test name
Test status
Simulation time	71726667 ps
CPU time	1.39 seconds
Started	Jan 17 12:29:28 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202100 kb
Host	smart-35572af6-f521-42b7-8b7b-402af23f9ba5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236052529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.2236052529
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4053061575
Short name	T12
Test name
Test status
Simulation time	302192944 ps
CPU time	2.86 seconds
Started	Jan 17 12:29:41 PM PST 24
Finished	Jan 17 12:29:45 PM PST 24
Peak memory	202172 kb
Host	smart-e1a5d02f-7ce2-49cc-8f17-79698f9dcea6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4053061575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.4053061575
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.4212868577
Short name	T71
Test name
Test status
Simulation time	261737710 ps
CPU time	2.67 seconds
Started	Jan 17 12:29:42 PM PST 24
Finished	Jan 17 12:29:45 PM PST 24
Peak memory	202192 kb
Host	smart-021be930-fe77-4b1c-a10f-b8444d616858
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4212868577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.4212868577
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3084011648
Short name	T11
Test name
Test status
Simulation time	36310669 ps
CPU time	1 seconds
Started	Jan 17 12:29:47 PM PST 24
Finished	Jan 17 12:29:48 PM PST 24
Peak memory	202228 kb
Host	smart-9436b4a5-2393-451c-925a-29982174f8d9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084011648 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.3084011648
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1712583264
Short name	T49
Test name
Test status
Simulation time	89947825 ps
CPU time	1.04 seconds
Started	Jan 17 12:29:59 PM PST 24
Finished	Jan 17 12:30:02 PM PST 24
Peak memory	202132 kb
Host	smart-206425f4-d113-4c4a-89dd-2099c5938244
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712583264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1712583264
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.284065308
Short name	T55
Test name
Test status
Simulation time	149618414 ps
CPU time	1.55 seconds
Started	Jan 17 12:29:55 PM PST 24
Finished	Jan 17 12:29:57 PM PST 24
Peak memory	202224 kb
Host	smart-da9990a3-80d1-437e-8675-ae05f4b8f3a3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284065308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_c sr_outstanding.284065308
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3256250931
Short name	T129
Test name
Test status
Simulation time	271376312 ps
CPU time	2.85 seconds
Started	Jan 17 12:29:38 PM PST 24
Finished	Jan 17 12:29:41 PM PST 24
Peak memory	202140 kb
Host	smart-538169d6-1e19-4bbe-a9a8-198a580a6115
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3256250931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3256250931
Directory	/workspace/18.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2623805195
Short name	T104
Test name
Test status
Simulation time	45706374 ps
CPU time	1.18 seconds
Started	Jan 17 12:29:36 PM PST 24
Finished	Jan 17 12:29:38 PM PST 24
Peak memory	202124 kb
Host	smart-907b865d-01c8-46a8-9172-8b432f1da4bb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623805195 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.2623805195
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3142497509
Short name	T30
Test name
Test status
Simulation time	77213456 ps
CPU time	1.06 seconds
Started	Jan 17 12:29:52 PM PST 24
Finished	Jan 17 12:29:54 PM PST 24
Peak memory	202180 kb
Host	smart-94fe80ff-4602-494b-a4bd-7ea5d2b3f379
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142497509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3142497509
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2370012247
Short name	T63
Test name
Test status
Simulation time	25142713 ps
CPU time	0.66 seconds
Started	Jan 17 12:29:29 PM PST 24
Finished	Jan 17 12:29:32 PM PST 24
Peak memory	201224 kb
Host	smart-932a7f0f-7a59-466c-b61f-cc500d5264d7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2370012247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2370012247
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.662193031
Short name	T146
Test name
Test status
Simulation time	106662220 ps
CPU time	1.36 seconds
Started	Jan 17 12:29:26 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202144 kb
Host	smart-1341cb8b-ed98-496e-91f6-8e3ac8befda4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662193031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_c sr_outstanding.662193031
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3655363775
Short name	T34
Test name
Test status
Simulation time	251058195 ps
CPU time	2.52 seconds
Started	Jan 17 12:29:37 PM PST 24
Finished	Jan 17 12:29:40 PM PST 24
Peak memory	202200 kb
Host	smart-5c629351-a273-4737-b346-0abaa5681713
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3655363775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3655363775
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3423664126
Short name	T116
Test name
Test status
Simulation time	163112199 ps
CPU time	2.01 seconds
Started	Jan 17 12:29:26 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202196 kb
Host	smart-07d9264a-f2bf-4628-8702-4ade2f0f0175
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423664126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3423664126
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2132851548
Short name	T15
Test name
Test status
Simulation time	41774068 ps
CPU time	0.9 seconds
Started	Jan 17 12:29:39 PM PST 24
Finished	Jan 17 12:29:41 PM PST 24
Peak memory	202260 kb
Host	smart-ff733391-cc1d-4368-98e2-740aa1b26639
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132851548 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.2132851548
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1281554507
Short name	T38
Test name
Test status
Simulation time	40643610 ps
CPU time	0.97 seconds
Started	Jan 17 12:29:09 PM PST 24
Finished	Jan 17 12:29:12 PM PST 24
Peak memory	202208 kb
Host	smart-d4b04008-4c11-4ffd-b747-8dac12a2008a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281554507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1281554507
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.492429783
Short name	T68
Test name
Test status
Simulation time	39498633 ps
CPU time	0.65 seconds
Started	Jan 17 12:29:21 PM PST 24
Finished	Jan 17 12:29:23 PM PST 24
Peak memory	201200 kb
Host	smart-b92769ba-7c65-4ede-bbd7-0d647d9b8aa1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=492429783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.492429783
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3808319507
Short name	T48
Test name
Test status
Simulation time	77291649 ps
CPU time	1.39 seconds
Started	Jan 17 12:29:38 PM PST 24
Finished	Jan 17 12:29:40 PM PST 24
Peak memory	202156 kb
Host	smart-e18df47c-70f0-47ef-a714-d86fa570ada8
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3808319507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3808319507
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2577639466
Short name	T126
Test name
Test status
Simulation time	362042850 ps
CPU time	2.51 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:39 PM PST 24
Peak memory	202036 kb
Host	smart-d7ee5676-6952-42aa-8f71-0138565cbfb8
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2577639466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2577639466
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3782046461
Short name	T147
Test name
Test status
Simulation time	98370595 ps
CPU time	1.13 seconds
Started	Jan 17 12:29:07 PM PST 24
Finished	Jan 17 12:29:12 PM PST 24
Peak memory	202256 kb
Host	smart-08e180db-3e24-408f-a262-bcef6893e61a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782046461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c sr_outstanding.3782046461
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1593372877
Short name	T56
Test name
Test status
Simulation time	311335046 ps
CPU time	2.77 seconds
Started	Jan 17 12:29:23 PM PST 24
Finished	Jan 17 12:29:27 PM PST 24
Peak memory	202160 kb
Host	smart-ee3ff9d9-78e0-47e3-bf31-ef9884169d8e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1593372877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1593372877
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.2589467980
Short name	T148
Test name
Test status
Simulation time	104455469 ps
CPU time	0.71 seconds
Started	Jan 17 12:29:35 PM PST 24
Finished	Jan 17 12:29:36 PM PST 24
Peak memory	201144 kb
Host	smart-a5ac0436-7ca3-4209-8278-e84317e0de70
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2589467980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2589467980
Directory	/workspace/20.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.4187980221
Short name	T92
Test name
Test status
Simulation time	22729286 ps
CPU time	0.64 seconds
Started	Jan 17 12:29:32 PM PST 24
Finished	Jan 17 12:29:34 PM PST 24
Peak memory	201220 kb
Host	smart-c408d502-15e6-41ba-bc50-c30a2fabbed4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4187980221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.4187980221
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.388621052
Short name	T62
Test name
Test status
Simulation time	26471701 ps
CPU time	0.66 seconds
Started	Jan 17 12:29:55 PM PST 24
Finished	Jan 17 12:29:56 PM PST 24
Peak memory	201228 kb
Host	smart-14ee7bad-9ac5-4ab7-b062-433bdc41acc7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=388621052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.388621052
Directory	/workspace/23.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.334552805
Short name	T156
Test name
Test status
Simulation time	25803021 ps
CPU time	0.64 seconds
Started	Jan 17 12:29:34 PM PST 24
Finished	Jan 17 12:29:36 PM PST 24
Peak memory	201392 kb
Host	smart-83415230-a15e-4852-8714-c3237bc477c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=334552805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.334552805
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.2997191508
Short name	T122
Test name
Test status
Simulation time	31906756 ps
CPU time	0.65 seconds
Started	Jan 17 12:29:57 PM PST 24
Finished	Jan 17 12:30:00 PM PST 24
Peak memory	201172 kb
Host	smart-faed1460-0083-41b1-9f94-9ea0a0c80b25
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2997191508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2997191508
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2746684916
Short name	T151
Test name
Test status
Simulation time	30779430 ps
CPU time	0.7 seconds
Started	Jan 17 12:29:43 PM PST 24
Finished	Jan 17 12:29:44 PM PST 24
Peak memory	201100 kb
Host	smart-ad2a907f-62ae-4097-ac0e-fcb22d41253c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2746684916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2746684916
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.251775811
Short name	T94
Test name
Test status
Simulation time	22391544 ps
CPU time	0.63 seconds
Started	Jan 17 12:29:37 PM PST 24
Finished	Jan 17 12:29:39 PM PST 24
Peak memory	201244 kb
Host	smart-e4c90fc6-566a-4665-8678-6a3fe0ee4c53
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=251775811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.251775811
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3941138066
Short name	T124
Test name
Test status
Simulation time	26093954 ps
CPU time	0.66 seconds
Started	Jan 17 12:29:44 PM PST 24
Finished	Jan 17 12:29:45 PM PST 24
Peak memory	201220 kb
Host	smart-afd259e7-5fe9-40ba-be58-1b315566b69c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3941138066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3941138066
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2994537877
Short name	T134
Test name
Test status
Simulation time	224973944 ps
CPU time	3.21 seconds
Started	Jan 17 12:29:31 PM PST 24
Finished	Jan 17 12:29:36 PM PST 24
Peak memory	202212 kb
Host	smart-37de1158-c9dd-4efa-bc5e-6bcf4d8472ee
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994537877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2994537877
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1239919062
Short name	T24
Test name
Test status
Simulation time	48487091 ps
CPU time	0.75 seconds
Started	Jan 17 12:29:28 PM PST 24
Finished	Jan 17 12:29:32 PM PST 24
Peak memory	202268 kb
Host	smart-775c662c-9a40-4314-a127-c92a5a2366af
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239919062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1239919062
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3176260044
Short name	T80
Test name
Test status
Simulation time	42906514 ps
CPU time	1.56 seconds
Started	Jan 17 12:29:32 PM PST 24
Finished	Jan 17 12:29:35 PM PST 24
Peak memory	212576 kb
Host	smart-372b6fd3-be79-4ce0-899e-c0cbeb5fc814
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176260044 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.3176260044
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2952429462
Short name	T98
Test name
Test status
Simulation time	33622742 ps
CPU time	0.97 seconds
Started	Jan 17 12:29:09 PM PST 24
Finished	Jan 17 12:29:12 PM PST 24
Peak memory	202128 kb
Host	smart-127bd1a7-196f-44b2-a55a-76875a26e701
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952429462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2952429462
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.799482106
Short name	T130
Test name
Test status
Simulation time	42167454 ps
CPU time	0.67 seconds
Started	Jan 17 12:29:20 PM PST 24
Finished	Jan 17 12:29:23 PM PST 24
Peak memory	201460 kb
Host	smart-3f425f37-3278-4ec4-af52-a4ab704d076e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=799482106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.799482106
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1894066610
Short name	T113
Test name
Test status
Simulation time	103477522 ps
CPU time	1.36 seconds
Started	Jan 17 12:29:15 PM PST 24
Finished	Jan 17 12:29:17 PM PST 24
Peak memory	202136 kb
Host	smart-d024a1c9-fcdb-4f07-82ee-6b0bbac5393c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1894066610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1894066610
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.279986311
Short name	T141
Test name
Test status
Simulation time	255720085 ps
CPU time	2.35 seconds
Started	Jan 17 12:29:23 PM PST 24
Finished	Jan 17 12:29:26 PM PST 24
Peak memory	202012 kb
Host	smart-8f35ec4a-979c-4c65-8b66-c04f52498a79
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=279986311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.279986311
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2873846063
Short name	T111
Test name
Test status
Simulation time	252768041 ps
CPU time	1.46 seconds
Started	Jan 17 12:29:40 PM PST 24
Finished	Jan 17 12:29:42 PM PST 24
Peak memory	202144 kb
Host	smart-ec8737e0-d67c-4c4f-9358-423128bfaf4e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873846063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c sr_outstanding.2873846063
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.766511126
Short name	T10
Test name
Test status
Simulation time	101600771 ps
CPU time	2.08 seconds
Started	Jan 17 12:29:27 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202236 kb
Host	smart-906f7a68-c4e1-4066-8c5e-512434d631e6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=766511126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.766511126
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1667914905
Short name	T140
Test name
Test status
Simulation time	334947852 ps
CPU time	3.03 seconds
Started	Jan 17 12:29:08 PM PST 24
Finished	Jan 17 12:29:14 PM PST 24
Peak memory	202084 kb
Host	smart-be9eac54-cb6c-4d70-ac74-fa46f9317b87
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1667914905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1667914905
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.3914002818
Short name	T70
Test name
Test status
Simulation time	119208510 ps
CPU time	0.73 seconds
Started	Jan 17 12:29:49 PM PST 24
Finished	Jan 17 12:29:50 PM PST 24
Peak memory	201136 kb
Host	smart-57d5f244-9ce4-4371-86ab-623c278ebcf5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3914002818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3914002818
Directory	/workspace/30.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.2117301095
Short name	T8
Test name
Test status
Simulation time	30047637 ps
CPU time	0.7 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	201124 kb
Host	smart-b1331a42-8dea-402e-8b1a-d6c8916b8d4e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2117301095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2117301095
Directory	/workspace/31.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.2256993824
Short name	T27
Test name
Test status
Simulation time	24416392 ps
CPU time	0.63 seconds
Started	Jan 17 12:29:51 PM PST 24
Finished	Jan 17 12:29:52 PM PST 24
Peak memory	201100 kb
Host	smart-57653292-01d8-419c-9091-a9734fd356cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2256993824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2256993824
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.3862729635
Short name	T39
Test name
Test status
Simulation time	31892901 ps
CPU time	0.65 seconds
Started	Jan 17 12:29:49 PM PST 24
Finished	Jan 17 12:29:51 PM PST 24
Peak memory	201176 kb
Host	smart-3f3d8be4-82e4-4240-b33a-fdc57915139d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3862729635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3862729635
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.2304329492
Short name	T37
Test name
Test status
Simulation time	26720295 ps
CPU time	0.64 seconds
Started	Jan 17 12:29:42 PM PST 24
Finished	Jan 17 12:29:43 PM PST 24
Peak memory	201124 kb
Host	smart-3ab51e55-840e-4971-babf-9bb3ebcd4165
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2304329492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2304329492
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.2583392957
Short name	T65
Test name
Test status
Simulation time	24393039 ps
CPU time	0.61 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:32 PM PST 24
Peak memory	201228 kb
Host	smart-5221100c-28c2-4bce-bf41-e089895cab1b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2583392957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2583392957
Directory	/workspace/36.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.1963584756
Short name	T67
Test name
Test status
Simulation time	22761631 ps
CPU time	0.6 seconds
Started	Jan 17 12:29:37 PM PST 24
Finished	Jan 17 12:29:38 PM PST 24
Peak memory	201268 kb
Host	smart-ffd13162-a295-42c9-b6ae-a806e6aa0518
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1963584756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1963584756
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3902101296
Short name	T7
Test name
Test status
Simulation time	26178076 ps
CPU time	0.64 seconds
Started	Jan 17 12:30:00 PM PST 24
Finished	Jan 17 12:30:02 PM PST 24
Peak memory	201272 kb
Host	smart-ec853ddc-2f0b-4a3d-ab85-2272f65361e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3902101296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3902101296
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1200226007
Short name	T103
Test name
Test status
Simulation time	172149265 ps
CPU time	2 seconds
Started	Jan 17 12:29:39 PM PST 24
Finished	Jan 17 12:29:41 PM PST 24
Peak memory	202228 kb
Host	smart-dc03344a-1366-4a31-a899-a8592674a330
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200226007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1200226007
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2150267008
Short name	T150
Test name
Test status
Simulation time	24938734 ps
CPU time	0.74 seconds
Started	Jan 17 12:29:08 PM PST 24
Finished	Jan 17 12:29:11 PM PST 24
Peak memory	201916 kb
Host	smart-8e92547d-dafb-4dce-9525-87a51cf795e3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150267008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2150267008
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3585069359
Short name	T60
Test name
Test status
Simulation time	31638683 ps
CPU time	0.65 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:32 PM PST 24
Peak memory	201220 kb
Host	smart-f4d965fe-dc2f-449c-91ff-4cadd80feeac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3585069359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3585069359
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2358199781
Short name	T51
Test name
Test status
Simulation time	182931813 ps
CPU time	2.27 seconds
Started	Jan 17 12:29:40 PM PST 24
Finished	Jan 17 12:29:43 PM PST 24
Peak memory	202152 kb
Host	smart-40d9b0bb-5892-4571-980f-4d41cc3fbad0
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2358199781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2358199781
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.416070821
Short name	T14
Test name
Test status
Simulation time	253958465 ps
CPU time	2.38 seconds
Started	Jan 17 12:29:14 PM PST 24
Finished	Jan 17 12:29:17 PM PST 24
Peak memory	202016 kb
Host	smart-1d1a4ddd-ee24-4b29-9940-957fcfdd4dd2
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=416070821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.416070821
Directory	/workspace/4.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.384138786
Short name	T118
Test name
Test status
Simulation time	173435603 ps
CPU time	1.54 seconds
Started	Jan 17 12:29:25 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202172 kb
Host	smart-7d19b067-c2d8-46d0-b431-039ee7146d38
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384138786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_cs r_outstanding.384138786
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.85864345
Short name	T85
Test name
Test status
Simulation time	123548216 ps
CPU time	1.85 seconds
Started	Jan 17 12:29:26 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202512 kb
Host	smart-ae973696-5a0b-477e-9d66-9cdac20cc0c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=85864345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.85864345
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1299331960
Short name	T26
Test name
Test status
Simulation time	289531702 ps
CPU time	2.85 seconds
Started	Jan 17 12:29:27 PM PST 24
Finished	Jan 17 12:29:34 PM PST 24
Peak memory	202180 kb
Host	smart-dc9f8977-5b8e-4ee7-b4dd-f9e092d70766
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1299331960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1299331960
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.3865865647
Short name	T152
Test name
Test status
Simulation time	33882042 ps
CPU time	0.66 seconds
Started	Jan 17 12:29:55 PM PST 24
Finished	Jan 17 12:29:57 PM PST 24
Peak memory	201180 kb
Host	smart-2315a8c1-7336-4448-95c7-7db9a805072b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3865865647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3865865647
Directory	/workspace/40.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.3654744199
Short name	T82
Test name
Test status
Simulation time	102267617 ps
CPU time	0.77 seconds
Started	Jan 17 12:29:55 PM PST 24
Finished	Jan 17 12:29:57 PM PST 24
Peak memory	201248 kb
Host	smart-735e9db8-04f9-4650-be5d-0610321ccd24
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3654744199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3654744199
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.489486034
Short name	T144
Test name
Test status
Simulation time	27722335 ps
CPU time	0.62 seconds
Started	Jan 17 12:29:47 PM PST 24
Finished	Jan 17 12:29:48 PM PST 24
Peak memory	201284 kb
Host	smart-fa1ff78a-820d-4505-bfe1-d3bb4b713eb0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=489486034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.489486034
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1856360753
Short name	T18
Test name
Test status
Simulation time	55438015 ps
CPU time	0.66 seconds
Started	Jan 17 12:29:51 PM PST 24
Finished	Jan 17 12:29:52 PM PST 24
Peak memory	201244 kb
Host	smart-14a426de-90d5-434e-9d08-32a94fce5008
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1856360753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1856360753
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.1969520086
Short name	T128
Test name
Test status
Simulation time	34370393 ps
CPU time	0.67 seconds
Started	Jan 17 12:29:49 PM PST 24
Finished	Jan 17 12:29:51 PM PST 24
Peak memory	201252 kb
Host	smart-f4e3b3da-481c-4757-aae1-5870debb07f7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1969520086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1969520086
Directory	/workspace/44.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2389689951
Short name	T96
Test name
Test status
Simulation time	26759091 ps
CPU time	0.64 seconds
Started	Jan 17 12:29:35 PM PST 24
Finished	Jan 17 12:29:37 PM PST 24
Peak memory	201252 kb
Host	smart-ae4d6901-8f89-4de2-a962-e3d237dfc9f7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2389689951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2389689951
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.2288069675
Short name	T66
Test name
Test status
Simulation time	24453436 ps
CPU time	0.63 seconds
Started	Jan 17 12:29:41 PM PST 24
Finished	Jan 17 12:29:42 PM PST 24
Peak memory	201104 kb
Host	smart-c13ab482-652b-4018-a6d2-210401c5b4f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2288069675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2288069675
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.239681159
Short name	T137
Test name
Test status
Simulation time	26970723 ps
CPU time	0.67 seconds
Started	Jan 17 12:29:33 PM PST 24
Finished	Jan 17 12:29:35 PM PST 24
Peak memory	201560 kb
Host	smart-6fb7d32e-3e0b-4eb9-a8bf-9e2941100e2d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=239681159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.239681159
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.1277867184
Short name	T157
Test name
Test status
Simulation time	27057038 ps
CPU time	0.65 seconds
Started	Jan 17 12:29:44 PM PST 24
Finished	Jan 17 12:29:45 PM PST 24
Peak memory	201152 kb
Host	smart-341fe2bb-5499-4ffd-88dc-34dffdbc11c2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1277867184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1277867184
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.3284939613
Short name	T102
Test name
Test status
Simulation time	32907808 ps
CPU time	0.63 seconds
Started	Jan 17 12:29:33 PM PST 24
Finished	Jan 17 12:29:35 PM PST 24
Peak memory	201216 kb
Host	smart-f95806a0-9c1a-4980-ae31-c87aeb13fd88
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3284939613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3284939613
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2841390820
Short name	T153
Test name
Test status
Simulation time	48505720 ps
CPU time	1.23 seconds
Started	Jan 17 12:29:26 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	218856 kb
Host	smart-40401383-fcb8-403a-852c-cf7fe4039962
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841390820 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.2841390820
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2013762641
Short name	T19
Test name
Test status
Simulation time	41896354 ps
CPU time	0.98 seconds
Started	Jan 17 12:29:22 PM PST 24
Finished	Jan 17 12:29:24 PM PST 24
Peak memory	202208 kb
Host	smart-1f7ca0b4-7f15-4315-a853-1fdd6b8ab04c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013762641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2013762641
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1739503577
Short name	T114
Test name
Test status
Simulation time	39692105 ps
CPU time	0.65 seconds
Started	Jan 17 12:29:24 PM PST 24
Finished	Jan 17 12:29:32 PM PST 24
Peak memory	201212 kb
Host	smart-a06fb5bf-e545-4116-b07f-c88535d64f82
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1739503577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1739503577
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1713689459
Short name	T88
Test name
Test status
Simulation time	62089159 ps
CPU time	1.58 seconds
Started	Jan 17 12:29:19 PM PST 24
Finished	Jan 17 12:29:22 PM PST 24
Peak memory	202184 kb
Host	smart-e990ab83-7b8e-4223-a230-07818410502c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713689459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c sr_outstanding.1713689459
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3752623277
Short name	T91
Test name
Test status
Simulation time	148221112 ps
CPU time	2.16 seconds
Started	Jan 17 12:29:24 PM PST 24
Finished	Jan 17 12:29:34 PM PST 24
Peak memory	202556 kb
Host	smart-e2dddcaa-53ec-4742-a0b1-a402f3d473be
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3752623277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3752623277
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2310998976
Short name	T40
Test name
Test status
Simulation time	36226303 ps
CPU time	0.94 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202268 kb
Host	smart-dec25495-b94d-4561-9776-64a98385de32
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310998976 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.2310998976
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3788995278
Short name	T145
Test name
Test status
Simulation time	54830628 ps
CPU time	0.82 seconds
Started	Jan 17 12:29:29 PM PST 24
Finished	Jan 17 12:29:32 PM PST 24
Peak memory	201956 kb
Host	smart-f38500f8-a7f9-41cc-a582-c5734aaa1345
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788995278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3788995278
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2663815793
Short name	T35
Test name
Test status
Simulation time	57174800 ps
CPU time	1.79 seconds
Started	Jan 17 12:29:20 PM PST 24
Finished	Jan 17 12:29:24 PM PST 24
Peak memory	202156 kb
Host	smart-4c1d4ea4-7de4-4faa-b51a-3f58ea9853d9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2663815793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2663815793
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.500848089
Short name	T58
Test name
Test status
Simulation time	305250413 ps
CPU time	2.7 seconds
Started	Jan 17 12:29:24 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202180 kb
Host	smart-7fe42f06-82d7-4d33-b26c-b5ce4ed79485
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=500848089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.500848089
Directory	/workspace/6.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1874857829
Short name	T105
Test name
Test status
Simulation time	38872412 ps
CPU time	1.69 seconds
Started	Jan 17 12:29:26 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	210440 kb
Host	smart-2dc353f5-65eb-46c1-98a1-c9b5edfd282b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874857829 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.1874857829
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3773575820
Short name	T45
Test name
Test status
Simulation time	112859033 ps
CPU time	0.89 seconds
Started	Jan 17 12:29:34 PM PST 24
Finished	Jan 17 12:29:36 PM PST 24
Peak memory	201876 kb
Host	smart-1390d014-fde9-48bb-901d-f252d90842f7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773575820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3773575820
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1142725788
Short name	T133
Test name
Test status
Simulation time	38346197 ps
CPU time	0.61 seconds
Started	Jan 17 12:29:38 PM PST 24
Finished	Jan 17 12:29:39 PM PST 24
Peak memory	201212 kb
Host	smart-2bcbaabd-0430-41cf-acff-7bafec481ab4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1142725788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1142725788
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.285582176
Short name	T120
Test name
Test status
Simulation time	208273820 ps
CPU time	1.42 seconds
Started	Jan 17 12:29:29 PM PST 24
Finished	Jan 17 12:29:33 PM PST 24
Peak memory	202140 kb
Host	smart-cdd0c6d5-c45f-4749-ad29-c97f02dbb24b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285582176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_cs r_outstanding.285582176
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1111878529
Short name	T155
Test name
Test status
Simulation time	216495771 ps
CPU time	2.71 seconds
Started	Jan 17 12:29:28 PM PST 24
Finished	Jan 17 12:29:34 PM PST 24
Peak memory	202176 kb
Host	smart-9785b30b-4acc-4543-bdd6-f0067f7fbb77
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1111878529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1111878529
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.390805991
Short name	T46
Test name
Test status
Simulation time	68913596 ps
CPU time	1.02 seconds
Started	Jan 17 12:29:29 PM PST 24
Finished	Jan 17 12:29:32 PM PST 24
Peak memory	202272 kb
Host	smart-34023d98-c863-416e-9bd3-54fb0995f51c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390805991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.390805991
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.2917805836
Short name	T110
Test name
Test status
Simulation time	44564033 ps
CPU time	0.7 seconds
Started	Jan 17 12:29:34 PM PST 24
Finished	Jan 17 12:29:36 PM PST 24
Peak memory	201272 kb
Host	smart-8d4bb350-c073-48ac-b6d4-ce7bdb5464ae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2917805836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2917805836
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.797724254
Short name	T22
Test name
Test status
Simulation time	145846227 ps
CPU time	1.58 seconds
Started	Jan 17 12:29:31 PM PST 24
Finished	Jan 17 12:29:35 PM PST 24
Peak memory	202128 kb
Host	smart-9e702ca0-aed2-4bdc-afa3-813c9dd676b8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797724254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_cs r_outstanding.797724254
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.793255790
Short name	T79
Test name
Test status
Simulation time	49595237 ps
CPU time	1.66 seconds
Started	Jan 17 12:29:32 PM PST 24
Finished	Jan 17 12:29:36 PM PST 24
Peak memory	202172 kb
Host	smart-21ef2f2b-7a8f-4edc-b295-be6fccda7177
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=793255790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.793255790
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2841244295
Short name	T74
Test name
Test status
Simulation time	212750720 ps
CPU time	2.49 seconds
Started	Jan 17 12:29:22 PM PST 24
Finished	Jan 17 12:29:26 PM PST 24
Peak memory	202180 kb
Host	smart-de48d48e-0b0d-4371-911b-5b37525decf6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2841244295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2841244295
Directory	/workspace/8.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2688223944
Short name	T123
Test name
Test status
Simulation time	69667520 ps
CPU time	1.29 seconds
Started	Jan 17 12:29:35 PM PST 24
Finished	Jan 17 12:29:37 PM PST 24
Peak memory	210392 kb
Host	smart-57aaa95f-db58-49ed-8e24-d2d15c70bf4d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688223944 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.2688223944
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1682476210
Short name	T52
Test name
Test status
Simulation time	31082597 ps
CPU time	0.84 seconds
Started	Jan 17 12:29:32 PM PST 24
Finished	Jan 17 12:29:34 PM PST 24
Peak memory	202068 kb
Host	smart-1106825e-ae1f-44ae-8d56-4783bdb01a7e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682476210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1682476210
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1008726821
Short name	T59
Test name
Test status
Simulation time	74684969 ps
CPU time	1.1 seconds
Started	Jan 17 12:29:31 PM PST 24
Finished	Jan 17 12:29:34 PM PST 24
Peak memory	202192 kb
Host	smart-72e8a9d2-990b-43b0-a1ba-1081594e31cb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008726821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c sr_outstanding.1008726821
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1641748418
Short name	T32
Test name
Test status
Simulation time	102111638 ps
CPU time	2.42 seconds
Started	Jan 17 12:29:30 PM PST 24
Finished	Jan 17 12:29:34 PM PST 24
Peak memory	202120 kb
Host	smart-d63c7d62-103c-4b14-97a3-92e39c3a2133
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1641748418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1641748418
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.910126565
Short name	T42
Test name
Test status
Simulation time	138611760 ps
CPU time	2.47 seconds
Started	Jan 17 12:29:35 PM PST 24
Finished	Jan 17 12:29:39 PM PST 24
Peak memory	202116 kb
Host	smart-42cc2488-9048-4475-a5e2-c76963d9243b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=910126565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.910126565
Directory	/workspace/9.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/0.usbdev_sec_cm.3799311697
Short name	T2
Test name
Test status
Simulation time	102937833 ps
CPU time	0.89 seconds
Started	Jan 17 01:20:42 PM PST 24
Finished	Jan 17 01:20:44 PM PST 24
Peak memory	220812 kb
Host	smart-2e2c6ada-cacf-4424-8bac-b1787e3318e2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3799311697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3799311697
Directory	/workspace/0.usbdev_sec_cm/latest