Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	17	0	17	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	324	1		T7	5		T8	8		T9	2
all_pins[1]	324	1		T7	5		T8	8		T9	2
all_pins[2]	324	1		T7	5		T8	8		T9	2
all_pins[3]	324	1		T7	5		T8	8		T9	2
all_pins[4]	324	1		T7	5		T8	8		T9	2
all_pins[5]	324	1		T7	5		T8	8		T9	2
all_pins[6]	324	1		T7	5		T8	8		T9	2
all_pins[7]	324	1		T7	5		T8	8		T9	2
all_pins[8]	324	1		T7	5		T8	8		T9	2
all_pins[9]	324	1		T7	5		T8	8		T9	2
all_pins[10]	324	1		T7	5		T8	8		T9	2
all_pins[11]	324	1		T7	5		T8	8		T9	2
all_pins[12]	324	1		T7	5		T8	8		T9	2
all_pins[13]	324	1		T7	5		T8	8		T9	2
all_pins[14]	324	1		T7	5		T8	8		T9	2
all_pins[15]	324	1		T7	5		T8	8		T9	2
all_pins[16]	324	1		T7	5		T8	8		T9	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	4543	1		T7	63		T8	109		T9	34
values[0x1]	965	1		T7	22		T8	27		T27	30
transitions[0x0=>0x1]	733	1		T7	14		T8	21		T27	19
transitions[0x1=>0x0]	738	1		T7	14		T8	21		T27	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	266	1		T7	2		T8	7		T9	2
all_pins[0]	values[0x1]	58	1		T7	3		T8	1		T27	2
all_pins[0]	transitions[0x0=>0x1]	43	1		T7	1		T8	1		T27	2
all_pins[0]	transitions[0x1=>0x0]	51	1		T8	4		T27	3		T29	1
all_pins[1]	values[0x0]	258	1		T7	3		T8	4		T9	2
all_pins[1]	values[0x1]	66	1		T7	2		T8	4		T27	3
all_pins[1]	transitions[0x0=>0x1]	54	1		T7	2		T8	3		T27	1
all_pins[1]	transitions[0x1=>0x0]	56	1		T7	1		T8	2		T28	2
all_pins[2]	values[0x0]	256	1		T7	4		T8	5		T9	2
all_pins[2]	values[0x1]	68	1		T7	1		T8	3		T27	2
all_pins[2]	transitions[0x0=>0x1]	59	1		T7	1		T8	3		T27	2
all_pins[2]	transitions[0x1=>0x0]	26	1		T28	3		T37	3		T39	3
all_pins[3]	values[0x0]	289	1		T7	5		T8	8		T9	2
all_pins[3]	values[0x1]	35	1		T28	4		T18	2		T37	3
all_pins[3]	transitions[0x0=>0x1]	30	1		T28	4		T37	3		T39	1
all_pins[3]	transitions[0x1=>0x0]	49	1		T7	2		T28	1		T61	2
all_pins[4]	values[0x0]	270	1		T7	3		T8	8		T9	2
all_pins[4]	values[0x1]	54	1		T7	2		T28	1		T18	2
all_pins[4]	transitions[0x0=>0x1]	38	1		T28	1		T18	2		T39	2
all_pins[4]	transitions[0x1=>0x0]	40	1		T7	1		T8	2		T27	3
all_pins[5]	values[0x0]	268	1		T7	2		T8	6		T9	2
all_pins[5]	values[0x1]	56	1		T7	3		T8	2		T27	3
all_pins[5]	transitions[0x0=>0x1]	42	1		T7	3		T8	2		T27	3
all_pins[5]	transitions[0x1=>0x0]	46	1		T7	1		T29	2		T37	3
all_pins[6]	values[0x0]	264	1		T7	4		T8	8		T9	2
all_pins[6]	values[0x1]	60	1		T7	1		T28	1		T29	2
all_pins[6]	transitions[0x0=>0x1]	45	1		T7	1		T28	1		T37	3
all_pins[6]	transitions[0x1=>0x0]	51	1		T8	3		T28	2		T29	1
all_pins[7]	values[0x0]	258	1		T7	5		T8	5		T9	2
all_pins[7]	values[0x1]	66	1		T8	3		T28	2		T29	3
all_pins[7]	transitions[0x0=>0x1]	50	1		T8	3		T28	2		T29	1
all_pins[7]	transitions[0x1=>0x0]	40	1		T8	1		T27	1		T28	1
all_pins[8]	values[0x0]	268	1		T7	5		T8	7		T9	2
all_pins[8]	values[0x1]	56	1		T8	1		T27	1		T28	1
all_pins[8]	transitions[0x0=>0x1]	44	1		T8	1		T28	1		T29	2
all_pins[8]	transitions[0x1=>0x0]	39	1		T7	3		T8	1		T27	5
all_pins[9]	values[0x0]	273	1		T7	2		T8	7		T9	2
all_pins[9]	values[0x1]	51	1		T7	3		T8	1		T27	6
all_pins[9]	transitions[0x0=>0x1]	43	1		T7	1		T8	1		T27	3
all_pins[9]	transitions[0x1=>0x0]	36	1		T8	1		T28	2		T29	1
all_pins[10]	values[0x0]	280	1		T7	3		T8	7		T9	2
all_pins[10]	values[0x1]	44	1		T7	2		T8	1		T27	3
all_pins[10]	transitions[0x0=>0x1]	35	1		T7	2		T28	2		T29	1
all_pins[10]	transitions[0x1=>0x0]	41	1		T8	2		T28	1		T29	2
all_pins[11]	values[0x0]	274	1		T7	5		T8	5		T9	2
all_pins[11]	values[0x1]	50	1		T8	3		T27	3		T28	1
all_pins[11]	transitions[0x0=>0x1]	39	1		T8	1		T27	3		T28	1
all_pins[11]	transitions[0x1=>0x0]	41	1		T7	3		T8	3		T28	1
all_pins[12]	values[0x0]	272	1		T7	2		T8	3		T9	2
all_pins[12]	values[0x1]	52	1		T7	3		T8	5		T28	1
all_pins[12]	transitions[0x0=>0x1]	41	1		T7	3		T8	4		T28	1
all_pins[12]	transitions[0x1=>0x0]	44	1		T27	1		T28	1		T39	1
all_pins[13]	values[0x0]	269	1		T7	5		T8	7		T9	2
all_pins[13]	values[0x1]	55	1		T8	1		T27	1		T28	1
all_pins[13]	transitions[0x0=>0x1]	40	1		T8	1		T27	1		T28	1
all_pins[13]	transitions[0x1=>0x0]	52	1		T27	1		T18	4		T39	2
all_pins[14]	values[0x0]	257	1		T7	5		T8	8		T9	2
all_pins[14]	values[0x1]	67	1		T27	1		T18	4		T39	2
all_pins[14]	transitions[0x0=>0x1]	43	1		T18	4		T39	2		T61	1
all_pins[14]	transitions[0x1=>0x0]	45	1		T8	1		T27	2		T28	2
all_pins[15]	values[0x0]	255	1		T7	5		T8	7		T9	2
all_pins[15]	values[0x1]	69	1		T8	1		T27	3		T28	2
all_pins[15]	transitions[0x0=>0x1]	51	1		T27	2		T28	2		T37	3
all_pins[15]	transitions[0x1=>0x0]	40	1		T7	2		T27	1		T18	3
all_pins[16]	values[0x0]	266	1		T7	3		T8	7		T9	2
all_pins[16]	values[0x1]	58	1		T7	2		T8	1		T27	2
all_pins[16]	transitions[0x0=>0x1]	36	1		T8	1		T27	2		T18	2
all_pins[16]	transitions[0x1=>0x0]	41	1		T7	1		T8	1		T27	2