Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	102	0	102	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	102	0	102	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	241	1		T7	4		T8	7		T27	7
all_values[1]	241	1		T7	4		T8	7		T27	7
all_values[2]	241	1		T7	4		T8	7		T27	7
all_values[3]	241	1		T7	4		T8	7		T27	7
all_values[4]	241	1		T7	4		T8	7		T27	7
all_values[5]	241	1		T7	4		T8	7		T27	7
all_values[6]	241	1		T7	4		T8	7		T27	7
all_values[7]	241	1		T7	4		T8	7		T27	7
all_values[8]	241	1		T7	4		T8	7		T27	7
all_values[9]	241	1		T7	4		T8	7		T27	7
all_values[10]	241	1		T7	4		T8	7		T27	7
all_values[11]	241	1		T7	4		T8	7		T27	7
all_values[12]	241	1		T7	4		T8	7		T27	7
all_values[13]	241	1		T7	4		T8	7		T27	7
all_values[14]	241	1		T7	4		T8	7		T27	7
all_values[15]	241	1		T7	4		T8	7		T27	7
all_values[16]	241	1		T7	4		T8	7		T27	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2276	1		T7	43		T8	81		T27	66
auto[1]	1821	1		T7	25		T8	38		T27	53

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	666	1		T7	6		T8	14		T27	10
auto[1]	3431	1		T7	62		T8	105		T27	109

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2406	1		T7	31		T8	69		T27	70
auto[1]	1691	1		T7	37		T8	50		T27	49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	102	0	102	100.00
Automatically Generated Cross Bins	102	0	102	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	25	1		T8	2		T27	2		T28	1
all_values[0]	auto[0]	auto[0]	auto[1]	35	1		T8	1		T27	1		T39	1
all_values[0]	auto[0]	auto[1]	auto[0]	20	1		T29	1		T18	2		T37	2
all_values[0]	auto[0]	auto[1]	auto[1]	63	1		T7	1		T8	2		T27	1
all_values[0]	auto[1]	auto[0]	auto[1]	63	1		T7	2		T8	2		T27	3
all_values[0]	auto[1]	auto[1]	auto[1]	35	1		T7	1		T28	1		T29	1
all_values[1]	auto[0]	auto[0]	auto[0]	22	1		T8	1		T27	1		T28	2
all_values[1]	auto[0]	auto[0]	auto[1]	45	1		T8	2		T27	1		T28	2
all_values[1]	auto[0]	auto[1]	auto[0]	11	1		T60	1		T67	2		T68	2
all_values[1]	auto[0]	auto[1]	auto[1]	59	1		T7	1		T8	1		T27	4
all_values[1]	auto[1]	auto[0]	auto[1]	59	1		T7	3		T28	2		T29	2
all_values[1]	auto[1]	auto[1]	auto[1]	45	1		T8	3		T27	1		T29	1
all_values[2]	auto[0]	auto[0]	auto[0]	21	1		T8	1		T61	1		T63	1
all_values[2]	auto[0]	auto[0]	auto[1]	59	1		T7	1		T8	2		T27	1
all_values[2]	auto[0]	auto[1]	auto[0]	14	1		T28	1		T65	1		T66	1
all_values[2]	auto[0]	auto[1]	auto[1]	44	1		T8	1		T27	2		T28	1
all_values[2]	auto[1]	auto[0]	auto[1]	55	1		T7	1		T8	2		T27	2
all_values[2]	auto[1]	auto[1]	auto[1]	48	1		T7	2		T8	1		T27	2
all_values[3]	auto[0]	auto[0]	auto[0]	36	1		T8	2		T29	4		T61	2
all_values[3]	auto[0]	auto[0]	auto[1]	60	1		T7	1		T8	1		T27	2
all_values[3]	auto[0]	auto[1]	auto[0]	23	1		T8	2		T18	2		T37	1
all_values[3]	auto[0]	auto[1]	auto[1]	44	1		T7	1		T27	4		T28	1
all_values[3]	auto[1]	auto[0]	auto[1]	47	1		T7	1		T8	2		T27	1
all_values[3]	auto[1]	auto[1]	auto[1]	31	1		T7	1		T28	3		T18	1
all_values[4]	auto[0]	auto[0]	auto[0]	25	1		T27	1		T29	1		T18	2
all_values[4]	auto[0]	auto[0]	auto[1]	47	1		T8	4		T27	3		T28	3
all_values[4]	auto[0]	auto[1]	auto[0]	21	1		T27	1		T28	1		T29	3
all_values[4]	auto[0]	auto[1]	auto[1]	48	1		T7	2		T28	1		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	56	1		T7	1		T8	3		T27	1
all_values[4]	auto[1]	auto[1]	auto[1]	44	1		T7	1		T27	1		T28	1
all_values[5]	auto[0]	auto[0]	auto[0]	21	1		T27	1		T29	2		T39	2
all_values[5]	auto[0]	auto[0]	auto[1]	44	1		T8	2		T27	2		T29	1
all_values[5]	auto[0]	auto[1]	auto[0]	14	1		T28	1		T18	1		T39	2
all_values[5]	auto[0]	auto[1]	auto[1]	70	1		T7	1		T8	1		T27	1
all_values[5]	auto[1]	auto[0]	auto[1]	45	1		T7	1		T8	1		T27	2
all_values[5]	auto[1]	auto[1]	auto[1]	47	1		T7	2		T8	3		T27	1
all_values[6]	auto[0]	auto[0]	auto[0]	22	1		T27	1		T29	2		T18	2
all_values[6]	auto[0]	auto[0]	auto[1]	52	1		T7	2		T8	3		T27	1
all_values[6]	auto[0]	auto[1]	auto[0]	14	1		T27	2		T62	4		T69	1
all_values[6]	auto[0]	auto[1]	auto[1]	47	1		T7	1		T27	2		T29	1
all_values[6]	auto[1]	auto[0]	auto[1]	70	1		T7	1		T8	4		T27	1
all_values[6]	auto[1]	auto[1]	auto[1]	36	1		T28	2		T29	1		T37	2
all_values[7]	auto[0]	auto[0]	auto[0]	22	1		T7	3		T29	1		T39	1
all_values[7]	auto[0]	auto[0]	auto[1]	46	1		T8	2		T27	1		T28	1
all_values[7]	auto[0]	auto[1]	auto[0]	19	1		T7	1		T39	3		T63	2
all_values[7]	auto[0]	auto[1]	auto[1]	49	1		T8	2		T27	1		T28	1
all_values[7]	auto[1]	auto[0]	auto[1]	59	1		T8	1		T27	5		T28	4
all_values[7]	auto[1]	auto[1]	auto[1]	46	1		T8	2		T28	1		T29	1
all_values[8]	auto[0]	auto[0]	auto[0]	19	1		T8	1		T27	1		T60	1
all_values[8]	auto[0]	auto[0]	auto[1]	54	1		T7	2		T8	2		T27	3
all_values[8]	auto[0]	auto[1]	auto[0]	14	1		T28	1		T29	2		T37	1
all_values[8]	auto[0]	auto[1]	auto[1]	55	1		T27	1		T28	1		T29	1
all_values[8]	auto[1]	auto[0]	auto[1]	57	1		T7	2		T8	4		T27	1
all_values[8]	auto[1]	auto[1]	auto[1]	42	1		T27	1		T28	1		T29	1
all_values[9]	auto[0]	auto[0]	auto[0]	22	1		T29	1		T18	4		T61	3
all_values[9]	auto[0]	auto[0]	auto[1]	55	1		T8	4		T28	1		T29	1
all_values[9]	auto[0]	auto[1]	auto[0]	10	1		T28	1		T29	1		T37	1
all_values[9]	auto[0]	auto[1]	auto[1]	46	1		T7	1		T27	1		T28	3
all_values[9]	auto[1]	auto[0]	auto[1]	59	1		T7	1		T8	3		T27	3
all_values[9]	auto[1]	auto[1]	auto[1]	49	1		T7	2		T27	3		T28	2
all_values[10]	auto[0]	auto[0]	auto[0]	21	1		T8	2		T18	1		T37	1
all_values[10]	auto[0]	auto[0]	auto[1]	67	1		T8	2		T27	2		T28	1
all_values[10]	auto[0]	auto[1]	auto[0]	13	1		T28	3		T37	2		T39	1
all_values[10]	auto[0]	auto[1]	auto[1]	45	1		T7	1		T8	2		T27	1
all_values[10]	auto[1]	auto[0]	auto[1]	61	1		T7	3		T8	1		T27	2
all_values[10]	auto[1]	auto[1]	auto[1]	34	1		T27	2		T28	1		T29	1
all_values[11]	auto[0]	auto[0]	auto[0]	30	1		T29	2		T37	3		T61	1
all_values[11]	auto[0]	auto[0]	auto[1]	62	1		T7	1		T8	2		T27	1
all_values[11]	auto[0]	auto[1]	auto[0]	17	1		T18	1		T37	4		T63	2
all_values[11]	auto[0]	auto[1]	auto[1]	36	1		T8	1		T27	1		T28	1
all_values[11]	auto[1]	auto[0]	auto[1]	50	1		T7	2		T8	1		T27	2
all_values[11]	auto[1]	auto[1]	auto[1]	46	1		T7	1		T8	3		T27	3
all_values[12]	auto[0]	auto[0]	auto[0]	32	1		T7	1		T8	1		T18	2
all_values[12]	auto[0]	auto[0]	auto[1]	49	1		T27	1		T28	1		T29	1
all_values[12]	auto[0]	auto[1]	auto[0]	13	1		T39	3		T63	3		T64	2
all_values[12]	auto[0]	auto[1]	auto[1]	45	1		T7	1		T8	2		T27	5
all_values[12]	auto[1]	auto[0]	auto[1]	59	1		T7	1		T27	1		T28	3
all_values[12]	auto[1]	auto[1]	auto[1]	43	1		T7	1		T8	4		T29	1
all_values[13]	auto[0]	auto[0]	auto[0]	25	1		T7	1		T8	1		T29	1
all_values[13]	auto[0]	auto[0]	auto[1]	53	1		T7	1		T8	4		T27	3
all_values[13]	auto[0]	auto[1]	auto[0]	20	1		T29	3		T65	1		T66	1
all_values[13]	auto[0]	auto[1]	auto[1]	44	1		T27	1		T28	1		T37	1
all_values[13]	auto[1]	auto[0]	auto[1]	63	1		T7	1		T27	2		T28	4
all_values[13]	auto[1]	auto[1]	auto[1]	36	1		T7	1		T8	2		T27	1
all_values[14]	auto[0]	auto[0]	auto[0]	26	1		T28	1		T29	2		T37	2
all_values[14]	auto[0]	auto[0]	auto[1]	54	1		T7	1		T8	4		T27	4
all_values[14]	auto[0]	auto[1]	auto[0]	7	1		T29	2		T65	1		T70	3
all_values[14]	auto[0]	auto[1]	auto[1]	51	1		T8	1		T27	1		T18	2
all_values[14]	auto[1]	auto[0]	auto[1]	55	1		T7	3		T8	1		T27	1
all_values[14]	auto[1]	auto[1]	auto[1]	48	1		T8	1		T27	1		T28	1
all_values[15]	auto[0]	auto[0]	auto[0]	17	1		T8	1		T18	4		T39	1
all_values[15]	auto[0]	auto[0]	auto[1]	58	1		T7	2		T8	2		T27	1
all_values[15]	auto[0]	auto[1]	auto[0]	13	1		T39	3		T63	1		T66	1
all_values[15]	auto[0]	auto[1]	auto[1]	52	1		T7	1		T8	2		T27	3
all_values[15]	auto[1]	auto[0]	auto[1]	58	1		T7	1		T8	2		T27	3
all_values[15]	auto[1]	auto[1]	auto[1]	43	1		T28	3		T37	2		T63	3
all_values[16]	auto[0]	auto[0]	auto[0]	23	1		T29	1		T37	3		T39	1
all_values[16]	auto[0]	auto[0]	auto[1]	50	1		T7	2		T8	2		T28	3
all_values[16]	auto[0]	auto[1]	auto[0]	14	1		T29	1		T18	1		T39	1
all_values[16]	auto[0]	auto[1]	auto[1]	52	1		T7	1		T8	1		T27	4
all_values[16]	auto[1]	auto[0]	auto[1]	61	1		T7	1		T8	3		T27	2
all_values[16]	auto[1]	auto[1]	auto[1]	41	1		T8	1		T27	1		T18	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal