Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	247	1		T9	8		T24	8		T25	8
all_values[1]	247	1		T9	8		T24	8		T25	8
all_values[2]	247	1		T9	8		T24	8		T25	8
all_values[3]	247	1		T9	8		T24	8		T25	8
all_values[4]	247	1		T9	8		T24	8		T25	8
all_values[5]	247	1		T9	8		T24	8		T25	8
all_values[6]	247	1		T9	8		T24	8		T25	8
all_values[7]	247	1		T9	8		T24	8		T25	8
all_values[8]	247	1		T9	8		T24	8		T25	8
all_values[9]	247	1		T9	8		T24	8		T25	8
all_values[10]	247	1		T9	8		T24	8		T25	8
all_values[11]	247	1		T9	8		T24	8		T25	8
all_values[12]	247	1		T9	8		T24	8		T25	8
all_values[13]	247	1		T9	8		T24	8		T25	8
all_values[14]	247	1		T9	8		T24	8		T25	8
all_values[15]	247	1		T9	8		T24	8		T25	8
all_values[16]	247	1		T9	8		T24	8		T25	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2430	1		T9	61		T24	75		T25	79
auto[1]	1769	1		T9	75		T24	61		T25	57

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1177	1		T9	15		T24	32		T25	14
auto[1]	3022	1		T9	121		T24	104		T25	122

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	50	1		T9	1		T25	1		T26	1
all_values[0]	auto[0]	auto[1]	84	1		T9	2		T24	5		T25	1
all_values[0]	auto[1]	auto[0]	11	1		T19	2		T72	1		T73	2
all_values[0]	auto[1]	auto[1]	102	1		T9	5		T24	3		T25	6
all_values[1]	auto[0]	auto[0]	50	1		T17	2		T74	4		T32	2
all_values[1]	auto[0]	auto[1]	86	1		T9	1		T24	3		T25	5
all_values[1]	auto[1]	auto[0]	17	1		T9	1		T25	1		T74	1
all_values[1]	auto[1]	auto[1]	94	1		T9	6		T24	5		T25	2
all_values[2]	auto[0]	auto[0]	57	1		T9	1		T24	4		T17	2
all_values[2]	auto[0]	auto[1]	91	1		T25	5		T26	4		T66	1
all_values[2]	auto[1]	auto[0]	17	1		T9	2		T24	4		T26	1
all_values[2]	auto[1]	auto[1]	82	1		T9	5		T25	3		T26	3
all_values[3]	auto[0]	auto[0]	46	1		T24	1		T25	1		T17	2
all_values[3]	auto[0]	auto[1]	102	1		T9	2		T24	4		T25	6
all_values[3]	auto[1]	auto[0]	16	1		T9	1		T24	1		T19	1
all_values[3]	auto[1]	auto[1]	83	1		T9	5		T24	2		T25	1
all_values[4]	auto[0]	auto[0]	49	1		T24	1		T25	1		T26	1
all_values[4]	auto[0]	auto[1]	95	1		T9	5		T24	5		T25	3
all_values[4]	auto[1]	auto[0]	10	1		T25	3		T26	1		T19	1
all_values[4]	auto[1]	auto[1]	93	1		T9	3		T24	2		T25	1
all_values[5]	auto[0]	auto[0]	51	1		T26	5		T17	2		T32	2
all_values[5]	auto[0]	auto[1]	92	1		T9	3		T24	3		T25	6
all_values[5]	auto[1]	auto[0]	21	1		T26	3		T19	1		T72	5
all_values[5]	auto[1]	auto[1]	83	1		T9	5		T24	5		T25	2
all_values[6]	auto[0]	auto[0]	54	1		T66	2		T17	2		T75	1
all_values[6]	auto[0]	auto[1]	104	1		T9	4		T24	7		T25	7
all_values[6]	auto[1]	auto[0]	26	1		T9	1		T24	1		T66	3
all_values[6]	auto[1]	auto[1]	63	1		T9	3		T25	1		T26	2
all_values[7]	auto[0]	auto[0]	51	1		T25	1		T26	1		T66	2
all_values[7]	auto[0]	auto[1]	82	1		T9	5		T24	5		T25	5
all_values[7]	auto[1]	auto[0]	21	1		T24	2		T25	2		T26	2
all_values[7]	auto[1]	auto[1]	93	1		T9	3		T24	1		T26	4
all_values[8]	auto[0]	auto[0]	48	1		T9	1		T17	2		T72	1
all_values[8]	auto[0]	auto[1]	97	1		T9	1		T24	6		T25	6
all_values[8]	auto[1]	auto[0]	13	1		T9	2		T66	1		T76	4
all_values[8]	auto[1]	auto[1]	89	1		T9	4		T24	2		T25	2
all_values[9]	auto[0]	auto[0]	56	1		T9	1		T66	1		T17	2
all_values[9]	auto[0]	auto[1]	89	1		T9	5		T24	1		T25	2
all_values[9]	auto[1]	auto[0]	10	1		T9	1		T26	2		T19	1
all_values[9]	auto[1]	auto[1]	92	1		T9	1		T24	7		T25	6
all_values[10]	auto[0]	auto[0]	52	1		T24	1		T26	1		T19	1
all_values[10]	auto[0]	auto[1]	76	1		T9	4		T24	3		T25	5
all_values[10]	auto[1]	auto[0]	23	1		T24	1		T72	1		T77	4
all_values[10]	auto[1]	auto[1]	96	1		T9	4		T24	3		T25	3
all_values[11]	auto[0]	auto[0]	65	1		T66	1		T19	1		T17	2
all_values[11]	auto[0]	auto[1]	88	1		T9	6		T24	5		T25	6
all_values[11]	auto[1]	auto[0]	21	1		T66	1		T73	3		T77	4
all_values[11]	auto[1]	auto[1]	73	1		T9	2		T24	3		T25	2
all_values[12]	auto[0]	auto[0]	46	1		T24	2		T25	1		T19	1
all_values[12]	auto[0]	auto[1]	88	1		T9	5		T24	3		T25	1
all_values[12]	auto[1]	auto[0]	17	1		T9	1		T24	2		T25	1
all_values[12]	auto[1]	auto[1]	96	1		T9	2		T24	1		T25	5
all_values[13]	auto[0]	auto[0]	56	1		T19	1		T17	2		T75	5
all_values[13]	auto[0]	auto[1]	82	1		T9	6		T24	6		T25	5
all_values[13]	auto[1]	auto[0]	11	1		T24	1		T25	1		T26	1
all_values[13]	auto[1]	auto[1]	98	1		T9	2		T24	1		T25	2
all_values[14]	auto[0]	auto[0]	69	1		T9	1		T24	3		T25	1
all_values[14]	auto[0]	auto[1]	75	1		T9	4		T24	1		T25	1
all_values[14]	auto[1]	auto[0]	16	1		T9	1		T72	1		T77	1
all_values[14]	auto[1]	auto[1]	87	1		T9	2		T24	4		T25	6
all_values[15]	auto[0]	auto[0]	49	1		T26	1		T17	2		T74	2
all_values[15]	auto[0]	auto[1]	102	1		T9	3		T24	1		T25	3
all_values[15]	auto[1]	auto[0]	8	1		T74	1		T78	2		T79	1
all_values[15]	auto[1]	auto[1]	88	1		T9	5		T24	7		T25	5
all_values[16]	auto[0]	auto[0]	55	1		T24	5		T26	2		T17	2
all_values[16]	auto[0]	auto[1]	93	1		T25	6		T66	4		T19	1
all_values[16]	auto[1]	auto[0]	15	1		T24	3		T26	3		T66	1
all_values[16]	auto[1]	auto[1]	84	1		T9	8		T25	2		T26	3