Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.44	90.20	75.51	97.14	3.12	87.06	92.78	96.28

Total tests in report: 144

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
49.96	49.96	72.10	72.10	44.31	44.31	81.21	81.21	3.12	3.12	58.13	58.13	86.39	86.39	4.46	4.46	/workspace/coverage/default/3.usbdev_sec_cm.4286017419
63.07	13.10	84.00	11.90	71.12	26.81	86.37	5.16	3.12	0.00	85.17	27.04	88.25	1.86	23.42	18.96	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2950299348
71.62	8.56	89.87	5.87	72.83	1.71	91.98	5.60	3.12	0.00	86.72	1.55	88.45	0.21	68.40	44.98	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.122678578
73.92	2.30	89.91	0.04	73.62	0.79	94.84	2.86	3.12	0.00	86.76	0.04	89.48	1.03	79.74	11.34	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.745711489
74.93	1.01	90.29	0.38	73.62	0.00	94.84	0.00	3.12	0.00	86.76	0.00	89.48	0.00	86.43	6.69	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3403540776
75.84	0.91	90.31	0.02	73.85	0.23	96.04	1.21	3.12	0.00	86.80	0.04	89.48	0.00	91.26	4.83	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1919302914
76.22	0.38	90.31	0.00	73.85	0.00	96.04	0.00	3.12	0.00	86.80	0.00	92.16	2.68	91.26	0.00	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2260499014
76.54	0.32	90.31	0.00	73.85	0.00	96.04	0.00	3.12	0.00	86.80	0.00	92.16	0.00	93.49	2.23	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3118138290
76.79	0.25	90.33	0.02	74.95	1.10	96.48	0.44	3.12	0.00	87.02	0.21	92.16	0.00	93.49	0.00	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3261567139
76.95	0.16	90.33	0.00	74.95	0.00	96.48	0.00	3.12	0.00	87.02	0.00	92.16	0.00	94.61	1.12	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.3100549071
77.06	0.11	90.33	0.00	75.08	0.13	96.48	0.00	3.12	0.00	87.02	0.00	92.78	0.62	94.61	0.00	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3676719447
77.15	0.09	90.52	0.19	75.48	0.41	96.48	0.00	3.12	0.00	87.02	0.00	92.78	0.00	94.61	0.00	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.473363822
77.23	0.08	90.52	0.00	75.48	0.00	96.48	0.00	3.12	0.00	87.02	0.00	92.78	0.00	95.17	0.56	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1769635981
77.29	0.06	90.52	0.00	75.48	0.00	96.92	0.44	3.12	0.00	87.02	0.00	92.78	0.00	95.17	0.00	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.492898006
77.34	0.05	90.52	0.00	75.48	0.00	96.92	0.00	3.12	0.00	87.02	0.00	92.78	0.00	95.54	0.37	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4206154694
77.39	0.05	90.58	0.06	75.48	0.00	97.14	0.22	3.12	0.00	87.06	0.04	92.78	0.00	95.54	0.00	/workspace/coverage/default/2.usbdev_sec_cm.2862298670
77.41	0.03	90.58	0.00	75.48	0.00	97.14	0.00	3.12	0.00	87.06	0.00	92.78	0.00	95.72	0.19	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.739276695
77.44	0.03	90.58	0.00	75.48	0.00	97.14	0.00	3.12	0.00	87.06	0.00	92.78	0.00	95.91	0.19	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.4062006646
77.47	0.03	90.58	0.00	75.48	0.00	97.14	0.00	3.12	0.00	87.06	0.00	92.78	0.00	96.10	0.19	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3012001289
77.49	0.03	90.58	0.00	75.48	0.00	97.14	0.00	3.12	0.00	87.06	0.00	92.78	0.00	96.28	0.19	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3484672384
77.50	0.01	90.58	0.00	75.51	0.03	97.14	0.00	3.12	0.00	87.06	0.00	92.78	0.00	96.28	0.00	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3515431501

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1558508363
/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2641318647
/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1892958976
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3861978633
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1807214937
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2038386391
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.301082967
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1513792788
/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1587461945
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2943877186
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4201666204
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1599177447
/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2123499267
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2547245983
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4105625510
/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.319908799
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.778928473
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.173333298
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.98665845
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.25035945
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2370642803
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1513208727
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3957203055
/workspace/coverage/cover_reg_top/11.usbdev_intr_test.2874287337
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3494626397
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3972789545
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.990560928
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2781844694
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.715138445
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2959811930
/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1268640241
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.286508560
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3216182070
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.393876026
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2929264409
/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3614373944
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2601580113
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.430942437
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1256967118
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2540989733
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3700628601
/workspace/coverage/cover_reg_top/15.usbdev_intr_test.4265370210
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.195523263
/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3834673872
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2134939886
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1003225833
/workspace/coverage/cover_reg_top/16.usbdev_intr_test.5851519
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1425181983
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.425850273
/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.879405475
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.20600756
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4172441641
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3249987710
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1490425774
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.267389767
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.995578381
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.432045621
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1372972537
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.921634271
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2515755290
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2782251747
/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2071303517
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.258905255
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2726438662
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.2660603283
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2090264742
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1546412654
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3686817689
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.829269696
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.59449083
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.3258443320
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2728024964
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.3964059491
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.909589566
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1414717792
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.884106705
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1820729866
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1081356189
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2497563638
/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2730345343
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.820549700
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.1196790510
/workspace/coverage/cover_reg_top/35.usbdev_intr_test.4158338345
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1164149767
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2864777502
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2411902306
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1174366919
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1911476083
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2107440714
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.355789722
/workspace/coverage/cover_reg_top/41.usbdev_intr_test.234165706
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.680176652
/workspace/coverage/cover_reg_top/45.usbdev_intr_test.632593882
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.2816834331
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2910528888
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.299364928
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.376173334
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.4270643189
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.2667504527
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1565758109
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1616204497
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3852874609
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4287172488
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.985835184
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2332639396
/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2769672836
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1033088071
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1551753449
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1670242753
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4072662964
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.527327679
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3128104144
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2259207193
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1806953578
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2293038463
/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3196198633
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.450930050
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3513320426
/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2469652472
/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2221342569
/workspace/coverage/default/0.usbdev_sec_cm.3454016489
/workspace/coverage/default/1.usbdev_sec_cm.1560929729
/workspace/coverage/default/4.usbdev_sec_cm.2239496169

Total test records in report: 144

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.usbdev_sec_cm.2862298670	Jan 24 11:37:57 PM PST 24	Jan 24 11:37:59 PM PST 24	138752563 ps
T2	/workspace/coverage/default/4.usbdev_sec_cm.2239496169	Jan 24 10:43:05 PM PST 24	Jan 24 10:43:07 PM PST 24	87614074 ps
T3	/workspace/coverage/default/3.usbdev_sec_cm.4286017419	Jan 24 10:43:04 PM PST 24	Jan 24 10:43:06 PM PST 24	87847240 ps
T4	/workspace/coverage/default/0.usbdev_sec_cm.3454016489	Jan 24 10:42:11 PM PST 24	Jan 24 10:42:13 PM PST 24	149439128 ps
T5	/workspace/coverage/default/1.usbdev_sec_cm.1560929729	Jan 25 12:52:23 AM PST 24	Jan 25 12:52:25 AM PST 24	104604806 ps
T6	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.20600756	Jan 24 01:59:20 PM PST 24	Jan 24 01:59:23 PM PST 24	45635465 ps
T7	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4201666204	Jan 24 01:02:18 PM PST 24	Jan 24 01:02:27 PM PST 24	46170317 ps
T8	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.301082967	Jan 24 01:02:18 PM PST 24	Jan 24 01:02:30 PM PST 24	151433826 ps
T9	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.122678578	Jan 24 01:03:54 PM PST 24	Jan 24 01:04:37 PM PST 24	105755306 ps
T10	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3676719447	Jan 24 03:15:56 PM PST 24	Jan 24 03:15:58 PM PST 24	60619460 ps
T20	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2497563638	Jan 24 01:02:31 PM PST 24	Jan 24 01:02:39 PM PST 24	56408120 ps
T21	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4105625510	Jan 24 02:32:28 PM PST 24	Jan 24 02:33:01 PM PST 24	101347721 ps
T11	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1892958976	Jan 24 01:02:27 PM PST 24	Jan 24 01:02:34 PM PST 24	33029164 ps
T27	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3513320426	Jan 24 01:03:23 PM PST 24	Jan 24 01:03:52 PM PST 24	35560325 ps
T28	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2781844694	Jan 24 01:03:21 PM PST 24	Jan 24 01:03:48 PM PST 24	33778940 ps
T12	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2950299348	Jan 24 01:03:21 PM PST 24	Jan 24 01:03:49 PM PST 24	74071201 ps
T29	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.4270643189	Jan 24 01:23:26 PM PST 24	Jan 24 01:24:14 PM PST 24	31756687 ps
T24	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.4265370210	Jan 24 01:03:43 PM PST 24	Jan 24 01:04:24 PM PST 24	32913025 ps
T30	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.921634271	Jan 24 01:19:05 PM PST 24	Jan 24 01:20:06 PM PST 24	66991505 ps
T25	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.632593882	Jan 24 01:48:33 PM PST 24	Jan 24 01:48:37 PM PST 24	22011976 ps
T26	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3403540776	Jan 24 01:03:58 PM PST 24	Jan 24 01:04:41 PM PST 24	27480152 ps
T66	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.3964059491	Jan 24 01:11:39 PM PST 24	Jan 24 01:12:28 PM PST 24	25784533 ps
T22	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1919302914	Jan 24 01:03:51 PM PST 24	Jan 24 01:04:36 PM PST 24	254527570 ps
T31	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3216182070	Jan 24 01:15:14 PM PST 24	Jan 24 01:15:53 PM PST 24	46341797 ps
T49	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.739276695	Jan 24 01:03:22 PM PST 24	Jan 24 01:03:51 PM PST 24	132149470 ps
T13	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2038386391	Jan 24 01:02:33 PM PST 24	Jan 24 01:02:40 PM PST 24	178403045 ps
T18	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.492898006	Jan 24 01:02:31 PM PST 24	Jan 24 01:02:38 PM PST 24	50546569 ps
T14	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.432045621	Jan 24 01:03:51 PM PST 24	Jan 24 01:04:34 PM PST 24	50962628 ps
T15	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3128104144	Jan 24 01:03:24 PM PST 24	Jan 24 01:03:54 PM PST 24	30777052 ps
T19	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2728024964	Jan 24 01:49:29 PM PST 24	Jan 24 01:49:33 PM PST 24	27917189 ps
T16	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3700628601	Jan 24 01:39:03 PM PST 24	Jan 24 01:39:09 PM PST 24	35195169 ps
T52	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1558508363	Jan 24 01:11:41 PM PST 24	Jan 24 01:12:31 PM PST 24	223606740 ps
T17	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.745711489	Jan 24 01:02:32 PM PST 24	Jan 24 01:02:40 PM PST 24	169049758 ps
T41	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.985835184	Jan 24 01:13:41 PM PST 24	Jan 24 01:14:06 PM PST 24	72657037 ps
T42	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1372972537	Jan 24 01:03:43 PM PST 24	Jan 24 01:04:26 PM PST 24	32645541 ps
T43	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.173333298	Jan 24 01:03:20 PM PST 24	Jan 24 01:03:47 PM PST 24	53627848 ps
T44	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2641318647	Jan 24 01:02:25 PM PST 24	Jan 24 01:02:34 PM PST 24	285208289 ps
T45	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.884106705	Jan 24 01:24:18 PM PST 24	Jan 24 01:24:52 PM PST 24	35895799 ps
T46	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2769672836	Jan 24 01:28:37 PM PST 24	Jan 24 01:29:02 PM PST 24	332366674 ps
T47	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.879405475	Jan 24 01:03:39 PM PST 24	Jan 24 01:04:17 PM PST 24	285184308 ps
T53	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.430942437	Jan 24 01:31:38 PM PST 24	Jan 24 01:32:30 PM PST 24	29968939 ps
T50	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2221342569	Jan 24 01:03:22 PM PST 24	Jan 24 01:03:53 PM PST 24	414173786 ps
T74	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.3100549071	Jan 24 01:03:58 PM PST 24	Jan 24 01:04:41 PM PST 24	29588838 ps
T89	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1174366919	Jan 24 01:02:47 PM PST 24	Jan 24 01:03:06 PM PST 24	65378792 ps
T72	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2123499267	Jan 24 01:02:21 PM PST 24	Jan 24 01:02:28 PM PST 24	24877029 ps
T71	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1769635981	Jan 24 01:29:43 PM PST 24	Jan 24 01:30:00 PM PST 24	290704196 ps
T63	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1033088071	Jan 24 01:03:21 PM PST 24	Jan 24 01:03:48 PM PST 24	40111423 ps
T73	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1164149767	Jan 24 01:03:54 PM PST 24	Jan 24 01:04:37 PM PST 24	26032527 ps
T90	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1414717792	Jan 24 01:02:33 PM PST 24	Jan 24 01:02:40 PM PST 24	54094971 ps
T91	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4172441641	Jan 24 01:45:52 PM PST 24	Jan 24 01:46:13 PM PST 24	37388741 ps
T92	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.778928473	Jan 24 01:03:27 PM PST 24	Jan 24 01:03:58 PM PST 24	71229432 ps
T64	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.376173334	Jan 24 01:03:06 PM PST 24	Jan 24 01:03:30 PM PST 24	53746822 ps
T54	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2547245983	Jan 24 01:12:24 PM PST 24	Jan 24 01:13:16 PM PST 24	187488053 ps
T93	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1425181983	Jan 24 01:40:16 PM PST 24	Jan 24 01:41:14 PM PST 24	48065568 ps
T94	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.286508560	Jan 24 01:03:38 PM PST 24	Jan 24 01:04:16 PM PST 24	41782253 ps
T75	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.680176652	Jan 24 01:04:01 PM PST 24	Jan 24 01:04:44 PM PST 24	39456850 ps
T32	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.355789722	Jan 24 01:02:52 PM PST 24	Jan 24 01:03:14 PM PST 24	104685866 ps
T48	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.909589566	Jan 24 01:15:48 PM PST 24	Jan 24 01:16:36 PM PST 24	309203557 ps
T77	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.59449083	Jan 24 01:03:46 PM PST 24	Jan 24 01:04:27 PM PST 24	22165545 ps
T95	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3957203055	Jan 24 01:03:21 PM PST 24	Jan 24 01:03:49 PM PST 24	43015918 ps
T96	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1513792788	Jan 24 01:02:28 PM PST 24	Jan 24 01:02:35 PM PST 24	37421355 ps
T55	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2260499014	Jan 24 01:03:40 PM PST 24	Jan 24 01:04:18 PM PST 24	59588314 ps
T97	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1565758109	Jan 24 01:50:46 PM PST 24	Jan 24 01:50:49 PM PST 24	36838543 ps
T98	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3861978633	Jan 24 01:02:23 PM PST 24	Jan 24 01:02:29 PM PST 24	37494988 ps
T56	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2090264742	Jan 24 01:02:35 PM PST 24	Jan 24 01:02:43 PM PST 24	169977893 ps
T33	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2332639396	Jan 24 01:03:06 PM PST 24	Jan 24 01:03:32 PM PST 24	231439628 ps
T78	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.5851519	Jan 24 01:03:46 PM PST 24	Jan 24 01:04:28 PM PST 24	33198141 ps
T62	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1003225833	Jan 24 01:57:14 PM PST 24	Jan 24 01:57:16 PM PST 24	37652997 ps
T59	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2107440714	Jan 24 01:09:34 PM PST 24	Jan 24 01:10:15 PM PST 24	40165206 ps
T99	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1081356189	Jan 24 01:02:35 PM PST 24	Jan 24 01:02:45 PM PST 24	149927711 ps
T51	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3614373944	Jan 24 01:03:21 PM PST 24	Jan 24 01:03:49 PM PST 24	128290892 ps
T34	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2515755290	Jan 24 01:03:39 PM PST 24	Jan 24 01:04:17 PM PST 24	238222758 ps
T80	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.299364928	Jan 24 01:03:50 PM PST 24	Jan 24 01:04:33 PM PST 24	24936396 ps
T35	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2370642803	Jan 24 01:03:24 PM PST 24	Jan 24 01:03:55 PM PST 24	80289321 ps
T65	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1490425774	Jan 24 03:58:51 PM PST 24	Jan 24 03:58:53 PM PST 24	66203994 ps
T100	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3686817689	Jan 24 01:02:35 PM PST 24	Jan 24 01:02:43 PM PST 24	117956274 ps
T36	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2959811930	Jan 24 01:03:20 PM PST 24	Jan 24 01:03:47 PM PST 24	51990433 ps
T37	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.473363822	Jan 24 01:03:34 PM PST 24	Jan 24 01:04:12 PM PST 24	292458516 ps
T60	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2943877186	Jan 24 01:02:25 PM PST 24	Jan 24 01:02:32 PM PST 24	114530434 ps
T76	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.1196790510	Jan 24 01:45:16 PM PST 24	Jan 24 01:45:25 PM PST 24	26931223 ps
T101	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3494626397	Jan 24 01:03:24 PM PST 24	Jan 24 01:03:54 PM PST 24	42085986 ps
T85	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.2660603283	Jan 24 01:13:33 PM PST 24	Jan 24 01:13:59 PM PST 24	46319637 ps
T81	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1911476083	Jan 24 01:02:51 PM PST 24	Jan 24 01:03:12 PM PST 24	21363793 ps
T102	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.267389767	Jan 24 01:03:39 PM PST 24	Jan 24 01:04:15 PM PST 24	33403185 ps
T23	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3261567139	Jan 24 01:22:48 PM PST 24	Jan 24 01:23:45 PM PST 24	68486628 ps
T103	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3852874609	Jan 24 01:18:41 PM PST 24	Jan 24 01:19:22 PM PST 24	30438995 ps
T104	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1268640241	Jan 24 01:03:22 PM PST 24	Jan 24 01:03:51 PM PST 24	184644654 ps
T67	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1587461945	Jan 24 01:02:05 PM PST 24	Jan 24 01:02:15 PM PST 24	332552176 ps
T105	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.715138445	Jan 24 01:03:22 PM PST 24	Jan 24 01:03:49 PM PST 24	75016223 ps
T82	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3118138290	Jan 24 01:08:22 PM PST 24	Jan 24 01:08:58 PM PST 24	24102055 ps
T38	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2469652472	Jan 24 01:03:22 PM PST 24	Jan 24 01:03:50 PM PST 24	109354979 ps
T39	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3196198633	Jan 24 01:03:18 PM PST 24	Jan 24 01:03:48 PM PST 24	271895909 ps
T61	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1820729866	Jan 24 01:02:45 PM PST 24	Jan 24 01:03:05 PM PST 24	152002838 ps
T79	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.3258443320	Jan 24 01:03:54 PM PST 24	Jan 24 01:04:37 PM PST 24	43108574 ps
T106	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1256967118	Jan 24 01:03:46 PM PST 24	Jan 24 01:04:29 PM PST 24	51523036 ps
T68	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.450930050	Jan 24 01:03:22 PM PST 24	Jan 24 01:03:49 PM PST 24	144586172 ps
T40	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3515431501	Jan 24 01:02:15 PM PST 24	Jan 24 01:02:19 PM PST 24	192788805 ps
T107	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4287172488	Jan 24 01:03:05 PM PST 24	Jan 24 01:03:29 PM PST 24	86001463 ps
T108	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.527327679	Jan 24 01:19:07 PM PST 24	Jan 24 01:20:10 PM PST 24	122154730 ps
T109	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.990560928	Jan 24 01:03:26 PM PST 24	Jan 24 01:03:59 PM PST 24	44734846 ps
T110	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1670242753	Jan 24 01:03:11 PM PST 24	Jan 24 01:03:34 PM PST 24	24868737 ps
T111	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2730345343	Jan 24 01:02:46 PM PST 24	Jan 24 01:03:07 PM PST 24	351543687 ps
T112	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1513208727	Jan 24 01:03:22 PM PST 24	Jan 24 01:03:51 PM PST 24	35843593 ps
T113	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2540989733	Jan 24 01:03:51 PM PST 24	Jan 24 01:04:36 PM PST 24	99607139 ps
T114	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2134939886	Jan 24 01:20:03 PM PST 24	Jan 24 01:21:07 PM PST 24	30588950 ps
T86	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.4158338345	Jan 24 01:03:54 PM PST 24	Jan 24 01:04:36 PM PST 24	21501834 ps
T115	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2259207193	Jan 24 01:03:21 PM PST 24	Jan 24 01:03:48 PM PST 24	40671623 ps
T116	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2910528888	Jan 24 01:04:02 PM PST 24	Jan 24 01:04:47 PM PST 24	30268280 ps
T57	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1599177447	Jan 24 01:22:47 PM PST 24	Jan 24 01:23:44 PM PST 24	43744233 ps
T117	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2864777502	Jan 24 01:29:42 PM PST 24	Jan 24 01:29:58 PM PST 24	169190744 ps
T118	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2782251747	Jan 24 01:02:31 PM PST 24	Jan 24 01:02:41 PM PST 24	304243711 ps
T83	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4206154694	Jan 24 01:03:51 PM PST 24	Jan 24 01:04:34 PM PST 24	30770280 ps
T119	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2411902306	Jan 24 01:03:06 PM PST 24	Jan 24 01:03:30 PM PST 24	33133665 ps
T120	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4072662964	Jan 24 01:03:05 PM PST 24	Jan 24 01:03:29 PM PST 24	42844904 ps
T121	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.829269696	Jan 24 01:03:36 PM PST 24	Jan 24 01:04:10 PM PST 24	29044786 ps
T58	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2726438662	Jan 24 01:02:33 PM PST 24	Jan 24 01:02:40 PM PST 24	46212907 ps
T122	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2601580113	Jan 24 01:11:35 PM PST 24	Jan 24 01:12:22 PM PST 24	57220194 ps
T123	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2929264409	Jan 24 01:03:26 PM PST 24	Jan 24 01:04:00 PM PST 24	304489293 ps
T124	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.319908799	Jan 24 01:16:07 PM PST 24	Jan 24 01:16:48 PM PST 24	94573344 ps
T125	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2071303517	Jan 24 01:02:33 PM PST 24	Jan 24 01:02:47 PM PST 24	365824015 ps
T126	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.234165706	Jan 24 01:03:50 PM PST 24	Jan 24 01:04:34 PM PST 24	32098520 ps
T127	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3972789545	Jan 24 01:03:19 PM PST 24	Jan 24 01:03:46 PM PST 24	67571611 ps
T128	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2293038463	Jan 24 01:03:26 PM PST 24	Jan 24 01:03:59 PM PST 24	107968692 ps
T129	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.258905255	Jan 24 01:02:32 PM PST 24	Jan 24 01:02:39 PM PST 24	28721558 ps
T130	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3249987710	Jan 24 01:03:43 PM PST 24	Jan 24 01:04:26 PM PST 24	70902782 ps
T131	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1807214937	Jan 24 01:02:05 PM PST 24	Jan 24 01:02:11 PM PST 24	29582731 ps
T132	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1616204497	Jan 24 01:12:25 PM PST 24	Jan 24 01:13:19 PM PST 24	209864393 ps
T133	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1551753449	Jan 24 01:22:59 PM PST 24	Jan 24 01:23:53 PM PST 24	77750018 ps
T70	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3484672384	Jan 24 01:16:34 PM PST 24	Jan 24 01:17:20 PM PST 24	301542241 ps
T134	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.425850273	Jan 24 01:41:44 PM PST 24	Jan 24 01:41:50 PM PST 24	295458208 ps
T135	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.2874287337	Jan 24 01:03:21 PM PST 24	Jan 24 01:03:49 PM PST 24	48752097 ps
T136	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.393876026	Jan 24 01:03:39 PM PST 24	Jan 24 01:04:17 PM PST 24	96030034 ps
T137	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1806953578	Jan 24 01:03:19 PM PST 24	Jan 24 01:03:45 PM PST 24	65970958 ps
T87	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.820549700	Jan 24 01:03:52 PM PST 24	Jan 24 01:04:34 PM PST 24	26721892 ps
T138	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.4062006646	Jan 24 01:03:25 PM PST 24	Jan 24 01:03:55 PM PST 24	24873256 ps
T139	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.25035945	Jan 24 01:03:26 PM PST 24	Jan 24 01:03:56 PM PST 24	42382515 ps
T140	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.2667504527	Jan 24 02:05:21 PM PST 24	Jan 24 02:06:12 PM PST 24	25115359 ps
T88	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3834673872	Jan 24 01:03:43 PM PST 24	Jan 24 01:04:29 PM PST 24	251684232 ps
T141	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.995578381	Jan 24 01:03:38 PM PST 24	Jan 24 01:04:17 PM PST 24	117119774 ps
T84	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.98665845	Jan 24 01:03:26 PM PST 24	Jan 24 01:03:56 PM PST 24	31936043 ps
T142	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.2816834331	Jan 24 01:04:02 PM PST 24	Jan 24 01:04:47 PM PST 24	25501817 ps
T143	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1546412654	Jan 24 01:02:33 PM PST 24	Jan 24 01:02:42 PM PST 24	150341083 ps
T144	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.195523263	Jan 24 01:37:46 PM PST 24	Jan 24 01:38:16 PM PST 24	190096333 ps
T69	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3012001289	Jan 24 01:02:22 PM PST 24	Jan 24 01:02:32 PM PST 24	245820041 ps

Test location	/workspace/coverage/default/3.usbdev_sec_cm.4286017419
Short name	T3
Test name
Test status
Simulation time	87847240 ps
CPU time	0.89 seconds
Started	Jan 24 10:43:04 PM PST 24
Finished	Jan 24 10:43:06 PM PST 24
Peak memory	220344 kb
Host	smart-d4d64304-4b04-41f0-9fcc-0e819d4e2c0c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4286017419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.4286017419
Directory	/workspace/3.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2950299348
Short name	T12
Test name
Test status
Simulation time	74071201 ps
CPU time	2.27 seconds
Started	Jan 24 01:03:21 PM PST 24
Finished	Jan 24 01:03:49 PM PST 24
Peak memory	209528 kb
Host	smart-86670af0-e203-4bc0-96e7-7cc048c6d0b3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950299348 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.2950299348
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.122678578
Short name	T9
Test name
Test status
Simulation time	105755306 ps
CPU time	0.72 seconds
Started	Jan 24 01:03:54 PM PST 24
Finished	Jan 24 01:04:37 PM PST 24
Peak memory	200300 kb
Host	smart-7b1bd990-9739-44e1-990f-ddf0ca023d42
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=122678578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.122678578
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.745711489
Short name	T17
Test name
Test status
Simulation time	169049758 ps
CPU time	1.92 seconds
Started	Jan 24 01:02:32 PM PST 24
Finished	Jan 24 01:02:40 PM PST 24
Peak memory	201176 kb
Host	smart-4c3e8f66-9e94-4f7c-820f-ef358af30ea6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=745711489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.745711489
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3403540776
Short name	T26
Test name
Test status
Simulation time	27480152 ps
CPU time	0.71 seconds
Started	Jan 24 01:03:58 PM PST 24
Finished	Jan 24 01:04:41 PM PST 24
Peak memory	200200 kb
Host	smart-57e2c0ee-b507-4cdb-903b-6d7a623da675
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3403540776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3403540776
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1919302914
Short name	T22
Test name
Test status
Simulation time	254527570 ps
CPU time	2.74 seconds
Started	Jan 24 01:03:51 PM PST 24
Finished	Jan 24 01:04:36 PM PST 24
Peak memory	200828 kb
Host	smart-7a803c82-43f9-474d-8a6c-c58e49a871e6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1919302914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1919302914
Directory	/workspace/18.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2260499014
Short name	T55
Test name
Test status
Simulation time	59588314 ps
CPU time	0.97 seconds
Started	Jan 24 01:03:40 PM PST 24
Finished	Jan 24 01:04:18 PM PST 24
Peak memory	201116 kb
Host	smart-7840f74c-7484-44d3-b252-fbf982b50c6b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260499014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2260499014
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3118138290
Short name	T82
Test name
Test status
Simulation time	24102055 ps
CPU time	0.61 seconds
Started	Jan 24 01:08:22 PM PST 24
Finished	Jan 24 01:08:58 PM PST 24
Peak memory	200324 kb
Host	smart-8ecd525f-98ab-4f85-be14-03e3c3baa713
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3118138290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3118138290
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3261567139
Short name	T23
Test name
Test status
Simulation time	68486628 ps
CPU time	0.75 seconds
Started	Jan 24 01:22:48 PM PST 24
Finished	Jan 24 01:23:45 PM PST 24
Peak memory	201112 kb
Host	smart-29a02565-6968-4b5b-bec9-add630acca71
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261567139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3261567139
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.3100549071
Short name	T74
Test name
Test status
Simulation time	29588838 ps
CPU time	0.65 seconds
Started	Jan 24 01:03:58 PM PST 24
Finished	Jan 24 01:04:41 PM PST 24
Peak memory	200212 kb
Host	smart-657572b9-9a19-42d5-8e50-d47326ec702a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3100549071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3100549071
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3676719447
Short name	T10
Test name
Test status
Simulation time	60619460 ps
CPU time	1.44 seconds
Started	Jan 24 03:15:56 PM PST 24
Finished	Jan 24 03:15:58 PM PST 24
Peak memory	201360 kb
Host	smart-ab9128da-2f04-47da-aac0-305599c995b4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676719447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c sr_outstanding.3676719447
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.473363822
Short name	T37
Test name
Test status
Simulation time	292458516 ps
CPU time	3.61 seconds
Started	Jan 24 01:03:34 PM PST 24
Finished	Jan 24 01:04:12 PM PST 24
Peak memory	201288 kb
Host	smart-d5139547-82b1-41b9-90bf-169d48b82407
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=473363822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.473363822
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1769635981
Short name	T71
Test name
Test status
Simulation time	290704196 ps
CPU time	2.93 seconds
Started	Jan 24 01:29:43 PM PST 24
Finished	Jan 24 01:30:00 PM PST 24
Peak memory	201228 kb
Host	smart-200deaf4-f931-4e81-a389-79c6ed059231
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1769635981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1769635981
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.492898006
Short name	T18
Test name
Test status
Simulation time	50546569 ps
CPU time	0.83 seconds
Started	Jan 24 01:02:31 PM PST 24
Finished	Jan 24 01:02:38 PM PST 24
Peak memory	201028 kb
Host	smart-5471dbf1-1c6e-469f-ae6d-a9cea33f5f4c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492898006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.492898006
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4206154694
Short name	T83
Test name
Test status
Simulation time	30770280 ps
CPU time	0.62 seconds
Started	Jan 24 01:03:51 PM PST 24
Finished	Jan 24 01:04:34 PM PST 24
Peak memory	200396 kb
Host	smart-428602ef-7073-4e48-99ab-5d8aacbb3824
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4206154694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4206154694
Directory	/workspace/21.usbdev_intr_test/latest

Test location	/workspace/coverage/default/2.usbdev_sec_cm.2862298670
Short name	T1
Test name
Test status
Simulation time	138752563 ps
CPU time	0.99 seconds
Started	Jan 24 11:37:57 PM PST 24
Finished	Jan 24 11:37:59 PM PST 24
Peak memory	220228 kb
Host	smart-86c8f36a-15fd-47d4-8d99-79e66437160a
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2862298670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2862298670
Directory	/workspace/2.usbdev_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.739276695
Short name	T49
Test name
Test status
Simulation time	132149470 ps
CPU time	2.58 seconds
Started	Jan 24 01:03:22 PM PST 24
Finished	Jan 24 01:03:51 PM PST 24
Peak memory	201168 kb
Host	smart-8e6b18ef-813e-4277-bf26-713ea01c2814
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=739276695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.739276695
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.4062006646
Short name	T138
Test name
Test status
Simulation time	24873256 ps
CPU time	0.62 seconds
Started	Jan 24 01:03:25 PM PST 24
Finished	Jan 24 01:03:55 PM PST 24
Peak memory	200260 kb
Host	smart-ab7b3017-0b2c-44b9-acf6-909b0de19da6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4062006646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.4062006646
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3012001289
Short name	T69
Test name
Test status
Simulation time	245820041 ps
CPU time	4.37 seconds
Started	Jan 24 01:02:22 PM PST 24
Finished	Jan 24 01:02:32 PM PST 24
Peak memory	201204 kb
Host	smart-cdc39bcc-ce22-4b3c-8704-efa8569842b7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3012001289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3012001289
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3484672384
Short name	T70
Test name
Test status
Simulation time	301542241 ps
CPU time	2.95 seconds
Started	Jan 24 01:16:34 PM PST 24
Finished	Jan 24 01:17:20 PM PST 24
Peak memory	201232 kb
Host	smart-a2a2d567-a2dc-4391-bd7a-58fa6382eac0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3484672384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3484672384
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3515431501
Short name	T40
Test name
Test status
Simulation time	192788805 ps
CPU time	2.34 seconds
Started	Jan 24 01:02:15 PM PST 24
Finished	Jan 24 01:02:19 PM PST 24
Peak memory	201284 kb
Host	smart-c2f69dd1-54ac-4baa-b6cb-2770c44c1ac3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3515431501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3515431501
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1558508363
Short name	T52
Test name
Test status
Simulation time	223606740 ps
CPU time	2.18 seconds
Started	Jan 24 01:11:41 PM PST 24
Finished	Jan 24 01:12:31 PM PST 24
Peak memory	201252 kb
Host	smart-3905e832-b092-4a6b-9c0c-86571877627e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558508363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1558508363
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2641318647
Short name	T44
Test name
Test status
Simulation time	285208289 ps
CPU time	4.75 seconds
Started	Jan 24 01:02:25 PM PST 24
Finished	Jan 24 01:02:34 PM PST 24
Peak memory	201072 kb
Host	smart-b5c94787-2d42-4b92-85cd-84235d0da491
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641318647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2641318647
Directory	/workspace/0.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1892958976
Short name	T11
Test name
Test status
Simulation time	33029164 ps
CPU time	0.93 seconds
Started	Jan 24 01:02:27 PM PST 24
Finished	Jan 24 01:02:34 PM PST 24
Peak memory	201184 kb
Host	smart-dd87fdf2-a6da-4ae5-b77b-1654063d4352
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892958976 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.1892958976
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3861978633
Short name	T98
Test name
Test status
Simulation time	37494988 ps
CPU time	0.83 seconds
Started	Jan 24 01:02:23 PM PST 24
Finished	Jan 24 01:02:29 PM PST 24
Peak memory	201020 kb
Host	smart-5500de0e-b1cd-487d-a31d-dc008f03b0db
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861978633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3861978633
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1807214937
Short name	T131
Test name
Test status
Simulation time	29582731 ps
CPU time	0.65 seconds
Started	Jan 24 01:02:05 PM PST 24
Finished	Jan 24 01:02:11 PM PST 24
Peak memory	200368 kb
Host	smart-31baa8c1-3aa8-4db8-bdc7-51fa7c89e726
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1807214937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1807214937
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2038386391
Short name	T13
Test name
Test status
Simulation time	178403045 ps
CPU time	2.26 seconds
Started	Jan 24 01:02:33 PM PST 24
Finished	Jan 24 01:02:40 PM PST 24
Peak memory	201264 kb
Host	smart-e0515b95-c08d-4e9a-b694-421bc6fa1843
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2038386391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2038386391
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.301082967
Short name	T8
Test name
Test status
Simulation time	151433826 ps
CPU time	3.68 seconds
Started	Jan 24 01:02:18 PM PST 24
Finished	Jan 24 01:02:30 PM PST 24
Peak memory	201156 kb
Host	smart-887acae3-0454-440c-8380-91b30436aacd
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=301082967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.301082967
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1513792788
Short name	T96
Test name
Test status
Simulation time	37421355 ps
CPU time	1.04 seconds
Started	Jan 24 01:02:28 PM PST 24
Finished	Jan 24 01:02:35 PM PST 24
Peak memory	201140 kb
Host	smart-9e71804e-31a2-44f4-b2b6-c7c1a2b006ec
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513792788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_c sr_outstanding.1513792788
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1587461945
Short name	T67
Test name
Test status
Simulation time	332552176 ps
CPU time	3.07 seconds
Started	Jan 24 01:02:05 PM PST 24
Finished	Jan 24 01:02:15 PM PST 24
Peak memory	201164 kb
Host	smart-6573270b-cc9a-47ac-a36d-ab6305bfb9b1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1587461945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1587461945
Directory	/workspace/0.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2943877186
Short name	T60
Test name
Test status
Simulation time	114530434 ps
CPU time	3.17 seconds
Started	Jan 24 01:02:25 PM PST 24
Finished	Jan 24 01:02:32 PM PST 24
Peak memory	200356 kb
Host	smart-a54ccc72-e4b7-41ad-a019-93cafdb01bb6
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943877186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2943877186
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4201666204
Short name	T7
Test name
Test status
Simulation time	46170317 ps
CPU time	1.07 seconds
Started	Jan 24 01:02:18 PM PST 24
Finished	Jan 24 01:02:27 PM PST 24
Peak memory	201236 kb
Host	smart-20779b2f-b03c-44d7-824b-df3d89eed584
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201666204 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.4201666204
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1599177447
Short name	T57
Test name
Test status
Simulation time	43744233 ps
CPU time	0.82 seconds
Started	Jan 24 01:22:47 PM PST 24
Finished	Jan 24 01:23:44 PM PST 24
Peak memory	201144 kb
Host	smart-2a6c9e2a-297a-42b6-aa68-d3689a01161a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599177447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1599177447
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2123499267
Short name	T72
Test name
Test status
Simulation time	24877029 ps
CPU time	0.7 seconds
Started	Jan 24 01:02:21 PM PST 24
Finished	Jan 24 01:02:28 PM PST 24
Peak memory	200248 kb
Host	smart-6d56b2fa-ff13-4823-974e-c6e552a10ffc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2123499267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2123499267
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2547245983
Short name	T54
Test name
Test status
Simulation time	187488053 ps
CPU time	2.32 seconds
Started	Jan 24 01:12:24 PM PST 24
Finished	Jan 24 01:13:16 PM PST 24
Peak memory	201208 kb
Host	smart-97c2472e-18fe-41d6-a17e-82cbf23bb1ef
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2547245983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2547245983
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.4105625510
Short name	T21
Test name
Test status
Simulation time	101347721 ps
CPU time	1.18 seconds
Started	Jan 24 02:32:28 PM PST 24
Finished	Jan 24 02:33:01 PM PST 24
Peak memory	201272 kb
Host	smart-7cea0902-ae72-4e3d-a2fc-985241a98bf7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105625510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_c sr_outstanding.4105625510
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.319908799
Short name	T124
Test name
Test status
Simulation time	94573344 ps
CPU time	1.34 seconds
Started	Jan 24 01:16:07 PM PST 24
Finished	Jan 24 01:16:48 PM PST 24
Peak memory	201324 kb
Host	smart-49b4425c-ee0b-4e96-bf74-12c15d57b0d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=319908799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.319908799
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.778928473
Short name	T92
Test name
Test status
Simulation time	71229432 ps
CPU time	1.03 seconds
Started	Jan 24 01:03:27 PM PST 24
Finished	Jan 24 01:03:58 PM PST 24
Peak memory	201320 kb
Host	smart-eff1bdb8-44ee-4b2b-b5e1-514070b46e38
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778928473 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.778928473
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.173333298
Short name	T43
Test name
Test status
Simulation time	53627848 ps
CPU time	0.83 seconds
Started	Jan 24 01:03:20 PM PST 24
Finished	Jan 24 01:03:47 PM PST 24
Peak memory	201084 kb
Host	smart-269c5fee-f122-425f-8037-730f6af73e82
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173333298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.173333298
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.98665845
Short name	T84
Test name
Test status
Simulation time	31936043 ps
CPU time	0.69 seconds
Started	Jan 24 01:03:26 PM PST 24
Finished	Jan 24 01:03:56 PM PST 24
Peak memory	200408 kb
Host	smart-4b2ade15-0760-48ac-ab54-755f0c0f874a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=98665845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.98665845
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.25035945
Short name	T139
Test name
Test status
Simulation time	42382515 ps
CPU time	1.03 seconds
Started	Jan 24 01:03:26 PM PST 24
Finished	Jan 24 01:03:56 PM PST 24
Peak memory	201192 kb
Host	smart-5b39e025-1b34-4aa9-8580-1a7f49177489
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25035945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_cs r_outstanding.25035945
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2370642803
Short name	T35
Test name
Test status
Simulation time	80289321 ps
CPU time	2.24 seconds
Started	Jan 24 01:03:24 PM PST 24
Finished	Jan 24 01:03:55 PM PST 24
Peak memory	201256 kb
Host	smart-76e47e2f-7788-40de-8830-f04c953511d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2370642803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2370642803
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1513208727
Short name	T112
Test name
Test status
Simulation time	35843593 ps
CPU time	0.92 seconds
Started	Jan 24 01:03:22 PM PST 24
Finished	Jan 24 01:03:51 PM PST 24
Peak memory	201288 kb
Host	smart-a90eed85-8682-4dcd-972c-989a431694cd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513208727 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.1513208727
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3957203055
Short name	T95
Test name
Test status
Simulation time	43015918 ps
CPU time	0.8 seconds
Started	Jan 24 01:03:21 PM PST 24
Finished	Jan 24 01:03:49 PM PST 24
Peak memory	201032 kb
Host	smart-99583889-7f2f-47da-b899-b47bb57703b2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957203055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3957203055
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.2874287337
Short name	T135
Test name
Test status
Simulation time	48752097 ps
CPU time	0.63 seconds
Started	Jan 24 01:03:21 PM PST 24
Finished	Jan 24 01:03:49 PM PST 24
Peak memory	200256 kb
Host	smart-3b84cb2f-e40e-4138-92da-66c4f2b5a000
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2874287337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2874287337
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3494626397
Short name	T101
Test name
Test status
Simulation time	42085986 ps
CPU time	0.97 seconds
Started	Jan 24 01:03:24 PM PST 24
Finished	Jan 24 01:03:54 PM PST 24
Peak memory	201188 kb
Host	smart-cb8f1935-a9d7-49e9-87f7-ce3539dfb5d0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494626397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_ csr_outstanding.3494626397
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3972789545
Short name	T127
Test name
Test status
Simulation time	67571611 ps
CPU time	2.12 seconds
Started	Jan 24 01:03:19 PM PST 24
Finished	Jan 24 01:03:46 PM PST 24
Peak memory	201252 kb
Host	smart-9f6016ac-0861-4176-ac20-b08645489c87
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3972789545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3972789545
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.990560928
Short name	T109
Test name
Test status
Simulation time	44734846 ps
CPU time	1.73 seconds
Started	Jan 24 01:03:26 PM PST 24
Finished	Jan 24 01:03:59 PM PST 24
Peak memory	209516 kb
Host	smart-d53388e4-523d-43f3-99e4-1e3274a96170
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990560928 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.990560928
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2781844694
Short name	T28
Test name
Test status
Simulation time	33778940 ps
CPU time	0.91 seconds
Started	Jan 24 01:03:21 PM PST 24
Finished	Jan 24 01:03:48 PM PST 24
Peak memory	201244 kb
Host	smart-6f7989b1-f89b-4712-99aa-3b2f0854daf7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781844694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2781844694
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.715138445
Short name	T105
Test name
Test status
Simulation time	75016223 ps
CPU time	1.12 seconds
Started	Jan 24 01:03:22 PM PST 24
Finished	Jan 24 01:03:49 PM PST 24
Peak memory	201124 kb
Host	smart-13e47e64-e276-4534-bf60-1cac7d5647fa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715138445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_c sr_outstanding.715138445
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2959811930
Short name	T36
Test name
Test status
Simulation time	51990433 ps
CPU time	1.61 seconds
Started	Jan 24 01:03:20 PM PST 24
Finished	Jan 24 01:03:47 PM PST 24
Peak memory	201300 kb
Host	smart-d9cf39f3-83d9-446f-92b1-92c9c4a5e17e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2959811930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2959811930
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1268640241
Short name	T104
Test name
Test status
Simulation time	184644654 ps
CPU time	2.54 seconds
Started	Jan 24 01:03:22 PM PST 24
Finished	Jan 24 01:03:51 PM PST 24
Peak memory	201196 kb
Host	smart-29f6240c-39a0-49d0-ad50-5ab0bd297369
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1268640241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1268640241
Directory	/workspace/12.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.286508560
Short name	T94
Test name
Test status
Simulation time	41782253 ps
CPU time	1.54 seconds
Started	Jan 24 01:03:38 PM PST 24
Finished	Jan 24 01:04:16 PM PST 24
Peak memory	201340 kb
Host	smart-f4ef1ff8-58b5-4ff0-ac65-a2875fe11f82
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286508560 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.286508560
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3216182070
Short name	T31
Test name
Test status
Simulation time	46341797 ps
CPU time	0.8 seconds
Started	Jan 24 01:15:14 PM PST 24
Finished	Jan 24 01:15:53 PM PST 24
Peak memory	201112 kb
Host	smart-cf40d6ab-bc2f-4df9-98d9-a3c25517bfb4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216182070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3216182070
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.393876026
Short name	T136
Test name
Test status
Simulation time	96030034 ps
CPU time	1.34 seconds
Started	Jan 24 01:03:39 PM PST 24
Finished	Jan 24 01:04:17 PM PST 24
Peak memory	201196 kb
Host	smart-9fa268f1-9cd7-4d88-b481-53604e7db794
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393876026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_c sr_outstanding.393876026
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2929264409
Short name	T123
Test name
Test status
Simulation time	304489293 ps
CPU time	3.04 seconds
Started	Jan 24 01:03:26 PM PST 24
Finished	Jan 24 01:04:00 PM PST 24
Peak memory	200984 kb
Host	smart-f4d84265-a25f-415a-8661-120914ae9ef9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2929264409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2929264409
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3614373944
Short name	T51
Test name
Test status
Simulation time	128290892 ps
CPU time	2.38 seconds
Started	Jan 24 01:03:21 PM PST 24
Finished	Jan 24 01:03:49 PM PST 24
Peak memory	201272 kb
Host	smart-d8c425fe-5756-4bc5-a85a-7856ec61e4ce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3614373944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3614373944
Directory	/workspace/13.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2601580113
Short name	T122
Test name
Test status
Simulation time	57220194 ps
CPU time	1.25 seconds
Started	Jan 24 01:11:35 PM PST 24
Finished	Jan 24 01:12:22 PM PST 24
Peak memory	209580 kb
Host	smart-61936326-0e9d-44ba-bbcc-364612134898
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601580113 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.2601580113
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.430942437
Short name	T53
Test name
Test status
Simulation time	29968939 ps
CPU time	0.8 seconds
Started	Jan 24 01:31:38 PM PST 24
Finished	Jan 24 01:32:30 PM PST 24
Peak memory	201144 kb
Host	smart-54610d20-495d-48d6-b619-ea8fad876292
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430942437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.430942437
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1256967118
Short name	T106
Test name
Test status
Simulation time	51523036 ps
CPU time	1.02 seconds
Started	Jan 24 01:03:46 PM PST 24
Finished	Jan 24 01:04:29 PM PST 24
Peak memory	201248 kb
Host	smart-68269b04-fdf0-4ea7-a1fa-4f6d7d13281c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256967118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_ csr_outstanding.1256967118
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2540989733
Short name	T113
Test name
Test status
Simulation time	99607139 ps
CPU time	2.91 seconds
Started	Jan 24 01:03:51 PM PST 24
Finished	Jan 24 01:04:36 PM PST 24
Peak memory	201324 kb
Host	smart-5da934fe-0238-48ff-9dad-ef7c401d9f21
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2540989733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2540989733
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3700628601
Short name	T16
Test name
Test status
Simulation time	35195169 ps
CPU time	1.03 seconds
Started	Jan 24 01:39:03 PM PST 24
Finished	Jan 24 01:39:09 PM PST 24
Peak memory	201252 kb
Host	smart-12ab8a1d-4cc8-40b6-adc4-3589bbb64c86
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700628601 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.3700628601
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.4265370210
Short name	T24
Test name
Test status
Simulation time	32913025 ps
CPU time	0.7 seconds
Started	Jan 24 01:03:43 PM PST 24
Finished	Jan 24 01:04:24 PM PST 24
Peak memory	200216 kb
Host	smart-aca5dd47-0290-418a-a511-3a01f4223ee5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4265370210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.4265370210
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.195523263
Short name	T144
Test name
Test status
Simulation time	190096333 ps
CPU time	1.52 seconds
Started	Jan 24 01:37:46 PM PST 24
Finished	Jan 24 01:38:16 PM PST 24
Peak memory	201192 kb
Host	smart-c7d9508a-7a24-46a6-b961-0e51339f779e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195523263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_c sr_outstanding.195523263
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3834673872
Short name	T88
Test name
Test status
Simulation time	251684232 ps
CPU time	4.28 seconds
Started	Jan 24 01:03:43 PM PST 24
Finished	Jan 24 01:04:29 PM PST 24
Peak memory	201116 kb
Host	smart-b1890d83-4ad2-49e7-a207-536467fbd0e6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3834673872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3834673872
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2134939886
Short name	T114
Test name
Test status
Simulation time	30588950 ps
CPU time	1.17 seconds
Started	Jan 24 01:20:03 PM PST 24
Finished	Jan 24 01:21:07 PM PST 24
Peak memory	201372 kb
Host	smart-a8efd9a5-d518-44c6-a92f-061553d4ed32
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134939886 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.2134939886
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1003225833
Short name	T62
Test name
Test status
Simulation time	37652997 ps
CPU time	0.76 seconds
Started	Jan 24 01:57:14 PM PST 24
Finished	Jan 24 01:57:16 PM PST 24
Peak memory	201144 kb
Host	smart-2ffd4dfb-111b-44d2-9317-b63320ceec23
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003225833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1003225833
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.5851519
Short name	T78
Test name
Test status
Simulation time	33198141 ps
CPU time	0.65 seconds
Started	Jan 24 01:03:46 PM PST 24
Finished	Jan 24 01:04:28 PM PST 24
Peak memory	200300 kb
Host	smart-bfaddd98-b3e4-4f7a-ad34-d6d0fffd1de0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=5851519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.5851519
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1425181983
Short name	T93
Test name
Test status
Simulation time	48065568 ps
CPU time	1.02 seconds
Started	Jan 24 01:40:16 PM PST 24
Finished	Jan 24 01:41:14 PM PST 24
Peak memory	201240 kb
Host	smart-ce758786-16a0-4757-8c51-b8455237804a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425181983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_ csr_outstanding.1425181983
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.425850273
Short name	T134
Test name
Test status
Simulation time	295458208 ps
CPU time	3.03 seconds
Started	Jan 24 01:41:44 PM PST 24
Finished	Jan 24 01:41:50 PM PST 24
Peak memory	201304 kb
Host	smart-32106400-6887-45b8-9a2a-003cb475e8b4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=425850273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.425850273
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.879405475
Short name	T47
Test name
Test status
Simulation time	285184308 ps
CPU time	2.7 seconds
Started	Jan 24 01:03:39 PM PST 24
Finished	Jan 24 01:04:17 PM PST 24
Peak memory	201276 kb
Host	smart-b76bd19e-0105-4e15-86c2-eaeb6ab2084f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=879405475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.879405475
Directory	/workspace/16.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.20600756
Short name	T6
Test name
Test status
Simulation time	45635465 ps
CPU time	1.05 seconds
Started	Jan 24 01:59:20 PM PST 24
Finished	Jan 24 01:59:23 PM PST 24
Peak memory	201312 kb
Host	smart-3d0135ae-1470-4ee8-99e7-57b420edc918
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20600756 -assert nopostproc +UVM_TESTNAME=usbde v_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.20600756
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4172441641
Short name	T91
Test name
Test status
Simulation time	37388741 ps
CPU time	0.97 seconds
Started	Jan 24 01:45:52 PM PST 24
Finished	Jan 24 01:46:13 PM PST 24
Peak memory	201204 kb
Host	smart-453cc5f7-657b-449e-9f0e-bedb5c01891d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172441641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_ csr_outstanding.4172441641
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3249987710
Short name	T130
Test name
Test status
Simulation time	70902782 ps
CPU time	1.46 seconds
Started	Jan 24 01:03:43 PM PST 24
Finished	Jan 24 01:04:26 PM PST 24
Peak memory	201212 kb
Host	smart-cec2c01b-c967-48f4-8c44-2c4b0ce0e148
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3249987710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3249987710
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1490425774
Short name	T65
Test name
Test status
Simulation time	66203994 ps
CPU time	1.38 seconds
Started	Jan 24 03:58:51 PM PST 24
Finished	Jan 24 03:58:53 PM PST 24
Peak memory	201316 kb
Host	smart-a537930b-f2b3-40cf-b8ae-bb3f2e5a572f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490425774 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.1490425774
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.267389767
Short name	T102
Test name
Test status
Simulation time	33403185 ps
CPU time	0.8 seconds
Started	Jan 24 01:03:39 PM PST 24
Finished	Jan 24 01:04:15 PM PST 24
Peak memory	200856 kb
Host	smart-d87e40d2-95f8-4a85-8d13-0226fcaf1a81
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267389767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.267389767
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.995578381
Short name	T141
Test name
Test status
Simulation time	117119774 ps
CPU time	3.09 seconds
Started	Jan 24 01:03:38 PM PST 24
Finished	Jan 24 01:04:17 PM PST 24
Peak memory	201120 kb
Host	smart-16112c00-431a-432d-b99b-186b0569168d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=995578381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.995578381
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.432045621
Short name	T14
Test name
Test status
Simulation time	50962628 ps
CPU time	1.25 seconds
Started	Jan 24 01:03:51 PM PST 24
Finished	Jan 24 01:04:34 PM PST 24
Peak memory	217648 kb
Host	smart-8c4220d5-b804-42e8-b5d1-fa167f79045e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432045621 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.432045621
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1372972537
Short name	T42
Test name
Test status
Simulation time	32645541 ps
CPU time	1.07 seconds
Started	Jan 24 01:03:43 PM PST 24
Finished	Jan 24 01:04:26 PM PST 24
Peak memory	201180 kb
Host	smart-814f164b-2160-41c9-adbf-2453c400940f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372972537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1372972537
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.921634271
Short name	T30
Test name
Test status
Simulation time	66991505 ps
CPU time	0.96 seconds
Started	Jan 24 01:19:05 PM PST 24
Finished	Jan 24 01:20:06 PM PST 24
Peak memory	201204 kb
Host	smart-674a11e0-d261-453d-b35e-69271fd095b3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921634271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_c sr_outstanding.921634271
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2515755290
Short name	T34
Test name
Test status
Simulation time	238222758 ps
CPU time	3.06 seconds
Started	Jan 24 01:03:39 PM PST 24
Finished	Jan 24 01:04:17 PM PST 24
Peak memory	201032 kb
Host	smart-3f9db361-6df4-4ccd-ae17-27ba767d3d91
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2515755290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2515755290
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2782251747
Short name	T118
Test name
Test status
Simulation time	304243711 ps
CPU time	3.55 seconds
Started	Jan 24 01:02:31 PM PST 24
Finished	Jan 24 01:02:41 PM PST 24
Peak memory	201176 kb
Host	smart-1e1ddf9b-59ac-4f50-8f7c-d559c430956b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782251747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2782251747
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2071303517
Short name	T125
Test name
Test status
Simulation time	365824015 ps
CPU time	8.73 seconds
Started	Jan 24 01:02:33 PM PST 24
Finished	Jan 24 01:02:47 PM PST 24
Peak memory	201164 kb
Host	smart-a21f1b92-b068-4ed6-a7b9-0e83c59a13c0
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071303517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2071303517
Directory	/workspace/2.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.258905255
Short name	T129
Test name
Test status
Simulation time	28721558 ps
CPU time	0.98 seconds
Started	Jan 24 01:02:32 PM PST 24
Finished	Jan 24 01:02:39 PM PST 24
Peak memory	201172 kb
Host	smart-eac82b53-ec9e-48a0-a887-179fafa0f55a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258905255 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.258905255
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2726438662
Short name	T58
Test name
Test status
Simulation time	46212907 ps
CPU time	0.88 seconds
Started	Jan 24 01:02:33 PM PST 24
Finished	Jan 24 01:02:40 PM PST 24
Peak memory	201096 kb
Host	smart-6702f7ad-8b0e-480f-91a5-775316604adb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726438662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2726438662
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.2660603283
Short name	T85
Test name
Test status
Simulation time	46319637 ps
CPU time	0.63 seconds
Started	Jan 24 01:13:33 PM PST 24
Finished	Jan 24 01:13:59 PM PST 24
Peak memory	200360 kb
Host	smart-b9e68e5e-ffac-4d7c-8d97-e81eb82c8d6d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2660603283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2660603283
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2090264742
Short name	T56
Test name
Test status
Simulation time	169977893 ps
CPU time	2.34 seconds
Started	Jan 24 01:02:35 PM PST 24
Finished	Jan 24 01:02:43 PM PST 24
Peak memory	201256 kb
Host	smart-1f6dda84-c165-4ad6-948f-494e951718a8
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2090264742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2090264742
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1546412654
Short name	T143
Test name
Test status
Simulation time	150341083 ps
CPU time	3.95 seconds
Started	Jan 24 01:02:33 PM PST 24
Finished	Jan 24 01:02:42 PM PST 24
Peak memory	201152 kb
Host	smart-68def255-1c95-4a71-a303-553c5c8b32c9
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1546412654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1546412654
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3686817689
Short name	T100
Test name
Test status
Simulation time	117956274 ps
CPU time	1.42 seconds
Started	Jan 24 01:02:35 PM PST 24
Finished	Jan 24 01:02:43 PM PST 24
Peak memory	201076 kb
Host	smart-43c963c5-e063-4ee1-98d3-a0ddbd01f937
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686817689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c sr_outstanding.3686817689
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.829269696
Short name	T121
Test name
Test status
Simulation time	29044786 ps
CPU time	0.67 seconds
Started	Jan 24 01:03:36 PM PST 24
Finished	Jan 24 01:04:10 PM PST 24
Peak memory	200368 kb
Host	smart-4a8d044b-ca00-4721-ada3-9683b2785a91
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=829269696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.829269696
Directory	/workspace/23.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.59449083
Short name	T77
Test name
Test status
Simulation time	22165545 ps
CPU time	0.62 seconds
Started	Jan 24 01:03:46 PM PST 24
Finished	Jan 24 01:04:27 PM PST 24
Peak memory	200404 kb
Host	smart-9b5c8c17-fc87-4fbe-be03-4d35ccc8ee31
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=59449083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.59449083
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.3258443320
Short name	T79
Test name
Test status
Simulation time	43108574 ps
CPU time	0.67 seconds
Started	Jan 24 01:03:54 PM PST 24
Finished	Jan 24 01:04:37 PM PST 24
Peak memory	200396 kb
Host	smart-d6a21e04-c8fd-4d0b-8179-97aa8e46a870
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3258443320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3258443320
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.2728024964
Short name	T19
Test name
Test status
Simulation time	27917189 ps
CPU time	0.69 seconds
Started	Jan 24 01:49:29 PM PST 24
Finished	Jan 24 01:49:33 PM PST 24
Peak memory	200416 kb
Host	smart-6fe9b540-3e5f-46f1-9d7c-b022a68d8c24
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2728024964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2728024964
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.3964059491
Short name	T66
Test name
Test status
Simulation time	25784533 ps
CPU time	0.65 seconds
Started	Jan 24 01:11:39 PM PST 24
Finished	Jan 24 01:12:28 PM PST 24
Peak memory	200420 kb
Host	smart-e1f4a207-3d41-46d4-9944-51e7a63ded42
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3964059491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3964059491
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.909589566
Short name	T48
Test name
Test status
Simulation time	309203557 ps
CPU time	3.74 seconds
Started	Jan 24 01:15:48 PM PST 24
Finished	Jan 24 01:16:36 PM PST 24
Peak memory	201232 kb
Host	smart-0b409630-237e-466c-9bb4-841ba2b86933
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909589566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.909589566
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1414717792
Short name	T90
Test name
Test status
Simulation time	54094971 ps
CPU time	1.35 seconds
Started	Jan 24 01:02:33 PM PST 24
Finished	Jan 24 01:02:40 PM PST 24
Peak memory	209480 kb
Host	smart-449174cf-276a-4fa0-8e32-3744e8b4f88a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414717792 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.1414717792
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.884106705
Short name	T45
Test name
Test status
Simulation time	35895799 ps
CPU time	0.95 seconds
Started	Jan 24 01:24:18 PM PST 24
Finished	Jan 24 01:24:52 PM PST 24
Peak memory	201280 kb
Host	smart-c97e37a3-0e94-4ce1-a9bf-9599ad197927
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884106705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.884106705
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1820729866
Short name	T61
Test name
Test status
Simulation time	152002838 ps
CPU time	2.37 seconds
Started	Jan 24 01:02:45 PM PST 24
Finished	Jan 24 01:03:05 PM PST 24
Peak memory	201248 kb
Host	smart-9c035875-e304-46e8-8f40-520909b2ff10
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1820729866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1820729866
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1081356189
Short name	T99
Test name
Test status
Simulation time	149927711 ps
CPU time	3.79 seconds
Started	Jan 24 01:02:35 PM PST 24
Finished	Jan 24 01:02:45 PM PST 24
Peak memory	201032 kb
Host	smart-816a675d-22e2-405a-aa47-50d556cfce5c
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1081356189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1081356189
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2497563638
Short name	T20
Test name
Test status
Simulation time	56408120 ps
CPU time	1.32 seconds
Started	Jan 24 01:02:31 PM PST 24
Finished	Jan 24 01:02:39 PM PST 24
Peak memory	201208 kb
Host	smart-0aa4ebcd-deb9-441c-8557-54b56785ea11
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497563638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c sr_outstanding.2497563638
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2730345343
Short name	T111
Test name
Test status
Simulation time	351543687 ps
CPU time	3.16 seconds
Started	Jan 24 01:02:46 PM PST 24
Finished	Jan 24 01:03:07 PM PST 24
Peak memory	201228 kb
Host	smart-406375d5-2d43-42be-8692-a15071d92379
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2730345343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2730345343
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.820549700
Short name	T87
Test name
Test status
Simulation time	26721892 ps
CPU time	0.65 seconds
Started	Jan 24 01:03:52 PM PST 24
Finished	Jan 24 01:04:34 PM PST 24
Peak memory	200372 kb
Host	smart-f9548605-9c8e-43f9-87dd-b0554ced4075
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=820549700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.820549700
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.1196790510
Short name	T76
Test name
Test status
Simulation time	26931223 ps
CPU time	0.62 seconds
Started	Jan 24 01:45:16 PM PST 24
Finished	Jan 24 01:45:25 PM PST 24
Peak memory	200424 kb
Host	smart-d969e01e-ff50-41e6-9e7f-9a58eadcc008
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1196790510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1196790510
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.4158338345
Short name	T86
Test name
Test status
Simulation time	21501834 ps
CPU time	0.62 seconds
Started	Jan 24 01:03:54 PM PST 24
Finished	Jan 24 01:04:36 PM PST 24
Peak memory	200364 kb
Host	smart-adbdefc8-7d69-4533-aa76-68ee473aa19f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4158338345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.4158338345
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1164149767
Short name	T73
Test name
Test status
Simulation time	26032527 ps
CPU time	0.64 seconds
Started	Jan 24 01:03:54 PM PST 24
Finished	Jan 24 01:04:37 PM PST 24
Peak memory	200300 kb
Host	smart-8a1a6e4c-fda7-455e-b060-5274f6cb6568
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1164149767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1164149767
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2864777502
Short name	T117
Test name
Test status
Simulation time	169190744 ps
CPU time	2.04 seconds
Started	Jan 24 01:29:42 PM PST 24
Finished	Jan 24 01:29:58 PM PST 24
Peak memory	201236 kb
Host	smart-3a1b2cbb-41b1-4ca9-8247-b7466258eaac
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864777502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2864777502
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2411902306
Short name	T119
Test name
Test status
Simulation time	33133665 ps
CPU time	1.33 seconds
Started	Jan 24 01:03:06 PM PST 24
Finished	Jan 24 01:03:30 PM PST 24
Peak memory	209416 kb
Host	smart-1fc62ee3-5556-46c7-916c-b2881319f78f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411902306 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.2411902306
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1174366919
Short name	T89
Test name
Test status
Simulation time	65378792 ps
CPU time	1.02 seconds
Started	Jan 24 01:02:47 PM PST 24
Finished	Jan 24 01:03:06 PM PST 24
Peak memory	201100 kb
Host	smart-d6bc010c-f8b5-4d77-a50a-5ce87a5d9424
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174366919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1174366919
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1911476083
Short name	T81
Test name
Test status
Simulation time	21363793 ps
CPU time	0.65 seconds
Started	Jan 24 01:02:51 PM PST 24
Finished	Jan 24 01:03:12 PM PST 24
Peak memory	200216 kb
Host	smart-2ad89316-9c2a-4d29-927e-45286c864a09
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1911476083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1911476083
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2107440714
Short name	T59
Test name
Test status
Simulation time	40165206 ps
CPU time	1.32 seconds
Started	Jan 24 01:09:34 PM PST 24
Finished	Jan 24 01:10:15 PM PST 24
Peak memory	201248 kb
Host	smart-57e7067c-60e7-4931-902b-57a1d42783ea
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2107440714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2107440714
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.355789722
Short name	T32
Test name
Test status
Simulation time	104685866 ps
CPU time	1.57 seconds
Started	Jan 24 01:02:52 PM PST 24
Finished	Jan 24 01:03:14 PM PST 24
Peak memory	201312 kb
Host	smart-dfc17dda-0299-4a1f-9db2-22bbac64367a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=355789722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.355789722
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.234165706
Short name	T126
Test name
Test status
Simulation time	32098520 ps
CPU time	0.68 seconds
Started	Jan 24 01:03:50 PM PST 24
Finished	Jan 24 01:04:34 PM PST 24
Peak memory	200260 kb
Host	smart-5259cfb8-5c98-4874-8d20-a4b824d482bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=234165706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.234165706
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.680176652
Short name	T75
Test name
Test status
Simulation time	39456850 ps
CPU time	0.61 seconds
Started	Jan 24 01:04:01 PM PST 24
Finished	Jan 24 01:04:44 PM PST 24
Peak memory	200244 kb
Host	smart-493bc917-436a-4830-bc3f-809b62de50a4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=680176652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.680176652
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.632593882
Short name	T25
Test name
Test status
Simulation time	22011976 ps
CPU time	0.66 seconds
Started	Jan 24 01:48:33 PM PST 24
Finished	Jan 24 01:48:37 PM PST 24
Peak memory	200344 kb
Host	smart-344ab623-8f27-46fd-aa4a-0c379d4f1d3b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=632593882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.632593882
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.2816834331
Short name	T142
Test name
Test status
Simulation time	25501817 ps
CPU time	0.6 seconds
Started	Jan 24 01:04:02 PM PST 24
Finished	Jan 24 01:04:47 PM PST 24
Peak memory	200264 kb
Host	smart-f408ee6e-7280-47cd-8ecb-086503a39484
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2816834331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2816834331
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2910528888
Short name	T116
Test name
Test status
Simulation time	30268280 ps
CPU time	0.65 seconds
Started	Jan 24 01:04:02 PM PST 24
Finished	Jan 24 01:04:47 PM PST 24
Peak memory	200264 kb
Host	smart-664494a1-5579-4fc1-b15e-76999df166d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2910528888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2910528888
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.299364928
Short name	T80
Test name
Test status
Simulation time	24936396 ps
CPU time	0.64 seconds
Started	Jan 24 01:03:50 PM PST 24
Finished	Jan 24 01:04:33 PM PST 24
Peak memory	200280 kb
Host	smart-a57c569b-7287-4289-9875-fd5f7465a447
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=299364928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.299364928
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.376173334
Short name	T64
Test name
Test status
Simulation time	53746822 ps
CPU time	1.12 seconds
Started	Jan 24 01:03:06 PM PST 24
Finished	Jan 24 01:03:30 PM PST 24
Peak memory	201184 kb
Host	smart-83c6e362-2b97-4267-8c34-7cd803ed5548
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376173334 -assert nopostproc +UVM_TESTNAME=usbd ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.376173334
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.4270643189
Short name	T29
Test name
Test status
Simulation time	31756687 ps
CPU time	1.05 seconds
Started	Jan 24 01:23:26 PM PST 24
Finished	Jan 24 01:24:14 PM PST 24
Peak memory	201232 kb
Host	smart-0a15f8fb-a337-4043-aa43-c053cb848d5f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270643189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.4270643189
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.2667504527
Short name	T140
Test name
Test status
Simulation time	25115359 ps
CPU time	0.65 seconds
Started	Jan 24 02:05:21 PM PST 24
Finished	Jan 24 02:06:12 PM PST 24
Peak memory	200348 kb
Host	smart-7aa1db42-4092-4613-92b3-80c907890bf2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2667504527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2667504527
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1565758109
Short name	T97
Test name
Test status
Simulation time	36838543 ps
CPU time	1.02 seconds
Started	Jan 24 01:50:46 PM PST 24
Finished	Jan 24 01:50:49 PM PST 24
Peak memory	201296 kb
Host	smart-21e49208-d821-464a-8634-cf487a5c3cdb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565758109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c sr_outstanding.1565758109
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1616204497
Short name	T132
Test name
Test status
Simulation time	209864393 ps
CPU time	2.69 seconds
Started	Jan 24 01:12:25 PM PST 24
Finished	Jan 24 01:13:19 PM PST 24
Peak memory	201280 kb
Host	smart-06a2856d-43f3-4eea-acd1-5d91eec474c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1616204497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1616204497
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3852874609
Short name	T103
Test name
Test status
Simulation time	30438995 ps
CPU time	0.96 seconds
Started	Jan 24 01:18:41 PM PST 24
Finished	Jan 24 01:19:22 PM PST 24
Peak memory	201304 kb
Host	smart-cc89ff4c-b124-4044-adaf-90d5f19b00fc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852874609 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.3852874609
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4287172488
Short name	T107
Test name
Test status
Simulation time	86001463 ps
CPU time	1.08 seconds
Started	Jan 24 01:03:05 PM PST 24
Finished	Jan 24 01:03:29 PM PST 24
Peak memory	201176 kb
Host	smart-748a09fa-77c6-4af5-8c6f-8e03d542b50d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287172488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4287172488
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.985835184
Short name	T41
Test name
Test status
Simulation time	72657037 ps
CPU time	1.02 seconds
Started	Jan 24 01:13:41 PM PST 24
Finished	Jan 24 01:14:06 PM PST 24
Peak memory	201252 kb
Host	smart-ee49922a-a056-46f2-bef2-e7b30fb9d20b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985835184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_cs r_outstanding.985835184
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2332639396
Short name	T33
Test name
Test status
Simulation time	231439628 ps
CPU time	2.88 seconds
Started	Jan 24 01:03:06 PM PST 24
Finished	Jan 24 01:03:32 PM PST 24
Peak memory	201152 kb
Host	smart-c6cac3df-3eb0-40a0-86f3-72f545e69269
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2332639396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2332639396
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2769672836
Short name	T46
Test name
Test status
Simulation time	332366674 ps
CPU time	2.88 seconds
Started	Jan 24 01:28:37 PM PST 24
Finished	Jan 24 01:29:02 PM PST 24
Peak memory	201288 kb
Host	smart-a0951431-31dd-49da-ae16-1552a2ff177f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2769672836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2769672836
Directory	/workspace/6.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1033088071
Short name	T63
Test name
Test status
Simulation time	40111423 ps
CPU time	0.97 seconds
Started	Jan 24 01:03:21 PM PST 24
Finished	Jan 24 01:03:48 PM PST 24
Peak memory	201312 kb
Host	smart-7ce5b85c-cc91-4c90-9963-330b8e44eca4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033088071 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.1033088071
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1551753449
Short name	T133
Test name
Test status
Simulation time	77750018 ps
CPU time	0.81 seconds
Started	Jan 24 01:22:59 PM PST 24
Finished	Jan 24 01:23:53 PM PST 24
Peak memory	201176 kb
Host	smart-73b11251-2b45-43e1-b483-4c4cd3915f2e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551753449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1551753449
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1670242753
Short name	T110
Test name
Test status
Simulation time	24868737 ps
CPU time	0.63 seconds
Started	Jan 24 01:03:11 PM PST 24
Finished	Jan 24 01:03:34 PM PST 24
Peak memory	200288 kb
Host	smart-1c2d1940-d10e-4951-beeb-2c4e0e3d6306
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1670242753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1670242753
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4072662964
Short name	T120
Test name
Test status
Simulation time	42844904 ps
CPU time	0.98 seconds
Started	Jan 24 01:03:05 PM PST 24
Finished	Jan 24 01:03:29 PM PST 24
Peak memory	201196 kb
Host	smart-647b9a63-381b-48ae-9ee3-ac747d9e5a07
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072662964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c sr_outstanding.4072662964
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.527327679
Short name	T108
Test name
Test status
Simulation time	122154730 ps
CPU time	1.9 seconds
Started	Jan 24 01:19:07 PM PST 24
Finished	Jan 24 01:20:10 PM PST 24
Peak memory	201328 kb
Host	smart-c6ff8fd2-b397-41a1-bfde-497be81ca445
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=527327679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.527327679
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3128104144
Short name	T15
Test name
Test status
Simulation time	30777052 ps
CPU time	0.87 seconds
Started	Jan 24 01:03:24 PM PST 24
Finished	Jan 24 01:03:54 PM PST 24
Peak memory	201120 kb
Host	smart-c9e42dd5-1489-4012-9570-5b513e23fc80
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128104144 -assert nopostproc +UVM_TESTNAME=usb dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.3128104144
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2259207193
Short name	T115
Test name
Test status
Simulation time	40671623 ps
CPU time	0.79 seconds
Started	Jan 24 01:03:21 PM PST 24
Finished	Jan 24 01:03:48 PM PST 24
Peak memory	201032 kb
Host	smart-81b50438-9e5f-4cde-b16b-749bfcc662e3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259207193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2259207193
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1806953578
Short name	T137
Test name
Test status
Simulation time	65970958 ps
CPU time	0.98 seconds
Started	Jan 24 01:03:19 PM PST 24
Finished	Jan 24 01:03:45 PM PST 24
Peak memory	201140 kb
Host	smart-83a4fc2d-359f-4734-b997-3b4e8e1e312e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806953578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c sr_outstanding.1806953578
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2293038463
Short name	T128
Test name
Test status
Simulation time	107968692 ps
CPU time	1.56 seconds
Started	Jan 24 01:03:26 PM PST 24
Finished	Jan 24 01:03:59 PM PST 24
Peak memory	201032 kb
Host	smart-070691e9-ff67-4064-ad00-1ed5f301fa6d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2293038463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2293038463
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3196198633
Short name	T39
Test name
Test status
Simulation time	271895909 ps
CPU time	4.27 seconds
Started	Jan 24 01:03:18 PM PST 24
Finished	Jan 24 01:03:48 PM PST 24
Peak memory	201216 kb
Host	smart-dfd93f2f-fc69-4cf9-8c16-c20c15495b99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3196198633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3196198633
Directory	/workspace/8.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.450930050
Short name	T68
Test name
Test status
Simulation time	144586172 ps
CPU time	1.08 seconds
Started	Jan 24 01:03:22 PM PST 24
Finished	Jan 24 01:03:49 PM PST 24
Peak memory	201088 kb
Host	smart-5894eeac-6136-477f-9692-e0adbd651948
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450930050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.450930050
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3513320426
Short name	T27
Test name
Test status
Simulation time	35560325 ps
CPU time	0.94 seconds
Started	Jan 24 01:03:23 PM PST 24
Finished	Jan 24 01:03:52 PM PST 24
Peak memory	201120 kb
Host	smart-4e1b0368-6974-44b9-9e5e-2ac610ca99ab
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513320426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_c sr_outstanding.3513320426
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2469652472
Short name	T38
Test name
Test status
Simulation time	109354979 ps
CPU time	1.72 seconds
Started	Jan 24 01:03:22 PM PST 24
Finished	Jan 24 01:03:50 PM PST 24
Peak memory	201160 kb
Host	smart-cbfd9524-6571-4091-b378-a17dffb14448
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2469652472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2469652472
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2221342569
Short name	T50
Test name
Test status
Simulation time	414173786 ps
CPU time	3 seconds
Started	Jan 24 01:03:22 PM PST 24
Finished	Jan 24 01:03:53 PM PST 24
Peak memory	201144 kb
Host	smart-8d382a49-b407-4228-b17e-1444fad4150c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2221342569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2221342569
Directory	/workspace/9.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/0.usbdev_sec_cm.3454016489
Short name	T4
Test name
Test status
Simulation time	149439128 ps
CPU time	1.04 seconds
Started	Jan 24 10:42:11 PM PST 24
Finished	Jan 24 10:42:13 PM PST 24
Peak memory	220232 kb
Host	smart-a45e0c1c-8fab-447c-ab8a-1cd43f7cf180
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3454016489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3454016489
Directory	/workspace/0.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/1.usbdev_sec_cm.1560929729
Short name	T5
Test name
Test status
Simulation time	104604806 ps
CPU time	0.99 seconds
Started	Jan 25 12:52:23 AM PST 24
Finished	Jan 25 12:52:25 AM PST 24
Peak memory	220272 kb
Host	smart-a1974147-ec59-4cc1-b608-e0f9a2f7cf9c
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1560929729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1560929729
Directory	/workspace/1.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/4.usbdev_sec_cm.2239496169
Short name	T2
Test name
Test status
Simulation time	87614074 ps
CPU time	0.89 seconds
Started	Jan 24 10:43:05 PM PST 24
Finished	Jan 24 10:43:07 PM PST 24
Peak memory	220216 kb
Host	smart-ce5584cf-453c-4040-b26c-4b13b86b99b6
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2239496169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2239496169
Directory	/workspace/4.usbdev_sec_cm/latest