Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	68	0	68	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	17	0	17	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	68	0	68	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	247	1		T9	8		T24	8		T25	8
all_pins[1]	247	1		T9	8		T24	8		T25	8
all_pins[2]	247	1		T9	8		T24	8		T25	8
all_pins[3]	247	1		T9	8		T24	8		T25	8
all_pins[4]	247	1		T9	8		T24	8		T25	8
all_pins[5]	247	1		T9	8		T24	8		T25	8
all_pins[6]	247	1		T9	8		T24	8		T25	8
all_pins[7]	247	1		T9	8		T24	8		T25	8
all_pins[8]	247	1		T9	8		T24	8		T25	8
all_pins[9]	247	1		T9	8		T24	8		T25	8
all_pins[10]	247	1		T9	8		T24	8		T25	8
all_pins[11]	247	1		T9	8		T24	8		T25	8
all_pins[12]	247	1		T9	8		T24	8		T25	8
all_pins[13]	247	1		T9	8		T24	8		T25	8
all_pins[14]	247	1		T9	8		T24	8		T25	8
all_pins[15]	247	1		T9	8		T24	8		T25	8
all_pins[16]	247	1		T9	8		T24	8		T25	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	3495	1		T9	102		T24	106		T25	107
values[0x1]	704	1		T9	34		T24	30		T25	29
transitions[0x0=>0x1]	533	1		T9	27		T24	24		T25	21
transitions[0x1=>0x0]	542	1		T9	27		T24	24		T25	22

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	68	0	68	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	198	1		T9	7		T24	6		T25	3
all_pins[0]	values[0x1]	49	1		T9	1		T24	2		T25	5
all_pins[0]	transitions[0x0=>0x1]	37	1		T9	1		T24	1		T25	3
all_pins[0]	transitions[0x1=>0x0]	34	1		T9	3		T24	2		T26	1
all_pins[1]	values[0x0]	201	1		T9	5		T24	5		T25	6
all_pins[1]	values[0x1]	46	1		T9	3		T24	3		T25	2
all_pins[1]	transitions[0x0=>0x1]	33	1		T9	3		T24	3		T25	2
all_pins[1]	transitions[0x1=>0x0]	36	1		T9	2		T24	1		T25	2
all_pins[2]	values[0x0]	198	1		T9	6		T24	7		T25	6
all_pins[2]	values[0x1]	49	1		T9	2		T24	1		T25	2
all_pins[2]	transitions[0x0=>0x1]	37	1		T9	1		T24	1		T25	2
all_pins[2]	transitions[0x1=>0x0]	25	1		T9	1		T24	2		T66	1
all_pins[3]	values[0x0]	210	1		T9	6		T24	6		T25	8
all_pins[3]	values[0x1]	37	1		T9	2		T24	2		T26	1
all_pins[3]	transitions[0x0=>0x1]	30	1		T9	2		T24	2		T26	1
all_pins[3]	transitions[0x1=>0x0]	37	1		T9	2		T25	1		T26	1
all_pins[4]	values[0x0]	203	1		T9	6		T24	8		T25	7
all_pins[4]	values[0x1]	44	1		T9	2		T25	1		T26	1
all_pins[4]	transitions[0x0=>0x1]	33	1		T9	2		T25	1		T26	1
all_pins[4]	transitions[0x1=>0x0]	36	1		T9	2		T24	3		T25	1
all_pins[5]	values[0x0]	200	1		T9	6		T24	5		T25	7
all_pins[5]	values[0x1]	47	1		T9	2		T24	3		T25	1
all_pins[5]	transitions[0x0=>0x1]	41	1		T9	2		T24	3		T25	1
all_pins[5]	transitions[0x1=>0x0]	22	1		T9	2		T19	3		T73	1
all_pins[6]	values[0x0]	219	1		T9	6		T24	8		T25	8
all_pins[6]	values[0x1]	28	1		T9	2		T19	3		T74	2
all_pins[6]	transitions[0x0=>0x1]	15	1		T9	2		T19	3		T74	1
all_pins[6]	transitions[0x1=>0x0]	30	1		T9	2		T24	1		T26	3
all_pins[7]	values[0x0]	204	1		T9	6		T24	7		T25	8
all_pins[7]	values[0x1]	43	1		T9	2		T24	1		T26	3
all_pins[7]	transitions[0x0=>0x1]	30	1		T9	2		T26	3		T73	3
all_pins[7]	transitions[0x1=>0x0]	27	1		T9	3		T25	2		T19	1
all_pins[8]	values[0x0]	207	1		T9	5		T24	7		T25	6
all_pins[8]	values[0x1]	40	1		T9	3		T24	1		T25	2
all_pins[8]	transitions[0x0=>0x1]	36	1		T9	2		T24	1		T19	1
all_pins[8]	transitions[0x1=>0x0]	26	1		T24	3		T25	2		T26	2
all_pins[9]	values[0x0]	217	1		T9	7		T24	5		T25	4
all_pins[9]	values[0x1]	30	1		T9	1		T24	3		T25	4
all_pins[9]	transitions[0x0=>0x1]	21	1		T9	1		T24	3		T25	2
all_pins[9]	transitions[0x1=>0x0]	41	1		T9	2		T24	2		T26	2
all_pins[10]	values[0x0]	197	1		T9	6		T24	6		T25	6
all_pins[10]	values[0x1]	50	1		T9	2		T24	2		T25	2
all_pins[10]	transitions[0x0=>0x1]	38	1		T9	2		T25	2		T66	1
all_pins[10]	transitions[0x1=>0x0]	20	1		T9	1		T24	1		T26	3
all_pins[11]	values[0x0]	215	1		T9	7		T24	5		T25	8
all_pins[11]	values[0x1]	32	1		T9	1		T24	3		T26	5
all_pins[11]	transitions[0x0=>0x1]	29	1		T9	1		T24	3		T26	5
all_pins[11]	transitions[0x1=>0x0]	35	1		T25	4		T26	1		T66	1
all_pins[12]	values[0x0]	209	1		T9	8		T24	8		T25	4
all_pins[12]	values[0x1]	38	1		T25	4		T26	1		T66	1
all_pins[12]	transitions[0x0=>0x1]	30	1		T25	4		T26	1		T66	1
all_pins[12]	transitions[0x1=>0x0]	34	1		T9	1		T25	1		T26	1
all_pins[13]	values[0x0]	205	1		T9	7		T24	8		T25	7
all_pins[13]	values[0x1]	42	1		T9	1		T25	1		T26	1
all_pins[13]	transitions[0x0=>0x1]	35	1		T25	1		T26	1		T66	1
all_pins[13]	transitions[0x1=>0x0]	29	1		T24	3		T25	2		T26	3
all_pins[14]	values[0x0]	211	1		T9	7		T24	5		T25	6
all_pins[14]	values[0x1]	36	1		T9	1		T24	3		T25	2
all_pins[14]	transitions[0x0=>0x1]	24	1		T9	1		T24	1		T25	2
all_pins[14]	transitions[0x1=>0x0]	35	1		T9	4		T24	4		T25	2
all_pins[15]	values[0x0]	200	1		T9	4		T24	2		T25	6
all_pins[15]	values[0x1]	47	1		T9	4		T24	6		T25	2
all_pins[15]	transitions[0x0=>0x1]	37	1		T9	1		T24	6		T25	1
all_pins[15]	transitions[0x1=>0x0]	36	1		T9	2		T26	2		T74	1
all_pins[16]	values[0x0]	201	1		T9	3		T24	8		T25	7
all_pins[16]	values[0x1]	46	1		T9	5		T25	1		T26	2
all_pins[16]	transitions[0x0=>0x1]	27	1		T9	4		T26	2		T19	1
all_pins[16]	transitions[0x1=>0x0]	39	1		T24	2		T25	5		T26	2