Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	0	23	100.00
Crosses	102	0	102	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	17	0	17	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=16}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	102	0	102	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	178	1		T9	7		T24	7		T25	7
all_values[1]	178	1		T9	7		T24	7		T25	7
all_values[2]	178	1		T9	7		T24	7		T25	7
all_values[3]	178	1		T9	7		T24	7		T25	7
all_values[4]	178	1		T9	7		T24	7		T25	7
all_values[5]	178	1		T9	7		T24	7		T25	7
all_values[6]	178	1		T9	7		T24	7		T25	7
all_values[7]	178	1		T9	7		T24	7		T25	7
all_values[8]	178	1		T9	7		T24	7		T25	7
all_values[9]	178	1		T9	7		T24	7		T25	7
all_values[10]	178	1		T9	7		T24	7		T25	7
all_values[11]	178	1		T9	7		T24	7		T25	7
all_values[12]	178	1		T9	7		T24	7		T25	7
all_values[13]	178	1		T9	7		T24	7		T25	7
all_values[14]	178	1		T9	7		T24	7		T25	7
all_values[15]	178	1		T9	7		T24	7		T25	7
all_values[16]	178	1		T9	7		T24	7		T25	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1731	1		T9	75		T24	72		T25	81
auto[1]	1295	1		T9	44		T24	47		T25	38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	496	1		T9	15		T24	30		T25	14
auto[1]	2530	1		T9	104		T24	89		T25	105

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1764	1		T9	73		T24	76		T25	64
auto[1]	1262	1		T9	46		T24	43		T25	55

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	102	0	102	100.00
Automatically Generated Cross Bins	102	0	102	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	16	1		T9	1		T25	1		T26	1
all_values[0]	auto[0]	auto[0]	auto[1]	30	1		T9	1		T24	3		T25	1
all_values[0]	auto[0]	auto[1]	auto[0]	7	1		T19	1		T73	1		T80	1
all_values[0]	auto[0]	auto[1]	auto[1]	43	1		T9	2		T25	1		T26	1
all_values[0]	auto[1]	auto[0]	auto[1]	43	1		T9	3		T24	3		T25	1
all_values[0]	auto[1]	auto[1]	auto[1]	39	1		T24	1		T25	3		T26	1
all_values[1]	auto[0]	auto[0]	auto[0]	19	1		T9	1		T25	1		T74	4
all_values[1]	auto[0]	auto[0]	auto[1]	34	1		T9	2		T24	2		T25	2
all_values[1]	auto[0]	auto[1]	auto[0]	10	1		T74	1		T80	3		T81	2
all_values[1]	auto[0]	auto[1]	auto[1]	34	1		T9	2		T24	2		T26	3
all_values[1]	auto[1]	auto[0]	auto[1]	51	1		T24	2		T25	1		T26	2
all_values[1]	auto[1]	auto[1]	auto[1]	30	1		T9	2		T24	1		T25	3
all_values[2]	auto[0]	auto[0]	auto[0]	25	1		T9	3		T24	4		T26	1
all_values[2]	auto[0]	auto[0]	auto[1]	39	1		T25	2		T26	3		T74	3
all_values[2]	auto[0]	auto[1]	auto[0]	9	1		T24	3		T19	1		T76	1
all_values[2]	auto[0]	auto[1]	auto[1]	37	1		T9	3		T25	1		T26	1
all_values[2]	auto[1]	auto[0]	auto[1]	39	1		T25	3		T66	2		T19	1
all_values[2]	auto[1]	auto[1]	auto[1]	29	1		T9	1		T25	1		T26	2
all_values[3]	auto[0]	auto[0]	auto[0]	12	1		T9	1		T24	1		T25	1
all_values[3]	auto[0]	auto[0]	auto[1]	42	1		T24	1		T25	3		T26	3
all_values[3]	auto[0]	auto[1]	auto[0]	10	1		T24	1		T76	1		T82	3
all_values[3]	auto[0]	auto[1]	auto[1]	37	1		T9	2		T24	1		T26	1
all_values[3]	auto[1]	auto[0]	auto[1]	48	1		T24	1		T25	2		T26	2
all_values[3]	auto[1]	auto[1]	auto[1]	29	1		T9	4		T24	2		T25	1
all_values[4]	auto[0]	auto[0]	auto[0]	17	1		T24	1		T25	2		T26	2
all_values[4]	auto[0]	auto[0]	auto[1]	42	1		T9	2		T24	2		T25	1
all_values[4]	auto[0]	auto[1]	auto[0]	4	1		T25	2		T83	1		T84	1
all_values[4]	auto[0]	auto[1]	auto[1]	44	1		T9	1		T24	2		T25	1
all_values[4]	auto[1]	auto[0]	auto[1]	42	1		T9	3		T24	2		T66	2
all_values[4]	auto[1]	auto[1]	auto[1]	29	1		T9	1		T25	1		T26	1
all_values[5]	auto[0]	auto[0]	auto[0]	17	1		T26	5		T19	1		T72	1
all_values[5]	auto[0]	auto[0]	auto[1]	37	1		T9	2		T24	2		T25	4
all_values[5]	auto[0]	auto[1]	auto[0]	14	1		T26	2		T72	3		T85	1
all_values[5]	auto[0]	auto[1]	auto[1]	33	1		T9	2		T24	2		T19	2
all_values[5]	auto[1]	auto[0]	auto[1]	48	1		T9	3		T24	2		T25	2
all_values[5]	auto[1]	auto[1]	auto[1]	29	1		T24	1		T25	1		T66	2
all_values[6]	auto[0]	auto[0]	auto[0]	22	1		T9	1		T24	1		T66	3
all_values[6]	auto[0]	auto[0]	auto[1]	47	1		T9	3		T24	3		T25	3
all_values[6]	auto[0]	auto[1]	auto[0]	15	1		T66	1		T73	1		T75	2
all_values[6]	auto[0]	auto[1]	auto[1]	28	1		T9	1		T26	1		T19	1
all_values[6]	auto[1]	auto[0]	auto[1]	41	1		T9	1		T24	3		T25	4
all_values[6]	auto[1]	auto[1]	auto[1]	25	1		T9	1		T26	1		T19	3
all_values[7]	auto[0]	auto[0]	auto[0]	18	1		T24	1		T25	2		T26	1
all_values[7]	auto[0]	auto[0]	auto[1]	37	1		T9	4		T24	2		T25	1
all_values[7]	auto[0]	auto[1]	auto[0]	13	1		T24	1		T25	1		T26	2
all_values[7]	auto[0]	auto[1]	auto[1]	34	1		T9	1		T24	1		T26	2
all_values[7]	auto[1]	auto[0]	auto[1]	42	1		T9	1		T24	1		T25	3
all_values[7]	auto[1]	auto[1]	auto[1]	34	1		T9	1		T24	1		T26	1
all_values[8]	auto[0]	auto[0]	auto[0]	13	1		T9	1		T66	1		T72	1
all_values[8]	auto[0]	auto[0]	auto[1]	41	1		T9	1		T24	3		T25	5
all_values[8]	auto[0]	auto[1]	auto[0]	7	1		T9	2		T76	2		T86	2
all_values[8]	auto[0]	auto[1]	auto[1]	43	1		T9	2		T24	1		T66	2
all_values[8]	auto[1]	auto[0]	auto[1]	45	1		T9	1		T24	1		T25	1
all_values[8]	auto[1]	auto[1]	auto[1]	29	1		T24	2		T25	1		T26	2
all_values[9]	auto[0]	auto[0]	auto[0]	21	1		T9	1		T26	1		T66	1
all_values[9]	auto[0]	auto[0]	auto[1]	36	1		T9	2		T25	2		T26	2
all_values[9]	auto[0]	auto[1]	auto[0]	6	1		T9	1		T26	1		T83	1
all_values[9]	auto[0]	auto[1]	auto[1]	43	1		T24	5		T25	3		T66	1
all_values[9]	auto[1]	auto[0]	auto[1]	42	1		T9	2		T24	1		T25	2
all_values[9]	auto[1]	auto[1]	auto[1]	30	1		T9	1		T24	1		T26	2
all_values[10]	auto[0]	auto[0]	auto[0]	20	1		T24	2		T26	1		T19	1
all_values[10]	auto[0]	auto[0]	auto[1]	32	1		T9	4		T24	1		T25	1
all_values[10]	auto[0]	auto[1]	auto[0]	13	1		T77	2		T85	1		T82	4
all_values[10]	auto[0]	auto[1]	auto[1]	40	1		T9	1		T24	2		T25	1
all_values[10]	auto[1]	auto[0]	auto[1]	49	1		T9	1		T24	1		T25	5
all_values[10]	auto[1]	auto[1]	auto[1]	24	1		T9	1		T24	1		T26	1
all_values[11]	auto[0]	auto[0]	auto[0]	28	1		T66	2		T19	1		T73	5
all_values[11]	auto[0]	auto[0]	auto[1]	38	1		T9	3		T24	2		T25	1
all_values[11]	auto[0]	auto[1]	auto[0]	15	1		T73	2		T77	3		T82	1
all_values[11]	auto[0]	auto[1]	auto[1]	34	1		T9	2		T24	1		T25	3
all_values[11]	auto[1]	auto[0]	auto[1]	37	1		T9	2		T24	2		T25	3
all_values[11]	auto[1]	auto[1]	auto[1]	26	1		T24	2		T26	3		T74	1
all_values[12]	auto[0]	auto[0]	auto[0]	15	1		T9	1		T24	1		T25	2
all_values[12]	auto[0]	auto[0]	auto[1]	37	1		T9	2		T24	2		T25	1
all_values[12]	auto[0]	auto[1]	auto[0]	9	1		T24	3		T26	1		T80	1
all_values[12]	auto[0]	auto[1]	auto[1]	37	1		T9	1		T25	1		T66	2
all_values[12]	auto[1]	auto[0]	auto[1]	49	1		T9	2		T24	1		T26	3
all_values[12]	auto[1]	auto[1]	auto[1]	31	1		T9	1		T25	3		T26	1
all_values[13]	auto[0]	auto[0]	auto[0]	20	1		T24	1		T25	1		T26	1
all_values[13]	auto[0]	auto[0]	auto[1]	38	1		T9	4		T24	2		T25	2
all_values[13]	auto[0]	auto[1]	auto[0]	7	1		T19	2		T82	1		T87	4
all_values[13]	auto[0]	auto[1]	auto[1]	38	1		T26	1		T66	3		T19	1
all_values[13]	auto[1]	auto[0]	auto[1]	46	1		T9	3		T24	4		T25	2
all_values[13]	auto[1]	auto[1]	auto[1]	29	1		T25	2		T26	3		T74	5
all_values[14]	auto[0]	auto[0]	auto[0]	35	1		T9	2		T24	3		T25	1
all_values[14]	auto[0]	auto[0]	auto[1]	32	1		T9	3		T26	1		T66	1
all_values[14]	auto[0]	auto[1]	auto[0]	9	1		T72	1		T80	3		T85	1
all_values[14]	auto[0]	auto[1]	auto[1]	34	1		T24	2		T25	2		T26	4
all_values[14]	auto[1]	auto[0]	auto[1]	45	1		T9	2		T24	2		T25	3
all_values[14]	auto[1]	auto[1]	auto[1]	23	1		T25	1		T26	1		T73	1
all_values[15]	auto[0]	auto[0]	auto[0]	13	1		T26	1		T74	1		T72	1
all_values[15]	auto[0]	auto[0]	auto[1]	37	1		T9	1		T25	1		T26	3
all_values[15]	auto[0]	auto[1]	auto[0]	6	1		T74	2		T78	1		T79	1
all_values[15]	auto[0]	auto[1]	auto[1]	35	1		T9	2		T24	2		T25	2
all_values[15]	auto[1]	auto[0]	auto[1]	52	1		T9	4		T24	1		T25	3
all_values[15]	auto[1]	auto[1]	auto[1]	35	1		T24	4		T25	1		T26	1
all_values[16]	auto[0]	auto[0]	auto[0]	23	1		T24	5		T26	3		T66	1
all_values[16]	auto[0]	auto[0]	auto[1]	41	1		T25	3		T66	2		T74	2
all_values[16]	auto[0]	auto[1]	auto[0]	8	1		T24	2		T26	2		T79	1
all_values[16]	auto[0]	auto[1]	auto[1]	34	1		T9	2		T25	2		T26	1
all_values[16]	auto[1]	auto[0]	auto[1]	38	1		T9	1		T25	2		T66	1
all_values[16]	auto[1]	auto[1]	auto[1]	34	1		T9	4		T26	1		T19	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal