Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36378	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	45973	1		T1	8		T2	7		T3	8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49088	1		T1	5		T2	5		T3	5
values[0x0]	16352	1		T1	5		T2	4		T3	4
values[0x1]	16911	1		T1	2		T2	3		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24962	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	57389	1		T1	9		T2	9		T3	9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	259	1		T81	2		T21	4		T61	2
valid_sources[0x01]	299	1		T38	1		T117	1		T37	1
valid_sources[0x02]	310	1		T38	1		T34	1		T87	1
valid_sources[0x03]	257	1		T41	12		T88	1		T118	1
valid_sources[0x04]	223	1		T119	1		T21	12		T61	3
valid_sources[0x05]	306	1		T120	1		T121	1		T122	1
valid_sources[0x06]	304	1		T123	1		T25	3		T61	3
valid_sources[0x07]	387	1		T124	1		T125	1		T126	1
valid_sources[0x08]	365	1		T124	2		T80	2		T15	3
valid_sources[0x09]	252	1		T84	1		T127	1		T128	1
valid_sources[0x0a]	263	1		T129	13		T21	7		T61	5
valid_sources[0x0b]	235	1		T130	2		T36	1		T131	3
valid_sources[0x0c]	286	1		T81	1		T132	1		T61	8
valid_sources[0x0d]	306	1		T133	2		T13	1		T134	13
valid_sources[0x0e]	327	1		T36	1		T135	12		T61	6
valid_sources[0x0f]	284	1		T136	1		T137	12		T138	1
valid_sources[0x10]	224	1		T90	1		T13	1		T139	1
valid_sources[0x11]	415	1		T140	3		T130	2		T141	3
valid_sources[0x12]	272	1		T124	1		T142	1		T143	1
valid_sources[0x13]	281	1		T4	1		T144	2		T145	1
valid_sources[0x14]	260	1		T126	1		T61	12		T24	34
valid_sources[0x15]	218	1		T11	1		T37	1		T16	5
valid_sources[0x16]	286	1		T146	1		T84	1		T36	2
valid_sources[0x17]	300	1		T133	1		T120	1		T147	1
valid_sources[0x18]	341	1		T132	1		T121	1		T61	5
valid_sources[0x19]	237	1		T119	1		T148	3		T24	4
valid_sources[0x1a]	287	1		T34	1		T132	1		T61	2
valid_sources[0x1b]	242	1		T136	1		T128	1		T149	2
valid_sources[0x1c]	374	1		T126	1		T61	2		T24	34
valid_sources[0x1d]	309	1		T44	3		T87	2		T21	4
valid_sources[0x1e]	213	1		T39	1		T61	5		T24	9
valid_sources[0x1f]	234	1		T31	1		T149	3		T150	1
valid_sources[0x20]	290	1		T145	1		T151	6		T152	12
valid_sources[0x21]	239	1		T15	5		T16	2		T45	1
valid_sources[0x22]	307	1		T138	3		T150	1		T21	3
valid_sources[0x23]	375	1		T136	1		T123	1		T117	1
valid_sources[0x24]	249	1		T153	12		T149	1		T61	10
valid_sources[0x25]	365	1		T24	11		T15	9		T16	4
valid_sources[0x26]	186	1		T154	2		T90	1		T155	1
valid_sources[0x27]	369	1		T126	3		T156	1		T61	13
valid_sources[0x28]	279	1		T34	1		T157	5		T85	6
valid_sources[0x29]	267	1		T117	1		T37	2		T131	1
valid_sources[0x2a]	321	1		T9	5		T158	2		T21	4
valid_sources[0x2b]	254	1		T24	4		T15	19		T16	2
valid_sources[0x2c]	341	1		T79	13		T159	1		T61	10
valid_sources[0x2d]	196	1		T123	1		T122	1		T25	2
valid_sources[0x2e]	248	1		T90	1		T142	2		T121	1
valid_sources[0x2f]	368	1		T21	5		T61	5		T15	10
valid_sources[0x30]	295	1		T133	1		T43	1		T156	1
valid_sources[0x31]	253	1		T25	1		T61	5		T24	2
valid_sources[0x32]	251	1		T31	5		T34	1		T145	1
valid_sources[0x33]	239	1		T160	4		T146	1		T119	1
valid_sources[0x34]	254	1		T84	1		T12	13		T61	5
valid_sources[0x35]	261	1		T61	4		T24	34		T15	34
valid_sources[0x36]	516	1		T147	1		T61	3		T15	36
valid_sources[0x37]	278	1		T61	14		T24	34		T15	13
valid_sources[0x38]	300	1		T9	1		T13	1		T21	4
valid_sources[0x39]	279	1		T161	1		T88	1		T15	1
valid_sources[0x3a]	282	1		T3	2		T38	1		T154	10
valid_sources[0x3b]	253	1		T6	3		T144	1		T162	2
valid_sources[0x3c]	181	1		T90	1		T155	1		T163	3
valid_sources[0x3d]	352	1		T136	1		T36	1		T164	3
valid_sources[0x3e]	279	1		T165	1		T166	4		T61	3
valid_sources[0x3f]	267	1		T2	2		T11	1		T143	1
valid_sources[0x40]	285	1		T161	2		T44	3		T125	2
valid_sources[0x41]	346	1		T142	1		T167	4		T61	2
valid_sources[0x42]	287	1		T83	1		T43	4		T125	1
valid_sources[0x43]	296	1		T39	3		T168	1		T15	10
valid_sources[0x44]	206	1		T39	1		T123	2		T34	1
valid_sources[0x45]	236	1		T61	2		T22	1		T16	1
valid_sources[0x46]	337	1		T90	1		T123	2		T146	1
valid_sources[0x47]	214	1		T162	2		T125	1		T61	5
valid_sources[0x48]	286	1		T144	1		T34	1		T169	4
valid_sources[0x49]	309	1		T123	2		T169	2		T148	1
valid_sources[0x4a]	346	1		T90	2		T120	1		T21	38
valid_sources[0x4b]	1839	1		T4	1		T146	1		T18	3
valid_sources[0x4c]	394	1		T81	1		T164	1		T166	1
valid_sources[0x4d]	388	1		T119	1		T61	2		T24	34
valid_sources[0x4e]	262	1		T39	1		T136	1		T151	1
valid_sources[0x4f]	221	1		T38	2		T33	13		T170	2
valid_sources[0x50]	235	1		T140	6		T147	2		T61	1
valid_sources[0x51]	399	1		T3	1		T140	1		T84	1
valid_sources[0x52]	230	1		T88	1		T158	1		T119	1
valid_sources[0x53]	582	1		T90	1		T13	2		T122	2
valid_sources[0x54]	542	1		T160	8		T171	1		T15	21
valid_sources[0x55]	357	1		T172	13		T125	1		T173	12
valid_sources[0x56]	690	1		T3	1		T7	1		T144	1
valid_sources[0x57]	352	1		T174	2		T175	2		T119	2
valid_sources[0x58]	319	1		T7	1		T84	1		T142	1
valid_sources[0x59]	314	1		T83	1		T81	1		T125	1
valid_sources[0x5a]	234	1		T21	7		T61	4		T15	3
valid_sources[0x5b]	278	1		T146	1		T145	1		T171	1
valid_sources[0x5c]	296	1		T174	4		T44	1		T61	2
valid_sources[0x5d]	271	1		T159	4		T143	1		T61	12
valid_sources[0x5e]	317	1		T38	2		T168	1		T176	1
valid_sources[0x5f]	348	1		T7	1		T161	1		T123	1
valid_sources[0x60]	225	1		T6	1		T136	1		T43	4
valid_sources[0x61]	380	1		T155	1		T88	1		T24	38
valid_sources[0x62]	304	1		T140	3		T156	1		T177	12
valid_sources[0x63]	166	1		T168	1		T61	1		T14	2
valid_sources[0x64]	303	1		T3	1		T21	7		T61	8
valid_sources[0x65]	203	1		T128	1		T61	8		T15	5
valid_sources[0x66]	234	1		T6	1		T117	1		T149	2
valid_sources[0x67]	306	1		T7	1		T39	2		T90	1
valid_sources[0x68]	328	1		T178	12		T21	10		T61	6
valid_sources[0x69]	305	1		T2	1		T61	3		T15	19
valid_sources[0x6a]	322	1		T7	1		T8	12		T136	1
valid_sources[0x6b]	278	1		T136	1		T61	2		T24	12
valid_sources[0x6c]	302	1		T2	1		T38	1		T179	12
valid_sources[0x6d]	304	1		T9	4		T133	2		T31	1
valid_sources[0x6e]	362	1		T88	1		T61	10		T24	34
valid_sources[0x6f]	294	1		T136	2		T117	1		T126	1
valid_sources[0x70]	265	1		T155	1		T180	3		T122	1
valid_sources[0x71]	320	1		T38	1		T144	5		T11	1
valid_sources[0x72]	279	1		T2	1		T148	1		T61	10
valid_sources[0x73]	319	1		T117	1		T168	1		T138	1
valid_sources[0x74]	349	1		T4	1		T39	1		T181	12
valid_sources[0x75]	403	1		T24	6		T14	2		T15	8
valid_sources[0x76]	336	1		T165	1		T169	1		T170	1
valid_sources[0x77]	310	1		T161	1		T117	2		T165	1
valid_sources[0x78]	292	1		T117	1		T126	1		T166	2
valid_sources[0x79]	337	1		T155	1		T158	1		T128	1
valid_sources[0x7a]	277	1		T2	1		T175	4		T146	1
valid_sources[0x7b]	376	1		T163	2		T118	1		T182	4
valid_sources[0x7c]	164	1		T168	1		T61	1		T15	4
valid_sources[0x7d]	254	1		T124	1		T168	1		T156	1
valid_sources[0x7e]	354	1		T117	1		T120	1		T128	1
valid_sources[0x7f]	349	1		T78	12		T176	1		T85	6
valid_sources[0x80]	323	1		T81	2		T11	1		T143	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17738

1

T1

4

T2

3

T3

5

values[0x0]

all_enables

biggest_size

14760

1

T1

2

T2

2

T3

2

values[0x1]

all_enables

biggest_size

13475

1

T1

2

T2

2

T3

1