Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 49030 1 T1 4 T2 5 T3 4
full_word 46899 1 T1 8 T2 7 T3 8



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 95769 1 T1 12 T2 12 T3 12
auto[TlIntgErrCmd] 53 1 T15 4 T64 6 T77 2
auto[TlIntgErrData] 55 1 T15 8 T64 4 T77 3
auto[TlIntgErrBoth] 52 1 T15 8 T77 5 T92 3



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 50875 1 T1 5 T2 5 T3 5
auto[1] 45054 1 T1 7 T2 7 T3 7



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 32900 1 T1 1 T2 2 T7 2
auto[TlIntgErrNone] partial auto[1] 15995 1 T1 3 T2 3 T3 4
auto[TlIntgErrNone] full_word auto[0] 17913 1 T1 4 T2 3 T3 5
auto[TlIntgErrNone] full_word auto[1] 28961 1 T1 4 T2 4 T3 3
auto[TlIntgErrCmd] partial auto[0] 17 1 T15 2 T64 4 T92 1
auto[TlIntgErrCmd] partial auto[1] 27 1 T15 2 T64 1 T77 1
auto[TlIntgErrCmd] full_word auto[0] 4 1 T64 1 T92 1 T111 2
auto[TlIntgErrCmd] full_word auto[1] 5 1 T77 1 T111 1 T112 1
auto[TlIntgErrData] partial auto[0] 20 1 T15 3 T64 1 T92 2
auto[TlIntgErrData] partial auto[1] 23 1 T15 3 T64 3 T77 1
auto[TlIntgErrData] full_word auto[0] 7 1 T15 1 T77 1 T92 1
auto[TlIntgErrData] full_word auto[1] 5 1 T15 1 T77 1 T92 1
auto[TlIntgErrBoth] partial auto[0] 12 1 T15 4 T77 1 T110 1
auto[TlIntgErrBoth] partial auto[1] 36 1 T15 4 T77 4 T92 2
auto[TlIntgErrBoth] full_word auto[0] 2 1 T92 1 T113 1 - -
auto[TlIntgErrBoth] full_word auto[1] 2 1 T111 2 - - - -

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%