Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
49030 |
1 |
|
T1 |
4 |
|
T2 |
5 |
|
T3 |
4 |
full_word |
46899 |
1 |
|
T1 |
8 |
|
T2 |
7 |
|
T3 |
8 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
95769 |
1 |
|
T1 |
12 |
|
T2 |
12 |
|
T3 |
12 |
auto[TlIntgErrCmd] |
53 |
1 |
|
T15 |
4 |
|
T64 |
6 |
|
T77 |
2 |
auto[TlIntgErrData] |
55 |
1 |
|
T15 |
8 |
|
T64 |
4 |
|
T77 |
3 |
auto[TlIntgErrBoth] |
52 |
1 |
|
T15 |
8 |
|
T77 |
5 |
|
T92 |
3 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50875 |
1 |
|
T1 |
5 |
|
T2 |
5 |
|
T3 |
5 |
auto[1] |
45054 |
1 |
|
T1 |
7 |
|
T2 |
7 |
|
T3 |
7 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
32900 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T7 |
2 |
auto[TlIntgErrNone] |
partial |
auto[1] |
15995 |
1 |
|
T1 |
3 |
|
T2 |
3 |
|
T3 |
4 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
17913 |
1 |
|
T1 |
4 |
|
T2 |
3 |
|
T3 |
5 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
28961 |
1 |
|
T1 |
4 |
|
T2 |
4 |
|
T3 |
3 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
17 |
1 |
|
T15 |
2 |
|
T64 |
4 |
|
T92 |
1 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
27 |
1 |
|
T15 |
2 |
|
T64 |
1 |
|
T77 |
1 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
4 |
1 |
|
T64 |
1 |
|
T92 |
1 |
|
T111 |
2 |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
5 |
1 |
|
T77 |
1 |
|
T111 |
1 |
|
T112 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
20 |
1 |
|
T15 |
3 |
|
T64 |
1 |
|
T92 |
2 |
auto[TlIntgErrData] |
partial |
auto[1] |
23 |
1 |
|
T15 |
3 |
|
T64 |
3 |
|
T77 |
1 |
auto[TlIntgErrData] |
full_word |
auto[0] |
7 |
1 |
|
T15 |
1 |
|
T77 |
1 |
|
T92 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
5 |
1 |
|
T15 |
1 |
|
T77 |
1 |
|
T92 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
12 |
1 |
|
T15 |
4 |
|
T77 |
1 |
|
T110 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
36 |
1 |
|
T15 |
4 |
|
T77 |
4 |
|
T92 |
2 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
2 |
1 |
|
T92 |
1 |
|
T113 |
1 |
|
- |
- |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
2 |
1 |
|
T111 |
2 |
|
- |
- |
|
- |
- |