Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43562	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	54647	1		T1	2		T2	5		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56937	1		T1	4		T2	4		T3	2
values[0x0]	20270	1		T1	3		T2	5		T3	3
values[0x1]	21002	1		T1	5		T2	3		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	28541	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	69668	1		T1	5		T2	6		T3	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	277	1		T173	1		T174	1		T93	1
valid_sources[0x01]	383	1		T64	1		T175	2		T176	2
valid_sources[0x02]	263	1		T177	1		T16	1		T100	1
valid_sources[0x03]	428	1		T64	2		T97	4		T115	1
valid_sources[0x04]	270	1		T98	2		T62	1		T93	1
valid_sources[0x05]	365	1		T16	3		T111	15		T104	3
valid_sources[0x06]	264	1		T115	1		T174	1		T178	2
valid_sources[0x07]	459	1		T4	3		T100	1		T174	1
valid_sources[0x08]	406	1		T94	1		T29	1		T103	15
valid_sources[0x09]	302	1		T63	1		T96	4		T20	1
valid_sources[0x0a]	650	1		T11	1		T173	1		T179	2
valid_sources[0x0b]	317	1		T17	1		T34	1		T174	2
valid_sources[0x0c]	371	1		T12	12		T93	1		T180	1
valid_sources[0x0d]	403	1		T87	3		T31	1		T181	1
valid_sources[0x0e]	316	1		T31	1		T182	1		T183	1
valid_sources[0x0f]	336	1		T18	1		T184	1		T99	1
valid_sources[0x10]	254	1		T18	1		T112	1		T185	1
valid_sources[0x11]	277	1		T2	2		T94	2		T186	1
valid_sources[0x12]	297	1		T16	3		T106	1		T57	1
valid_sources[0x13]	333	1		T1	1		T5	1		T19	3
valid_sources[0x14]	338	1		T115	1		T187	2		T188	3
valid_sources[0x15]	320	1		T189	5		T190	1		T154	1
valid_sources[0x16]	419	1		T13	1		T142	2		T92	1
valid_sources[0x17]	270	1		T9	1		T112	1		T191	1
valid_sources[0x18]	315	1		T106	1		T192	3		T21	1
valid_sources[0x19]	305	1		T4	6		T112	1		T62	1
valid_sources[0x1a]	490	1		T193	1		T112	2		T98	1
valid_sources[0x1b]	310	1		T193	1		T95	1		T194	1
valid_sources[0x1c]	284	1		T13	1		T195	1		T196	1
valid_sources[0x1d]	269	1		T59	1		T197	1		T113	5
valid_sources[0x1e]	261	1		T1	1		T77	2		T83	12
valid_sources[0x1f]	733	1		T25	1		T198	1		T199	10
valid_sources[0x20]	392	1		T73	1		T108	1		T21	1
valid_sources[0x21]	361	1		T29	1		T74	5		T200	1
valid_sources[0x22]	3468	1		T95	1		T36	9		T186	2
valid_sources[0x23]	323	1		T148	2		T195	1		T197	1
valid_sources[0x24]	396	1		T106	1		T95	1		T100	1
valid_sources[0x25]	628	1		T42	1		T190	1		T201	3
valid_sources[0x26]	303	1		T1	1		T57	1		T62	1
valid_sources[0x27]	375	1		T202	1		T200	1		T203	1
valid_sources[0x28]	520	1		T72	1		T196	1		T204	9
valid_sources[0x29]	519	1		T8	9		T13	2		T205	1
valid_sources[0x2a]	403	1		T13	3		T87	1		T72	1
valid_sources[0x2b]	331	1		T18	1		T25	1		T193	1
valid_sources[0x2c]	473	1		T206	1		T100	1		T115	1
valid_sources[0x2d]	467	1		T186	1		T99	1		T155	1
valid_sources[0x2e]	303	1		T57	1		T93	1		T90	1
valid_sources[0x2f]	251	1		T9	1		T22	2		T207	1
valid_sources[0x30]	444	1		T87	2		T63	1		T73	2
valid_sources[0x31]	436	1		T87	1		T208	1		T209	18
valid_sources[0x32]	362	1		T4	3		T106	1		T20	1
valid_sources[0x33]	362	1		T11	1		T106	1		T210	1
valid_sources[0x34]	472	1		T95	1		T57	1		T148	1
valid_sources[0x35]	324	1		T66	4		T92	1		T101	4
valid_sources[0x36]	323	1		T211	1		T212	1		T99	1
valid_sources[0x37]	431	1		T17	1		T106	3		T59	1
valid_sources[0x38]	387	1		T87	1		T77	3		T191	1
valid_sources[0x39]	342	1		T1	1		T105	18		T91	5
valid_sources[0x3a]	286	1		T77	1		T213	1		T191	1
valid_sources[0x3b]	387	1		T161	3		T16	1		T97	5
valid_sources[0x3c]	275	1		T14	18		T106	1		T214	1
valid_sources[0x3d]	487	1		T73	1		T58	2		T215	3
valid_sources[0x3e]	370	1		T11	3		T102	4		T101	4
valid_sources[0x3f]	283	1		T17	1		T24	11		T93	1
valid_sources[0x40]	267	1		T106	1		T104	1		T216	1
valid_sources[0x41]	290	1		T20	1		T149	1		T159	1
valid_sources[0x42]	353	1		T17	1		T104	2		T217	1
valid_sources[0x43]	355	1		T95	1		T148	1		T218	1
valid_sources[0x44]	213	1		T219	2		T46	6		T38	10
valid_sources[0x45]	331	1		T9	1		T97	1		T96	2
valid_sources[0x46]	390	1		T100	2		T191	1		T93	1
valid_sources[0x47]	332	1		T27	1		T92	1		T220	1
valid_sources[0x48]	321	1		T177	1		T193	1		T106	1
valid_sources[0x49]	308	1		T73	1		T30	4		T221	3
valid_sources[0x4a]	330	1		T2	1		T10	7		T11	1
valid_sources[0x4b]	269	1		T93	1		T222	2		T81	2
valid_sources[0x4c]	569	1		T97	1		T206	1		T223	4
valid_sources[0x4d]	354	1		T26	15		T177	1		T206	1
valid_sources[0x4e]	403	1		T224	1		T57	1		T202	1
valid_sources[0x4f]	317	1		T25	1		T67	4		T20	1
valid_sources[0x50]	653	1		T97	1		T56	1		T192	1
valid_sources[0x51]	505	1		T96	1		T61	1		T109	15
valid_sources[0x52]	264	1		T100	1		T225	2		T226	1
valid_sources[0x53]	299	1		T96	2		T179	2		T73	1
valid_sources[0x54]	253	1		T65	9		T112	1		T205	1
valid_sources[0x55]	367	1		T27	2		T94	1		T95	1
valid_sources[0x56]	381	1		T11	2		T17	1		T173	1
valid_sources[0x57]	432	1		T227	1		T154	1		T228	3
valid_sources[0x58]	343	1		T3	7		T224	2		T20	1
valid_sources[0x59]	458	1		T18	1		T94	1		T58	5
valid_sources[0x5a]	396	1		T25	2		T218	2		T99	1
valid_sources[0x5b]	391	1		T63	1		T229	7		T80	1
valid_sources[0x5c]	330	1		T1	3		T106	1		T148	1
valid_sources[0x5d]	387	1		T98	2		T115	1		T22	1
valid_sources[0x5e]	540	1		T108	4		T186	1		T93	1
valid_sources[0x5f]	308	1		T72	3		T61	2		T174	1
valid_sources[0x60]	254	1		T148	1		T92	1		T174	1
valid_sources[0x61]	365	1		T25	1		T230	2		T231	2
valid_sources[0x62]	418	1		T24	4		T100	1		T205	2
valid_sources[0x63]	320	1		T212	1		T232	1		T38	3
valid_sources[0x64]	246	1		T72	1		T100	1		T57	1
valid_sources[0x65]	305	1		T62	1		T149	1		T114	3
valid_sources[0x66]	297	1		T224	4		T233	1		T85	1
valid_sources[0x67]	392	1		T25	1		T94	1		T61	1
valid_sources[0x68]	377	1		T98	2		T57	1		T234	1
valid_sources[0x69]	342	1		T82	3		T190	1		T235	1
valid_sources[0x6a]	461	1		T5	2		T64	1		T102	11
valid_sources[0x6b]	406	1		T108	1		T185	2		T230	3
valid_sources[0x6c]	538	1		T18	1		T108	1		T152	1
valid_sources[0x6d]	442	1		T96	3		T104	1		T108	3
valid_sources[0x6e]	398	1		T62	1		T115	1		T236	5
valid_sources[0x6f]	309	1		T64	1		T158	7		T237	7
valid_sources[0x70]	329	1		T5	2		T63	1		T34	1
valid_sources[0x71]	433	1		T63	1		T220	1		T194	1
valid_sources[0x72]	544	1		T238	1		T113	1		T74	1
valid_sources[0x73]	443	1		T239	3		T69	2		T146	1
valid_sources[0x74]	394	1		T175	1		T90	3		T211	1
valid_sources[0x75]	351	1		T112	1		T218	1		T70	2
valid_sources[0x76]	366	1		T173	1		T112	1		T57	1
valid_sources[0x77]	274	1		T106	1		T92	1		T210	1
valid_sources[0x78]	282	1		T61	1		T240	9		T238	1
valid_sources[0x79]	430	1		T104	1		T195	1		T182	1
valid_sources[0x7a]	505	1		T19	4		T100	1		T41	1
valid_sources[0x7b]	337	1		T241	7		T94	1		T242	9
valid_sources[0x7c]	268	1		T148	2		T104	3		T174	1
valid_sources[0x7d]	386	1		T97	2		T108	3		T196	1
valid_sources[0x7e]	397	1		T233	1		T78	12		T180	1
valid_sources[0x7f]	346	1		T193	1		T69	1		T243	1
valid_sources[0x80]	256	1		T97	1		T244	7		T245	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18732

1

T1

1

T2

2

T3

1

values[0x0]

all_enables

biggest_size

18640

1

T1

1

T2

3

T3

3

values[0x1]

all_enables

biggest_size

17275

1

T3

1

T4

1

T5

2