Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	65588	1		T1	10		T2	7		T3	2
full_word	56292	1		T1	2		T2	5		T3	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	121670	1		T1	12		T2	12		T3	7
auto[TlIntgErrCmd]	65	1		T118	1		T121	6		T143	3
auto[TlIntgErrData]	68	1		T118	5		T121	3		T143	4
auto[TlIntgErrBoth]	77	1		T118	4		T121	11		T143	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	60116	1		T1	4		T2	4		T3	2
auto[1]	61764	1		T1	8		T2	8		T3	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	40969	1		T1	3		T2	2		T3	1
auto[TlIntgErrNone]	partial	auto[1]	24426	1		T1	7		T2	5		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	19059	1		T1	1		T2	2		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	37216	1		T1	1		T2	3		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	29	1		T118	1		T121	4		T143	2
auto[TlIntgErrCmd]	partial	auto[1]	29	1		T121	1		T143	1		T125	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T125	1		T163	1		T170	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T121	1		T169	1		T170	1
auto[TlIntgErrData]	partial	auto[0]	25	1		T118	2		T143	1		T125	2
auto[TlIntgErrData]	partial	auto[1]	38	1		T118	2		T121	3		T143	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T118	1		T163	1		T171	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T143	1		T168	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T118	2		T121	3		T125	7
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T118	2		T121	7		T143	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T172	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T121	1		T172	1		T165	1