Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47001	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	62169	1		T1	4		T2	4		T3	7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	61739	1		T1	2		T2	4		T3	4
values[0x0]	23326	1		T1	2		T2	5		T3	4
values[0x1]	24105	1		T1	3		T2	3		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	30187	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	78983	1		T1	4		T2	5		T3	7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	321	1		T13	1		T175	1		T91	1
valid_sources[0x01]	333	1		T3	1		T11	2		T29	5
valid_sources[0x02]	486	1		T3	1		T89	1		T106	2
valid_sources[0x03]	420	1		T37	2		T146	1		T176	18
valid_sources[0x04]	343	1		T177	1		T178	3		T74	1
valid_sources[0x05]	432	1		T106	2		T149	1		T146	1
valid_sources[0x06]	426	1		T179	1		T180	3		T181	1
valid_sources[0x07]	375	1		T182	1		T183	1		T184	1
valid_sources[0x08]	527	1		T185	2		T85	18		T149	1
valid_sources[0x09]	367	1		T3	1		T9	12		T75	1
valid_sources[0x0a]	481	1		T3	1		T4	2		T89	1
valid_sources[0x0b]	312	1		T81	1		T72	1		T94	1
valid_sources[0x0c]	448	1		T135	1		T186	1		T187	2
valid_sources[0x0d]	461	1		T84	1		T188	2		T189	9
valid_sources[0x0e]	356	1		T190	1		T104	1		T165	5
valid_sources[0x0f]	385	1		T95	2		T70	1		T191	1
valid_sources[0x10]	382	1		T2	1		T4	1		T16	1
valid_sources[0x11]	361	1		T192	1		T193	1		T165	3
valid_sources[0x12]	760	1		T36	1		T96	15		T194	1
valid_sources[0x13]	476	1		T80	1		T195	1		T196	1
valid_sources[0x14]	379	1		T84	1		T196	1		T165	9
valid_sources[0x15]	344	1		T108	1		T185	1		T195	1
valid_sources[0x16]	307	1		T95	1		T180	1		T197	1
valid_sources[0x17]	376	1		T198	1		T140	1		T145	2
valid_sources[0x18]	384	1		T177	1		T199	1		T165	3
valid_sources[0x19]	1996	1		T38	2		T84	1		T200	1
valid_sources[0x1a]	379	1		T201	4		T81	1		T202	2
valid_sources[0x1b]	427	1		T25	6		T56	2		T70	1
valid_sources[0x1c]	485	1		T108	1		T202	2		T148	2
valid_sources[0x1d]	489	1		T40	1		T187	1		T203	1
valid_sources[0x1e]	403	1		T204	1		T205	1		T206	2
valid_sources[0x1f]	416	1		T108	1		T18	1		T175	1
valid_sources[0x20]	512	1		T40	1		T88	15		T207	1
valid_sources[0x21]	401	1		T37	1		T180	1		T208	5
valid_sources[0x22]	374	1		T185	1		T179	1		T209	1
valid_sources[0x23]	401	1		T93	1		T99	1		T183	2
valid_sources[0x24]	343	1		T11	1		T37	2		T142	2
valid_sources[0x25]	394	1		T210	1		T211	4		T64	4
valid_sources[0x26]	391	1		T109	3		T212	9		T213	1
valid_sources[0x27]	498	1		T214	2		T72	1		T190	1
valid_sources[0x28]	486	1		T8	1		T39	12		T18	1
valid_sources[0x29]	323	1		T40	3		T149	1		T196	1
valid_sources[0x2a]	361	1		T89	1		T215	18		T54	1
valid_sources[0x2b]	311	1		T30	9		T192	1		T147	1
valid_sources[0x2c]	719	1		T75	3		T192	1		T67	1
valid_sources[0x2d]	448	1		T66	2		T207	1		T216	1
valid_sources[0x2e]	564	1		T108	1		T217	2		T218	1
valid_sources[0x2f]	384	1		T80	1		T209	1		T70	1
valid_sources[0x30]	440	1		T217	1		T219	1		T71	1
valid_sources[0x31]	348	1		T5	9		T109	1		T91	1
valid_sources[0x32]	399	1		T11	1		T108	1		T101	15
valid_sources[0x33]	365	1		T6	3		T11	1		T147	1
valid_sources[0x34]	301	1		T84	1		T31	1		T190	1
valid_sources[0x35]	375	1		T28	4		T92	2		T219	1
valid_sources[0x36]	632	1		T1	1		T184	1		T220	1
valid_sources[0x37]	443	1		T59	9		T221	2		T203	1
valid_sources[0x38]	450	1		T13	1		T31	1		T91	1
valid_sources[0x39]	303	1		T188	2		T204	1		T149	1
valid_sources[0x3a]	403	1		T95	1		T222	1		T223	3
valid_sources[0x3b]	333	1		T224	1		T95	1		T149	1
valid_sources[0x3c]	296	1		T75	1		T66	2		T146	1
valid_sources[0x3d]	360	1		T97	1		T225	1		T76	3
valid_sources[0x3e]	366	1		T95	1		T185	1		T226	9
valid_sources[0x3f]	353	1		T8	1		T13	2		T89	1
valid_sources[0x40]	549	1		T13	1		T224	3		T105	1
valid_sources[0x41]	392	1		T227	18		T82	1		T79	2
valid_sources[0x42]	339	1		T92	1		T219	1		T66	7
valid_sources[0x43]	364	1		T89	2		T188	1		T192	1
valid_sources[0x44]	340	1		T19	15		T80	1		T201	6
valid_sources[0x45]	469	1		T4	2		T40	1		T108	1
valid_sources[0x46]	469	1		T18	1		T70	1		T193	1
valid_sources[0x47]	335	1		T108	1		T18	1		T92	1
valid_sources[0x48]	363	1		T8	1		T18	1		T92	1
valid_sources[0x49]	590	1		T1	1		T55	1		T61	1
valid_sources[0x4a]	440	1		T89	1		T210	1		T146	1
valid_sources[0x4b]	402	1		T11	1		T61	1		T135	1
valid_sources[0x4c]	384	1		T18	1		T61	1		T147	1
valid_sources[0x4d]	525	1		T35	1		T75	2		T146	1
valid_sources[0x4e]	365	1		T16	1		T55	1		T34	1
valid_sources[0x4f]	454	1		T188	2		T228	1		T71	1
valid_sources[0x50]	369	1		T229	1		T80	1		T230	1
valid_sources[0x51]	479	1		T95	2		T180	4		T107	1
valid_sources[0x52]	338	1		T66	1		T180	3		T231	1
valid_sources[0x53]	327	1		T153	3		T67	2		T218	1
valid_sources[0x54]	527	1		T58	4		T109	2		T190	1
valid_sources[0x55]	639	1		T14	3		T36	1		T231	1
valid_sources[0x56]	397	1		T232	1		T165	3		T41	2
valid_sources[0x57]	790	1		T7	1		T135	1		T91	1
valid_sources[0x58]	1097	1		T4	3		T106	1		T84	1
valid_sources[0x59]	483	1		T86	3		T134	4		T80	1
valid_sources[0x5a]	369	1		T108	1		T140	1		T151	5
valid_sources[0x5b]	360	1		T57	9		T219	2		T207	4
valid_sources[0x5c]	313	1		T15	1		T95	1		T80	1
valid_sources[0x5d]	327	1		T230	1		T233	5		T74	1
valid_sources[0x5e]	472	1		T55	1		T108	1		T100	11
valid_sources[0x5f]	389	1		T108	1		T29	1		T234	1
valid_sources[0x60]	446	1		T31	1		T94	1		T182	1
valid_sources[0x61]	450	1		T90	10		T91	1		T198	2
valid_sources[0x62]	435	1		T3	1		T7	1		T235	9
valid_sources[0x63]	555	1		T106	1		T204	1		T236	18
valid_sources[0x64]	556	1		T23	1		T37	1		T218	1
valid_sources[0x65]	324	1		T3	1		T108	1		T70	1
valid_sources[0x66]	288	1		T55	1		T104	1		T178	1
valid_sources[0x67]	336	1		T108	1		T92	1		T237	18
valid_sources[0x68]	360	1		T179	1		T238	2		T142	2
valid_sources[0x69]	400	1		T92	2		T229	1		T191	1
valid_sources[0x6a]	499	1		T37	2		T106	1		T239	2
valid_sources[0x6b]	408	1		T36	2		T32	1		T240	1
valid_sources[0x6c]	629	1		T93	2		T241	1		T97	1
valid_sources[0x6d]	434	1		T242	1		T243	1		T244	1
valid_sources[0x6e]	428	1		T16	1		T40	2		T209	1
valid_sources[0x6f]	412	1		T211	1		T199	1		T245	3
valid_sources[0x70]	384	1		T219	3		T205	1		T165	2
valid_sources[0x71]	774	1		T1	2		T81	1		T242	2
valid_sources[0x72]	498	1		T55	1		T84	1		T204	1
valid_sources[0x73]	500	1		T104	1		T232	1		T225	1
valid_sources[0x74]	364	1		T148	1		T206	2		T165	8
valid_sources[0x75]	389	1		T12	18		T246	7		T108	1
valid_sources[0x76]	308	1		T55	1		T89	2		T18	1
valid_sources[0x77]	299	1		T8	1		T82	1		T247	1
valid_sources[0x78]	385	1		T24	5		T86	3		T195	1
valid_sources[0x79]	561	1		T89	1		T175	1		T83	1
valid_sources[0x7a]	336	1		T89	1		T91	2		T72	2
valid_sources[0x7b]	324	1		T224	1		T248	1		T249	1
valid_sources[0x7c]	395	1		T6	2		T91	1		T179	1
valid_sources[0x7d]	307	1		T13	2		T86	4		T28	1
valid_sources[0x7e]	571	1		T2	2		T15	1		T80	2
valid_sources[0x7f]	324	1		T13	1		T40	1		T20	15
valid_sources[0x80]	478	1		T175	1		T250	18		T218	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19909

1

T1

1

T2

2

T3

3

values[0x0]

all_enables

biggest_size

21675

1

T1

2

T2

2

T3

3

values[0x1]

all_enables

biggest_size

20585

1

T1

1

T3

1

T4

1