Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	60085	1		T1	3		T2	8		T3	5
full_word	63149	1		T1	4		T2	4		T3	7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	123084	1		T1	7		T2	12		T3	12
auto[TlIntgErrCmd]	41	1		T41	2		T115	4		T169	3
auto[TlIntgErrData]	48	1		T41	4		T136	9		T115	2
auto[TlIntgErrBoth]	61	1		T41	4		T136	1		T115	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	63473	1		T1	2		T2	4		T3	4
auto[1]	59761	1		T1	5		T2	8		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	43334	1		T1	1		T2	2		T3	1
auto[TlIntgErrNone]	partial	auto[1]	16617	1		T1	2		T2	6		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	20074	1		T1	1		T2	2		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	43059	1		T1	3		T2	2		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	17	1		T41	1		T115	2		T169	2
auto[TlIntgErrCmd]	partial	auto[1]	22	1		T41	1		T115	2		T169	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T171	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T172	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	19	1		T41	1		T136	5		T115	1
auto[TlIntgErrData]	partial	auto[1]	19	1		T41	2		T136	2		T169	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T168	1		T173	1		T174	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T41	1		T136	2		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	23	1		T41	1		T115	2		T169	1
auto[TlIntgErrBoth]	partial	auto[1]	34	1		T41	3		T115	2		T169	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T172	1		T174	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T136	1		T173	1		-	-