Line Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=4,Width=3,Secure=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 76 | 7 | 6 | 85.71 |
ALWAYS | 88 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
0 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
|
unreachable |
92 |
1 |
1 |
93 |
0 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
Line Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=8,Width=4,Secure=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 76 | 7 | 6 | 85.71 |
ALWAYS | 88 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
0 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
|
unreachable |
92 |
1 |
1 |
93 |
0 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
Line Coverage for Module :
prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 76 | 7 | 6 | 85.71 |
ALWAYS | 88 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
0 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
|
unreachable |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
0 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Module :
prim_fifo_sync_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
76 |
4 |
4 |
100.00 |
IF |
88 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 78 if (clr_i)
-3-: 80 if (wptr_wrap)
-4-: 82 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T25,T26,T27 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T4 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 88 if ((!rst_ni))
-2-: 90 if (clr_i)
-3-: 92 if (rptr_wrap)
-4-: 94 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T25,T26,T27 |
0 |
0 |
0 |
1 |
Covered |
T2,T3,T4 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 76 | 7 | 6 | 85.71 |
ALWAYS | 88 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
0 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
|
unreachable |
92 |
1 |
1 |
93 |
0 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
6 |
75.00 |
IF |
76 |
4 |
3 |
75.00 |
IF |
88 |
4 |
3 |
75.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 78 if (clr_i)
-3-: 80 if (wptr_wrap)
-4-: 82 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 88 if ((!rst_ni))
-2-: 90 if (clr_i)
-3-: 92 if (rptr_wrap)
-4-: 94 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
Covered |
T4,T5,T7 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 76 | 7 | 6 | 85.71 |
ALWAYS | 88 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
0 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
|
unreachable |
92 |
1 |
1 |
93 |
0 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
6 |
75.00 |
IF |
76 |
4 |
3 |
75.00 |
IF |
88 |
4 |
3 |
75.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 78 if (clr_i)
-3-: 80 if (wptr_wrap)
-4-: 82 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 88 if ((!rst_ni))
-2-: 90 if (clr_i)
-3-: 92 if (rptr_wrap)
-4-: 94 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
Covered |
T2,T3,T6 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 76 | 7 | 6 | 85.71 |
ALWAYS | 88 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
0 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
|
unreachable |
92 |
1 |
1 |
93 |
0 |
1 |
94 |
1 |
1 |
95 |
1 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
6 |
75.00 |
IF |
76 |
4 |
3 |
75.00 |
IF |
88 |
4 |
3 |
75.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 78 if (clr_i)
-3-: 80 if (wptr_wrap)
-4-: 82 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
Covered |
T2,T3,T4 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 88 if ((!rst_ni))
-2-: 90 if (clr_i)
-3-: 92 if (rptr_wrap)
-4-: 94 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
1 |
Covered |
T2,T3,T4 |
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 76 | 7 | 6 | 85.71 |
ALWAYS | 88 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
0 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
|
unreachable |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
0 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
6 |
75.00 |
IF |
76 |
4 |
3 |
75.00 |
IF |
88 |
4 |
3 |
75.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 78 if (clr_i)
-3-: 80 if (wptr_wrap)
-4-: 82 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T25,T26,T27 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 88 if ((!rst_ni))
-2-: 90 if (clr_i)
-3-: 92 if (rptr_wrap)
-4-: 94 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T25,T26,T27 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 76 | 7 | 6 | 85.71 |
ALWAYS | 88 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
0 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
|
unreachable |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
0 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
6 |
75.00 |
IF |
76 |
4 |
3 |
75.00 |
IF |
88 |
4 |
3 |
75.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 78 if (clr_i)
-3-: 80 if (wptr_wrap)
-4-: 82 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T25,T26,T27 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 88 if ((!rst_ni))
-2-: 90 if (clr_i)
-3-: 92 if (rptr_wrap)
-4-: 94 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T25,T26,T27 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 18 | 16 | 88.89 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
ALWAYS | 76 | 7 | 6 | 85.71 |
ALWAYS | 88 | 7 | 6 | 85.71 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
30 |
1 |
1 |
32 |
1 |
1 |
33 |
1 |
1 |
76 |
1 |
1 |
77 |
1 |
1 |
78 |
1 |
1 |
79 |
|
unreachable |
80 |
1 |
1 |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
0 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
91 |
|
unreachable |
92 |
1 |
1 |
93 |
1 |
1 |
94 |
1 |
1 |
95 |
0 |
1 |
|
|
|
MISSING_ELSE |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
6 |
75.00 |
IF |
76 |
4 |
3 |
75.00 |
IF |
88 |
4 |
3 |
75.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 if ((!rst_ni))
-2-: 78 if (clr_i)
-3-: 80 if (wptr_wrap)
-4-: 82 if (incr_wptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T25,T26,T27 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 88 if ((!rst_ni))
-2-: 90 if (clr_i)
-3-: 92 if (rptr_wrap)
-4-: 94 if (incr_rptr_i)
Branches:
-1- | -2- | -3- | -4- | Status | Tests |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
- |
Unreachable |
|
0 |
0 |
1 |
- |
Covered |
T25,T26,T27 |
0 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |