Unified Coverage Report :: Module :: prim_generic_ram_1p

Module : prim_generic_ram_1p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_no_stubbed_memory.u_memory_1p.u_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_1p.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T3,T4
1	0	Covered	T8,T11,T12
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1p

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	289	289	0	0
gen_wmask[0].MaskCheck_A	114527811	1553	0	0
gen_wmask[1].MaskCheck_A	114527811	1553	0	0
gen_wmask[2].MaskCheck_A	114527811	1553	0	0
gen_wmask[3].MaskCheck_A	114527811	1553	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	289	289	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527811	1553	0	0
T2	403738	2	0	0
T3	404950	16	0	0
T4	401960	3	0	0
T5	401711	3	0	0
T6	405211	11	0	0
T7	402005	3	0	0
T8	404714	11	0	0
T9	402337	3	0	0
T10	401762	3	0	0
T11	403786	9	0	0

gen_wmask[1].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527811	1553	0	0
T2	403738	2	0	0
T3	404950	16	0	0
T4	401960	3	0	0
T5	401711	3	0	0
T6	405211	11	0	0
T7	402005	3	0	0
T8	404714	11	0	0
T9	402337	3	0	0
T10	401762	3	0	0
T11	403786	9	0	0

gen_wmask[2].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527811	1553	0	0
T2	403738	2	0	0
T3	404950	16	0	0
T4	401960	3	0	0
T5	401711	3	0	0
T6	405211	11	0	0
T7	402005	3	0	0
T8	404714	11	0	0
T9	402337	3	0	0
T10	401762	3	0	0
T11	403786	9	0	0

gen_wmask[3].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527811	1553	0	0
T2	403738	2	0	0
T3	404950	16	0	0
T4	401960	3	0	0
T5	401711	3	0	0
T6	405211	11	0	0
T7	402005	3	0	0
T8	404714	11	0	0
T9	402337	3	0	0
T10	401762	3	0	0
T11	403786	9	0	0