Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.40	96.38	62.63	92.99		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	115298931	11232	0	0
ep_in_enable_rd_A	115298931	1918	0	0
ep_out_enable_rd_A	115298931	1758	0	0
in_iso_rd_A	115298931	1795	0	0
intr_enable_rd_A	115298931	2304	0	0
out_iso_rd_A	115298931	2216	0	0
phy_config_rd_A	115298931	1145	0	0
phy_pins_drive_rd_A	115298931	1547	0	0
rxenable_setup_rd_A	115298931	2188	0	0
set_nak_out_rd_A	115298931	1652	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115298931	11232	0	0
T41	12194	4	0	0
T42	5308	1082	0	0
T43	8782	638	0	0
T49	16041	23	0	0
T112	12047	14	0	0
T113	18551	18	0	0
T115	12354	2	0	0
T116	6482	7	0	0
T117	5841	8	0	0
T136	15098	1	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115298931	1918	0	0
T46	2604	12	0	0
T110	1903	5	0	0
T112	12047	36	0	0
T113	18551	16	0	0
T116	6482	36	0	0
T121	12276	49	0	0
T128	2233	2	0	0
T133	6622	28	0	0
T136	15098	212	0	0
T166	13236	153	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115298931	1758	0	0
T46	2604	9	0	0
T112	12047	20	0	0
T113	18551	30	0	0
T116	6482	4	0	0
T121	12276	83	0	0
T128	2233	42	0	0
T133	6622	1	0	0
T136	15098	139	0	0
T166	13236	79	0	0
T167	3857	32	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115298931	1795	0	0
T45	1943	6	0	0
T46	2604	9	0	0
T110	1903	9	0	0
T112	12047	60	0	0
T113	18551	13	0	0
T116	6482	64	0	0
T121	12276	49	0	0
T133	6622	37	0	0
T136	15098	274	0	0
T166	13236	137	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115298931	2304	0	0
T46	2604	3	0	0
T110	1903	31	0	0
T112	12047	20	0	0
T113	18551	91	0	0
T116	6482	4	0	0
T121	12276	110	0	0
T133	6622	25	0	0
T136	15098	234	0	0
T166	13236	210	0	0
T167	3857	10	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115298931	2216	0	0
T45	1943	3	0	0
T112	12047	26	0	0
T113	18551	17	0	0
T116	6482	40	0	0
T121	12276	16	0	0
T128	2233	10	0	0
T133	6622	34	0	0
T136	15098	300	0	0
T166	13236	172	0	0
T167	3857	35	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115298931	1145	0	0
T45	1943	1	0	0
T46	2604	5	0	0
T110	1903	13	0	0
T112	12047	28	0	0
T113	18551	18	0	0
T116	6482	7	0	0
T121	12276	37	0	0
T133	6622	14	0	0
T136	15098	90	0	0
T166	13236	65	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115298931	1547	0	0
T46	2604	11	0	0
T112	12047	61	0	0
T113	18551	86	0	0
T116	6482	42	0	0
T121	12276	35	0	0
T128	2233	6	0	0
T133	6622	21	0	0
T136	15098	224	0	0
T166	13236	127	0	0
T167	3857	14	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115298931	2188	0	0
T46	2604	12	0	0
T110	1903	22	0	0
T112	12047	29	0	0
T113	18551	4	0	0
T116	6482	59	0	0
T121	12276	114	0	0
T128	2233	9	0	0
T133	6622	21	0	0
T136	15098	387	0	0
T166	13236	132	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115298931	1652	0	0
T45	1943	4	0	0
T46	2604	9	0	0
T110	1903	1	0	0
T112	12047	37	0	0
T113	18551	49	0	0
T116	6482	35	0	0
T121	12276	12	0	0
T128	2233	51	0	0
T136	15098	240	0	0
T166	13236	135	0	0