Line Coverage for Instance : tb.dut.u_reg.u_intr_state_pkt_received.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_pkt_received.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 5 | 50.00 |
Logical | 10 | 5 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T4 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_pkt_sent.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_pkt_sent.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 5 | 50.00 |
Logical | 10 | 5 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T8,T11,T12 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_disconnected.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_disconnected.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 6 | 60.00 |
Logical | 10 | 6 | 60.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_host_lost.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_host_lost.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T52,T46,T47 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T52,T46,T47 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T52,T46,T47 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_link_reset.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_link_reset.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_link_suspend.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_link_suspend.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T51,T45,T46 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T51,T45,T46 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T45,T46 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_link_resume.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_link_resume.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T52,T51,T45 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T52,T51,T45 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T52,T51,T45 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_av_out_empty.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_av_out_empty.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 5 | 50.00 |
Logical | 10 | 5 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_full.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_full.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 5 | 50.00 |
Logical | 10 | 5 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T51,T46,T47 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_av_overflow.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_av_overflow.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T52,T45,T46 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T52,T45,T46 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T52,T45,T46 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_link_in_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_link_in_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T52,T51,T47 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T52,T51,T47 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T52,T51,T47 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_crc_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_crc_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T52,T51,T45 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T52,T51,T45 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T52,T51,T45 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_pid_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_pid_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T51,T46,T47 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T51,T46,T47 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T46,T47 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_bitstuff_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_bitstuff_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T52,T51,T46 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T52,T51,T46 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T52,T51,T46 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_frame.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_frame.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T51 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T51 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_powered.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_powered.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_link_out_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_link_out_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 7 | 70.00 |
Logical | 10 | 7 | 70.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T2,T3,T6 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T6 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T6 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_av_setup_empty.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_av_setup_empty.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 5 | 50.00 |
Logical | 10 | 5 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_pkt_received.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_pkt_received.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_pkt_received.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_pkt_sent.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_pkt_sent.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_pkt_sent.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_disconnected.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_disconnected.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_disconnected.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_host_lost.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_host_lost.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_host_lost.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_reset.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_reset.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_reset.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_suspend.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_suspend.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_suspend.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_resume.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_resume.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_resume.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_av_out_empty.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_av_out_empty.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_av_out_empty.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_full.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_full.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_full.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_av_overflow.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_av_overflow.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_av_overflow.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_in_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_in_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_link_in_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_crc_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_crc_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_crc_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_pid_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_pid_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_pid_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_bitstuff_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_bitstuff_err.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_bitstuff_err.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_frame.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_frame.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T4,T5 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T4,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_frame.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T4,T5 |
0 |
Covered |
T1,T2,T3 |