Module Definition
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Module : usb_fs_nb_out_pe
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.31 86.51 75.81 50.00 79.25 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe 78.31 86.51 75.81 50.00 79.25 100.00



Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.31 86.51 75.81 50.00 79.25 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.31 86.51 75.81 50.00 79.25 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.33 100.00 50.00 100.00 u_usb_fs_nb_pe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usb_fs_nb_out_pe
Line No.TotalCoveredPercent
TOTAL12610986.51
CONT_ASSIGN8811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17611100.00
ALWAYS18266100.00
ALWAYS19444100.00
ALWAYS210543870.37
CONT_ASSIGN32411100.00
ALWAYS32733100.00
CONT_ASSIGN33711100.00
ALWAYS34033100.00
ALWAYS3497685.71
CONT_ASSIGN36311100.00
ALWAYS36655100.00
ALWAYS37699100.00
ALWAYS39333100.00
ALWAYS40566100.00
CONT_ASSIGN42111100.00
ALWAYS42466100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
129 1 1
130 1 1
132 1 1
138 1 1
142 1 1
146 1 1
150 1 1
155 1 1
161 1 1
162 1 1
169 1 1
170 1 1
173 1 1
174 1 1
176 1 1
182 1 1
183 1 1
185 1 1
186 1 1
187 1 1
188 1 1
MISSING_ELSE
194 1 1
195 1 1
197 1 1
198 1 1
MISSING_ELSE
210 1 1
211 1 1
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
219 1 1
223 1 1
224 1 1
225 1 1
227 1 1
235 1 1
237 1 1
238 1 1
239 1 1
240 0 1
242 1 1
247 1 1
251 0 1
252 1 1
255 0 1
256 0 1
257 0 1
258 0 1
259 1 1
261 0 1
262 0 1
263 1 1
264 1 1
266 1 1
271 1 1
272 1 1
274 1 1
276 1 1
278 0 1
279 0 1
281 1 1
282 1 1
283 1 1
287 1 1
288 0 1
289 1 1
290 1 1
291 1 1
293 1 1
294 1 1
295 1 1
302 0 1
304 0 1
306 0 1
309 0 1
310 0 1
324 1 1
327 1 1
328 1 1
330 1 1
337 1 1
340 1 1
341 1 1
343 1 1
349 1 1
351 1 1
352 1 1
353 1 1
354 1 1
MISSING_ELSE
357 1 1
358 0 1
MISSING_ELSE
363 1 1
366 1 1
367 1 1
368 1 1
369 1 1
371 1 1
376 1 1
377 1 1
378 1 1
379 1 1
381 1 1
382 1 1
383 1 1
384 1 1
386 1 1
393 1 1
394 1 1
396 1 1
405 1 1
406 1 1
408 1 1
409 1 1
410 1 1
411 1 1
MISSING_ELSE
421 1 1
424 1 1
425 1 1
427 1 1
428 1 1
429 1 1
430 1 1
MISSING_ELSE


Cond Coverage for Module : usb_fs_nb_out_pe
TotalCoveredPercent
Conditions1249475.81
Logical1249475.81
Non-Logical00
Event00

 LINE       132
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101CoveredT2,T3,T4
1110Not Covered
1111CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (token_received && (rx_pid == UsbPidOut))
             -------1------    ----------2----------
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT1,T4,T5
11CoveredT2,T3,T6

 LINE       138
 SUB-EXPRESSION (rx_pid == UsbPidOut)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T6

 LINE       142
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT2,T3,T6
11CoveredT1,T4,T5

 LINE       142
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       146
 EXPRESSION (rx_pkt_end_i && ((!rx_pkt_valid_i)))
             ------1-----    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       150
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)))
             ------1-----    -------2------    --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101Not Covered
110CoveredT1,T2,T3
111CoveredT2,T3,T4

 LINE       150
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T4

 LINE       150
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       150
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) ))
             ------1-----    -------2------    -----------------------------3----------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT2,T3,T4
111CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) )
                    --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       155
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T4

 LINE       155
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       155
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       162
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       173
 EXPRESSION (out_ep_enabled_i[out_ep_index_d] & ep_in_hw)
             ----------------1---------------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       176
 EXPRESSION (data_packet_received && ep_active && (rx_pid_i[3] != data_toggle_q[out_ep_index_d]))
             ----------1---------    ----2----    -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT2,T3,T4
111Not Covered

 LINE       176
 SUB-EXPRESSION (rx_pid_i[3] != data_toggle_q[out_ep_index_d])
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       185
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       187
 EXPRESSION (out_token_received && ep_active)
             ---------1--------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T6

 LINE       223
 EXPRESSION (ep_active && (out_token_received || (setup_token_received && ep_is_control)))
             ----1----    -------------------------------2-------------------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       223
 SUB-EXPRESSION (out_token_received || (setup_token_received && ep_is_control))
                 ---------1--------    -------------------2-------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T7
10CoveredT2,T3,T6

 LINE       223
 SUB-EXPRESSION (setup_token_received && ep_is_control)
                 ----------1---------    ------2------
-1--2-StatusTests
01CoveredT4,T5,T7
10CoveredT1,T16,T17
11CoveredT4,T5,T7

 LINE       239
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------
-1-StatusTests
0CoveredT2,T3,T4
1Not Covered

 LINE       247
 EXPRESSION (((!ep_is_control)) && out_ep_iso_i[out_ep_index] && data_packet_received)
             ---------1--------    -------------2------------    ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T6
110Not Covered
111Not Covered

 LINE       252
 EXPRESSION (bad_data_toggle && ((!out_ep_stall_i[out_ep_index])))
             -------1-------    ----------------2----------------
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11Not Covered

 LINE       259
 EXPRESSION (invalid_packet_received || non_data_packet_received)
             -----------1-----------    ------------2-----------
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10Not Covered

 LINE       276
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT4,T5,T7
01Not Covered
10Not Covered

 LINE       289
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT2,T3,T6
01Not Covered
10Not Covered

 LINE       304
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       343
 EXPRESSION (link_reset_i ? StIdle : out_xact_state_next)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       351
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       396
 EXPRESSION ((out_xact_state == StRcvdDataStart) && rx_data_put_i)
             -----------------1-----------------    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       396
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       408
 EXPRESSION ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))
             -------------1------------    --------------2--------------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       408
 SUB-EXPRESSION (out_xact_state == StIdle)
                -------------1------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       408
 SUB-EXPRESSION (out_xact_state == StRcvdOut)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       410
 EXPRESSION (out_ep_data_put_o && out_ep_full_i[out_ep_index])
             --------1--------    -------------2-------------
-1--2-StatusTests
01CoveredT2,T3,T6
10CoveredT2,T3,T4
11CoveredT2,T3,T6

 LINE       421
 EXPRESSION (((!nak_out_transaction)) && ((~&out_ep_put_addr_o)) && out_ep_data_put_o)
             ------------1-----------    -----------2-----------    --------3--------
-1--2--3-StatusTests
011CoveredT2,T3,T6
101CoveredT18,T19,T20
110CoveredT1,T2,T3
111CoveredT2,T3,T4

 LINE       427
 EXPRESSION (out_xact_state == StRcvdOut)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       429
 EXPRESSION ((out_xact_state == StRcvdDataStart) && increment_addr)
             -----------------1-----------------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       429
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

FSM Coverage for Module : usb_fs_nb_out_pe
Summary for FSM :: out_xact_state
TotalCoveredPercent
States 5 4 80.00 (Not included in score)
Transitions 8 4 50.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: out_xact_state
states   Line No.   Covered   Tests   
StIdle 343 Covered T1,T2,T3
StRcvdDataEnd 264 Covered T2,T3,T4
StRcvdDataStart 238 Covered T2,T3,T4
StRcvdIsoDataEnd 251 Not Covered
StRcvdOut 224 Covered T2,T3,T4


transitions   Line No.   Covered   Tests   
StIdle->StRcvdOut 224 Covered T2,T3,T4
StRcvdDataEnd->StIdle 343 Covered T2,T3,T4
StRcvdDataStart->StIdle 343 Not Covered
StRcvdDataStart->StRcvdDataEnd 264 Covered T2,T3,T4
StRcvdDataStart->StRcvdIsoDataEnd 251 Not Covered
StRcvdIsoDataEnd->StIdle 343 Not Covered
StRcvdOut->StIdle 343 Not Covered
StRcvdOut->StRcvdDataStart 238 Covered T2,T3,T4



Branch Coverage for Module : usb_fs_nb_out_pe
Line No.TotalCoveredPercent
Branches 53 42 79.25
TERNARY 162 2 1 50.00
IF 182 4 4 100.00
IF 194 3 3 100.00
CASE 219 18 9 50.00
IF 327 2 2 100.00
IF 340 3 3 100.00
IF 351 3 3 100.00
IF 357 2 1 50.00
IF 366 3 3 100.00
IF 376 3 3 100.00
IF 393 2 2 100.00
IF 405 4 4 100.00
IF 424 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 162 (ep_in_hw) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 182 if ((!rst_ni)) -2-: 185 if ((setup_token_received && ep_active)) -3-: 187 if ((out_token_received && ep_active))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T4,T5
0 0 1 Covered T2,T3,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 194 if ((!rst_ni)) -2-: 197 if (rx_data_put_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 219 case (out_xact_state) -2-: 223 if ((ep_active && (out_token_received || (setup_token_received && ep_is_control)))) -3-: 237 if (rx_pkt_start_i) -4-: 239 if ((timeout_cntdown_q == '0)) -5-: 247 if ((((!ep_is_control) && out_ep_iso_i[out_ep_index]) && data_packet_received)) -6-: 252 if ((bad_data_toggle && (!out_ep_stall_i[out_ep_index]))) -7-: 259 if ((invalid_packet_received || non_data_packet_received)) -8-: 263 if (data_packet_received) -9-: 274 if (current_xact_setup_q) -10-: 276 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -11-: 287 if (out_ep_stall_i[out_ep_index]) -12-: 289 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -13-: 304 if ((nak_out_transaction | out_ep_full_i[out_ep_index]))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTests
StIdle 1 - - - - - - - - - - - Covered T2,T3,T4
StIdle 0 - - - - - - - - - - - Covered T1,T2,T3
StRcvdOut - 1 - - - - - - - - - - Covered T2,T3,T4
StRcvdOut - 0 1 - - - - - - - - - Not Covered
StRcvdOut - 0 0 - - - - - - - - - Covered T2,T3,T4
StRcvdDataStart - - - 1 - - - - - - - - Not Covered
StRcvdDataStart - - - 0 1 - - - - - - - Not Covered
StRcvdDataStart - - - 0 0 1 - - - - - - Not Covered
StRcvdDataStart - - - 0 0 0 1 - - - - - Covered T2,T3,T4
StRcvdDataStart - - - 0 0 0 0 - - - - - Covered T2,T3,T4
StRcvdDataEnd - - - - - - - 1 1 - - - Not Covered
StRcvdDataEnd - - - - - - - 1 0 - - - Covered T4,T5,T7
StRcvdDataEnd - - - - - - - 0 - 1 - - Not Covered
StRcvdDataEnd - - - - - - - 0 - 0 1 - Covered T2,T3,T6
StRcvdDataEnd - - - - - - - 0 - 0 0 - Covered T2,T3,T6
StRcvdIsoDataEnd - - - - - - - - - - - 1 Not Covered
StRcvdIsoDataEnd - - - - - - - - - - - 0 Not Covered
default - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 327 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 340 if ((!rst_ni)) -2-: 343 (link_reset_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 351 if ((setup_token_received && ep_active)) -2-: 353 if (new_pkt_end)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T5
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 357 if (out_datatog_we_i)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 366 if ((!rst_ni)) -2-: 368 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 376 if ((!rst_ni)) -2-: 381 if (out_xact_start)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 393 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 405 if ((!rst_ni)) -2-: 408 if (((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))) -3-: 410 if ((out_ep_data_put_o && out_ep_full_i[out_ep_index]))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T2,T3,T6
0 0 0 Covered T2,T3,T4


LineNo. Expression -1-: 424 if ((!rst_ni)) -2-: 427 if ((out_xact_state == StRcvdOut)) -3-: 429 if (((out_xact_state == StRcvdDataStart) && increment_addr))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 1 Covered T2,T3,T4
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : usb_fs_nb_out_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutXactStateValid_A 114527811 114472164 0 0


OutXactStateValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114527811 114472164 0 0
T1 401695 401517 0 0
T2 403738 403597 0 0
T3 404950 404816 0 0
T4 401960 401788 0 0
T5 401711 401482 0 0
T6 405211 405084 0 0
T7 402005 401769 0 0
T8 404714 404598 0 0
T9 402337 402189 0 0
T10 401762 401494 0 0