Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56842	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	64297	1		T1	9		T2	3		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	71019	1		T1	4		T2	2		T3	4
values[0x0]	24545	1		T1	7		T2	4		T3	1
values[0x1]	25575	1		T1	4		T2	1		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37343	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	83796	1		T1	11		T2	4		T3	7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	623	1		T90	1		T102	1		T165	4
valid_sources[0x01]	441	1		T77	1		T63	1		T166	1
valid_sources[0x02]	396	1		T1	1		T17	1		T99	15
valid_sources[0x03]	407	1		T5	4		T14	7		T112	2
valid_sources[0x04]	419	1		T22	1		T90	1		T167	1
valid_sources[0x05]	483	1		T168	1		T169	2		T70	2
valid_sources[0x06]	406	1		T106	1		T170	1		T171	2
valid_sources[0x07]	448	1		T48	1		T172	1		T166	2
valid_sources[0x08]	386	1		T173	1		T174	1		T175	2
valid_sources[0x09]	384	1		T176	1		T177	3		T178	1
valid_sources[0x0a]	509	1		T22	1		T50	1		T101	7
valid_sources[0x0b]	463	1		T63	1		T26	1		T62	1
valid_sources[0x0c]	505	1		T82	4		T110	1		T84	9
valid_sources[0x0d]	404	1		T103	15		T66	1		T179	1
valid_sources[0x0e]	464	1		T180	1		T175	3		T181	1
valid_sources[0x0f]	419	1		T12	2		T16	1		T141	1
valid_sources[0x10]	529	1		T170	1		T64	1		T176	1
valid_sources[0x11]	445	1		T13	2		T182	1		T90	1
valid_sources[0x12]	411	1		T106	2		T183	1		T62	1
valid_sources[0x13]	402	1		T90	1		T110	1		T176	1
valid_sources[0x14]	447	1		T184	1		T97	1		T145	1
valid_sources[0x15]	377	1		T53	1		T185	1		T186	1
valid_sources[0x16]	579	1		T16	1		T187	2		T188	2
valid_sources[0x17]	442	1		T12	1		T189	1		T23	3
valid_sources[0x18]	463	1		T190	2		T69	1		T191	1
valid_sources[0x19]	535	1		T192	1		T193	1		T194	2
valid_sources[0x1a]	384	1		T16	1		T54	9		T195	1
valid_sources[0x1b]	402	1		T196	2		T185	1		T197	1
valid_sources[0x1c]	437	1		T3	1		T170	1		T77	1
valid_sources[0x1d]	591	1		T198	3		T104	1		T74	1
valid_sources[0x1e]	471	1		T77	1		T112	2		T17	2
valid_sources[0x1f]	504	1		T199	1		T173	1		T200	1
valid_sources[0x20]	564	1		T172	2		T108	1		T201	3
valid_sources[0x21]	452	1		T3	2		T16	1		T20	1
valid_sources[0x22]	502	1		T18	1		T196	1		T110	2
valid_sources[0x23]	376	1		T102	1		T202	2		T203	1
valid_sources[0x24]	452	1		T199	1		T204	1		T205	1
valid_sources[0x25]	529	1		T49	7		T64	1		T168	1
valid_sources[0x26]	495	1		T78	6		T31	4		T206	9
valid_sources[0x27]	477	1		T14	1		T21	1		T110	1
valid_sources[0x28]	398	1		T198	1		T63	3		T110	1
valid_sources[0x29]	479	1		T48	1		T170	3		T83	3
valid_sources[0x2a]	499	1		T207	4		T17	1		T66	3
valid_sources[0x2b]	378	1		T22	1		T208	3		T21	1
valid_sources[0x2c]	483	1		T3	1		T106	2		T76	9
valid_sources[0x2d]	411	1		T1	1		T90	1		T209	1
valid_sources[0x2e]	347	1		T16	1		T210	3		T121	1
valid_sources[0x2f]	579	1		T48	1		T15	3		T108	1
valid_sources[0x30]	608	1		T196	1		T211	1		T144	1
valid_sources[0x31]	417	1		T102	1		T212	1		T174	2
valid_sources[0x32]	592	1		T175	1		T168	2		T213	1
valid_sources[0x33]	514	1		T1	3		T10	1		T83	2
valid_sources[0x34]	345	1		T10	1		T13	1		T195	1
valid_sources[0x35]	593	1		T102	2		T111	1		T85	5
valid_sources[0x36]	403	1		T141	2		T106	1		T76	1
valid_sources[0x37]	395	1		T2	1		T102	1		T111	3
valid_sources[0x38]	444	1		T12	1		T214	1		T209	1
valid_sources[0x39]	496	1		T20	1		T53	1		T83	1
valid_sources[0x3a]	446	1		T199	1		T110	1		T201	2
valid_sources[0x3b]	361	1		T141	1		T176	1		T66	3
valid_sources[0x3c]	522	1		T13	1		T60	15		T180	1
valid_sources[0x3d]	394	1		T196	1		T215	2		T216	1
valid_sources[0x3e]	577	1		T8	18		T20	1		T106	1
valid_sources[0x3f]	575	1		T12	1		T111	1		T188	3
valid_sources[0x40]	481	1		T121	3		T34	1		T43	2
valid_sources[0x41]	388	1		T1	2		T6	2		T199	1
valid_sources[0x42]	423	1		T217	2		T74	1		T218	1
valid_sources[0x43]	410	1		T53	1		T219	13		T186	1
valid_sources[0x44]	448	1		T170	1		T200	1		T184	2
valid_sources[0x45]	485	1		T15	3		T16	1		T199	1
valid_sources[0x46]	433	1		T94	2		T220	2		T17	2
valid_sources[0x47]	392	1		T27	1		T221	1		T108	1
valid_sources[0x48]	492	1		T88	2		T222	1		T213	1
valid_sources[0x49]	441	1		T223	1		T145	2		T34	15
valid_sources[0x4a]	378	1		T1	1		T18	1		T186	1
valid_sources[0x4b]	475	1		T21	2		T55	1		T224	2
valid_sources[0x4c]	359	1		T1	1		T220	2		T79	2
valid_sources[0x4d]	499	1		T16	1		T203	1		T225	2
valid_sources[0x4e]	538	1		T106	1		T207	1		T17	1
valid_sources[0x4f]	432	1		T171	1		T185	1		T121	3
valid_sources[0x50]	536	1		T173	1		T226	7		T184	1
valid_sources[0x51]	603	1		T22	1		T170	1		T61	4
valid_sources[0x52]	552	1		T141	1		T227	7		T176	3
valid_sources[0x53]	472	1		T170	1		T53	1		T228	1
valid_sources[0x54]	379	1		T173	1		T179	1		T229	1
valid_sources[0x55]	390	1		T16	1		T20	1		T90	2
valid_sources[0x56]	526	1		T104	2		T230	1		T34	3
valid_sources[0x57]	436	1		T22	1		T178	1		T231	2
valid_sources[0x58]	580	1		T82	3		T94	3		T166	1
valid_sources[0x59]	474	1		T6	2		T11	9		T199	1
valid_sources[0x5a]	341	1		T18	2		T22	1		T141	2
valid_sources[0x5b]	508	1		T3	1		T198	2		T199	1
valid_sources[0x5c]	505	1		T21	1		T166	1		T220	1
valid_sources[0x5d]	374	1		T28	1		T77	1		T214	2
valid_sources[0x5e]	408	1		T189	1		T232	1		T233	2
valid_sources[0x5f]	428	1		T172	1		T110	1		T88	2
valid_sources[0x60]	450	1		T10	1		T110	1		T166	1
valid_sources[0x61]	424	1		T141	1		T76	1		T17	1
valid_sources[0x62]	455	1		T64	2		T234	3		T121	3
valid_sources[0x63]	576	1		T52	2		T199	1		T17	1
valid_sources[0x64]	506	1		T15	1		T112	2		T235	1
valid_sources[0x65]	465	1		T79	4		T236	2		T104	1
valid_sources[0x66]	474	1		T10	1		T235	2		T220	2
valid_sources[0x67]	460	1		T104	4		T217	1		T108	1
valid_sources[0x68]	371	1		T195	1		T237	1		T214	1
valid_sources[0x69]	581	1		T77	1		T238	1		T179	1
valid_sources[0x6a]	428	1		T198	1		T170	1		T83	1
valid_sources[0x6b]	448	1		T3	1		T77	2		T179	2
valid_sources[0x6c]	500	1		T82	1		T230	1		T239	1
valid_sources[0x6d]	410	1		T196	1		T106	1		T53	1
valid_sources[0x6e]	453	1		T10	1		T211	1		T240	5
valid_sources[0x6f]	427	1		T13	1		T106	1		T82	4
valid_sources[0x70]	511	1		T111	1		T32	9		T194	1
valid_sources[0x71]	428	1		T3	1		T16	1		T21	1
valid_sources[0x72]	467	1		T10	1		T241	2		T121	3
valid_sources[0x73]	434	1		T22	1		T172	1		T213	1
valid_sources[0x74]	567	1		T220	1		T17	1		T242	9
valid_sources[0x75]	498	1		T53	1		T243	7		T121	3
valid_sources[0x76]	420	1		T176	1		T184	1		T197	1
valid_sources[0x77]	592	1		T12	1		T196	1		T52	1
valid_sources[0x78]	608	1		T244	1		T183	2		T97	1
valid_sources[0x79]	405	1		T106	1		T200	1		T193	3
valid_sources[0x7a]	557	1		T180	1		T111	1		T184	1
valid_sources[0x7b]	517	1		T25	9		T102	5		T26	1
valid_sources[0x7c]	432	1		T5	2		T141	1		T182	1
valid_sources[0x7d]	453	1		T28	2		T173	1		T121	4
valid_sources[0x7e]	627	1		T6	4		T21	2		T112	1
valid_sources[0x7f]	482	1		T12	1		T90	1		T84	1
valid_sources[0x80]	429	1		T92	5		T167	1		T245	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21541

1

T1

2

T3

4

T4

1

values[0x0]

all_enables

biggest_size

22156

1

T1

6

T2

2

T3

1

values[0x1]

all_enables

biggest_size

20600

1

T1

1

T2

1

T3

1