Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	73538	1		T1	6		T2	4		T3	3
full_word	65474	1		T1	9		T2	3		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	138792	1		T1	15		T2	7		T3	9
auto[TlIntgErrCmd]	71	1		T35	2		T36	11		T57	1
auto[TlIntgErrData]	82	1		T35	4		T36	4		T57	4
auto[TlIntgErrBoth]	67	1		T35	4		T36	5		T57	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	73154	1		T1	4		T2	2		T3	4
auto[1]	65858	1		T1	11		T2	5		T3	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	51308	1		T1	2		T2	2		T4	5
auto[TlIntgErrNone]	partial	auto[1]	22036	1		T1	4		T2	2		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	21749	1		T1	2		T3	4		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	43699	1		T1	7		T2	3		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	22	1		T35	2		T36	1		T58	1
auto[TlIntgErrCmd]	partial	auto[1]	38	1		T36	8		T57	1		T58	3
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T36	2		T159	1		T163	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T58	1		T160	1		T164	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T35	1		T36	2		T58	6
auto[TlIntgErrData]	partial	auto[1]	34	1		T35	3		T36	1		T57	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T58	1		T160	1		T162	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T36	1		T57	1		T164	2
auto[TlIntgErrBoth]	partial	auto[0]	25	1		T35	2		T36	1		T57	2
auto[TlIntgErrBoth]	partial	auto[1]	36	1		T35	1		T36	2		T57	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T36	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T35	1		T36	1		T160	1