Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.59	96.38	62.63	93.93		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	114974898	13575	0	0
ep_in_enable_rd_A	114974898	1608	0	0
ep_out_enable_rd_A	114974898	1521	0	0
in_iso_rd_A	114974898	1732	0	0
intr_enable_rd_A	114974898	2641	0	0
out_iso_rd_A	114974898	2060	0	0
phy_config_rd_A	114974898	1063	0	0
phy_pins_drive_rd_A	114974898	1256	0	0
rxenable_setup_rd_A	114974898	1402	0	0
set_nak_out_rd_A	114974898	1775	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	13575	0	0
T34	10324	4	0	0
T35	14250	3	0	0
T36	10546	5	0	0
T57	6055	1	0	0
T58	15697	4	0	0
T59	14676	2	0	0
T114	12828	14	0	0
T115	15640	25	0	0
T116	3454	575	0	0
T117	3914	623	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	1608	0	0
T34	10324	68	0	0
T43	7371	41	0	0
T56	7466	40	0	0
T59	14676	257	0	0
T114	12828	53	0	0
T115	15640	16	0	0
T118	7250	57	0	0
T122	11921	29	0	0
T123	3880	45	0	0
T158	14706	224	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	1521	0	0
T34	10324	56	0	0
T43	7371	77	0	0
T56	7466	28	0	0
T59	14676	260	0	0
T114	12828	69	0	0
T115	15640	33	0	0
T118	7250	11	0	0
T122	11921	11	0	0
T123	3880	83	0	0
T158	14706	197	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	1732	0	0
T34	10324	56	0	0
T43	7371	49	0	0
T56	7466	22	0	0
T59	14676	345	0	0
T114	12828	68	0	0
T115	15640	49	0	0
T118	7250	3	0	0
T122	11921	11	0	0
T123	3880	81	0	0
T158	14706	280	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	2641	0	0
T34	10324	46	0	0
T43	7371	53	0	0
T56	7466	13	0	0
T59	14676	486	0	0
T114	12828	86	0	0
T115	15640	91	0	0
T118	7250	82	0	0
T122	11921	13	0	0
T123	3880	88	0	0
T158	14706	477	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	2060	0	0
T34	10324	48	0	0
T43	7371	26	0	0
T56	7466	71	0	0
T59	14676	293	0	0
T114	12828	75	0	0
T115	15640	67	0	0
T118	7250	47	0	0
T122	11921	13	0	0
T123	3880	71	0	0
T158	14706	257	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	1063	0	0
T34	10324	8	0	0
T43	7371	28	0	0
T56	7466	26	0	0
T59	14676	102	0	0
T114	12828	12	0	0
T115	15640	38	0	0
T118	7250	3	0	0
T122	11921	18	0	0
T123	3880	5	0	0
T158	14706	177	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	1256	0	0
T34	10324	10	0	0
T43	7371	12	0	0
T56	7466	20	0	0
T59	14676	248	0	0
T114	12828	37	0	0
T115	15640	23	0	0
T118	7250	49	0	0
T122	11921	40	0	0
T123	3880	22	0	0
T158	14706	156	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	1402	0	0
T34	10324	6	0	0
T43	7371	52	0	0
T56	7466	46	0	0
T59	14676	201	0	0
T114	12828	90	0	0
T115	15640	55	0	0
T118	7250	8	0	0
T122	11921	22	0	0
T123	3880	8	0	0
T158	14706	121	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	1775	0	0
T34	10324	6	0	0
T43	7371	52	0	0
T56	7466	63	0	0
T59	14676	245	0	0
T114	12828	90	0	0
T115	15640	54	0	0
T118	7250	8	0	0
T122	11921	24	0	0
T123	3880	74	0	0
T158	14706	286	0	0