Unified Coverage Report :: Module :: usbdev_reg_top

Module : usbdev_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.44	99.71	98.05			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.44	99.71	98.05			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.44	99.71	98.05			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.26	97.56	93.95	100.00		97.68	87.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.59	96.38	62.63	93.93		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_avoutbuffer	100.00	100.00	100.00			100.00
u_avoutbuffer0_qe	100.00	100.00				100.00
u_avsetupbuffer	100.00	100.00	100.00			100.00
u_avsetupbuffer0_qe	100.00	100.00				100.00
u_chk	100.00	100.00		100.00			100.00
u_configin_0_buffer_0	100.00	100.00	100.00			100.00
u_configin_0_pend_0	94.44	100.00	83.33			100.00
u_configin_0_rdy_0	100.00	100.00	100.00			100.00
u_configin_0_size_0	100.00	100.00	100.00			100.00
u_configin_10_buffer_10	100.00	100.00	100.00			100.00
u_configin_10_pend_10	94.44	100.00	83.33			100.00
u_configin_10_rdy_10	100.00	100.00	100.00			100.00
u_configin_10_size_10	100.00	100.00	100.00			100.00
u_configin_11_buffer_11	100.00	100.00	100.00			100.00
u_configin_11_pend_11	94.44	100.00	83.33			100.00
u_configin_11_rdy_11	100.00	100.00	100.00			100.00
u_configin_11_size_11	100.00	100.00	100.00			100.00
u_configin_1_buffer_1	100.00	100.00	100.00			100.00
u_configin_1_pend_1	94.44	100.00	83.33			100.00
u_configin_1_rdy_1	100.00	100.00	100.00			100.00
u_configin_1_size_1	100.00	100.00	100.00			100.00
u_configin_2_buffer_2	100.00	100.00	100.00			100.00
u_configin_2_pend_2	94.44	100.00	83.33			100.00
u_configin_2_rdy_2	100.00	100.00	100.00			100.00
u_configin_2_size_2	100.00	100.00	100.00			100.00
u_configin_3_buffer_3	100.00	100.00	100.00			100.00
u_configin_3_pend_3	94.44	100.00	83.33			100.00
u_configin_3_rdy_3	100.00	100.00	100.00			100.00
u_configin_3_size_3	100.00	100.00	100.00			100.00
u_configin_4_buffer_4	100.00	100.00	100.00			100.00
u_configin_4_pend_4	94.44	100.00	83.33			100.00
u_configin_4_rdy_4	100.00	100.00	100.00			100.00
u_configin_4_size_4	100.00	100.00	100.00			100.00
u_configin_5_buffer_5	100.00	100.00	100.00			100.00
u_configin_5_pend_5	94.44	100.00	83.33			100.00
u_configin_5_rdy_5	100.00	100.00	100.00			100.00
u_configin_5_size_5	100.00	100.00	100.00			100.00
u_configin_6_buffer_6	100.00	100.00	100.00			100.00
u_configin_6_pend_6	94.44	100.00	83.33			100.00
u_configin_6_rdy_6	100.00	100.00	100.00			100.00
u_configin_6_size_6	100.00	100.00	100.00			100.00
u_configin_7_buffer_7	100.00	100.00	100.00			100.00
u_configin_7_pend_7	94.44	100.00	83.33			100.00
u_configin_7_rdy_7	100.00	100.00	100.00			100.00
u_configin_7_size_7	100.00	100.00	100.00			100.00
u_configin_8_buffer_8	100.00	100.00	100.00			100.00
u_configin_8_pend_8	94.44	100.00	83.33			100.00
u_configin_8_rdy_8	100.00	100.00	100.00			100.00
u_configin_8_size_8	100.00	100.00	100.00			100.00
u_configin_9_buffer_9	100.00	100.00	100.00			100.00
u_configin_9_pend_9	94.44	100.00	83.33			100.00
u_configin_9_rdy_9	100.00	100.00	100.00			100.00
u_configin_9_size_9	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_9	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_9	100.00	100.00	100.00			100.00
u_in_data_toggle_mask	60.00	60.00
u_in_data_toggle_status	100.00	100.00
u_in_iso_iso_0	100.00	100.00	100.00			100.00
u_in_iso_iso_1	100.00	100.00	100.00			100.00
u_in_iso_iso_10	100.00	100.00	100.00			100.00
u_in_iso_iso_11	100.00	100.00	100.00			100.00
u_in_iso_iso_2	100.00	100.00	100.00			100.00
u_in_iso_iso_3	100.00	100.00	100.00			100.00
u_in_iso_iso_4	100.00	100.00	100.00			100.00
u_in_iso_iso_5	100.00	100.00	100.00			100.00
u_in_iso_iso_6	100.00	100.00	100.00			100.00
u_in_iso_iso_7	100.00	100.00	100.00			100.00
u_in_iso_iso_8	100.00	100.00	100.00			100.00
u_in_iso_iso_9	100.00	100.00	100.00			100.00
u_in_sent_sent_0	100.00	100.00	100.00			100.00
u_in_sent_sent_1	100.00	100.00	100.00			100.00
u_in_sent_sent_10	100.00	100.00	100.00			100.00
u_in_sent_sent_11	100.00	100.00	100.00			100.00
u_in_sent_sent_2	100.00	100.00	100.00			100.00
u_in_sent_sent_3	100.00	100.00	100.00			100.00
u_in_sent_sent_4	100.00	100.00	100.00			100.00
u_in_sent_sent_5	100.00	100.00	100.00			100.00
u_in_sent_sent_6	100.00	100.00	100.00			100.00
u_in_sent_sent_7	100.00	100.00	100.00			100.00
u_in_sent_sent_8	100.00	100.00	100.00			100.00
u_in_sent_sent_9	100.00	100.00	100.00			100.00
u_in_stall_endpoint_0	100.00	100.00	100.00			100.00
u_in_stall_endpoint_1	96.30	100.00	88.89			100.00
u_in_stall_endpoint_10	96.30	100.00	88.89			100.00
u_in_stall_endpoint_11	96.30	100.00	88.89			100.00
u_in_stall_endpoint_2	96.30	100.00	88.89			100.00
u_in_stall_endpoint_3	96.30	100.00	88.89			100.00
u_in_stall_endpoint_4	96.30	100.00	88.89			100.00
u_in_stall_endpoint_5	96.30	100.00	88.89			100.00
u_in_stall_endpoint_6	96.30	100.00	88.89			100.00
u_in_stall_endpoint_7	96.30	100.00	88.89			100.00
u_in_stall_endpoint_8	96.30	100.00	88.89			100.00
u_in_stall_endpoint_9	96.30	100.00	88.89			100.00
u_intr_enable_av_out_empty	100.00	100.00	100.00			100.00
u_intr_enable_av_overflow	100.00	100.00	100.00			100.00
u_intr_enable_av_setup_empty	100.00	100.00	100.00			100.00
u_intr_enable_disconnected	100.00	100.00	100.00			100.00
u_intr_enable_frame	100.00	100.00	100.00			100.00
u_intr_enable_host_lost	100.00	100.00	100.00			100.00
u_intr_enable_link_in_err	100.00	100.00	100.00			100.00
u_intr_enable_link_out_err	100.00	100.00	100.00			100.00
u_intr_enable_link_reset	100.00	100.00	100.00			100.00
u_intr_enable_link_resume	100.00	100.00	100.00			100.00
u_intr_enable_link_suspend	100.00	100.00	100.00			100.00
u_intr_enable_pkt_received	100.00	100.00	100.00			100.00
u_intr_enable_pkt_sent	100.00	100.00	100.00			100.00
u_intr_enable_powered	100.00	100.00	100.00			100.00
u_intr_enable_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_full	100.00	100.00	100.00			100.00
u_intr_enable_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_state_av_out_empty	62.59	77.78	50.00			60.00
u_intr_state_av_overflow	91.67	100.00	75.00			100.00
u_intr_state_av_setup_empty	62.59	77.78	50.00			60.00
u_intr_state_disconnected	88.89	100.00	66.67			100.00
u_intr_state_frame	91.67	100.00	75.00			100.00
u_intr_state_host_lost	91.67	100.00	75.00			100.00
u_intr_state_link_in_err	91.67	100.00	75.00			100.00
u_intr_state_link_out_err	91.67	100.00	75.00			100.00
u_intr_state_link_reset	91.67	100.00	75.00			100.00
u_intr_state_link_resume	91.67	100.00	75.00			100.00
u_intr_state_link_suspend	91.67	100.00	75.00			100.00
u_intr_state_pkt_received	62.59	77.78	50.00			60.00
u_intr_state_pkt_sent	62.59	77.78	50.00			60.00
u_intr_state_powered	91.67	100.00	75.00			100.00
u_intr_state_rx_bitstuff_err	91.67	100.00	75.00			100.00
u_intr_state_rx_crc_err	91.67	100.00	75.00			100.00
u_intr_state_rx_full	62.59	77.78	50.00			60.00
u_intr_state_rx_pid_err	91.67	100.00	75.00			100.00
u_intr_test_av_out_empty	100.00	100.00
u_intr_test_av_overflow	100.00	100.00
u_intr_test_av_setup_empty	100.00	100.00
u_intr_test_disconnected	100.00	100.00
u_intr_test_frame	100.00	100.00
u_intr_test_host_lost	100.00	100.00
u_intr_test_link_in_err	100.00	100.00
u_intr_test_link_out_err	100.00	100.00
u_intr_test_link_reset	100.00	100.00
u_intr_test_link_resume	100.00	100.00
u_intr_test_link_suspend	100.00	100.00
u_intr_test_pkt_received	100.00	100.00
u_intr_test_pkt_sent	100.00	100.00
u_intr_test_powered	100.00	100.00
u_intr_test_rx_bitstuff_err	100.00	100.00
u_intr_test_rx_crc_err	100.00	100.00
u_intr_test_rx_full	100.00	100.00
u_intr_test_rx_pid_err	100.00	100.00
u_out_data_toggle_mask	60.00	60.00
u_out_data_toggle_status	100.00	100.00
u_out_iso_iso_0	100.00	100.00	100.00			100.00
u_out_iso_iso_1	100.00	100.00	100.00			100.00
u_out_iso_iso_10	100.00	100.00	100.00			100.00
u_out_iso_iso_11	100.00	100.00	100.00			100.00
u_out_iso_iso_2	100.00	100.00	100.00			100.00
u_out_iso_iso_3	100.00	100.00	100.00			100.00
u_out_iso_iso_4	100.00	100.00	100.00			100.00
u_out_iso_iso_5	100.00	100.00	100.00			100.00
u_out_iso_iso_6	100.00	100.00	100.00			100.00
u_out_iso_iso_7	100.00	100.00	100.00			100.00
u_out_iso_iso_8	100.00	100.00	100.00			100.00
u_out_iso_iso_9	100.00	100.00	100.00			100.00
u_out_stall_endpoint_0	100.00	100.00	100.00			100.00
u_out_stall_endpoint_1	96.30	100.00	88.89			100.00
u_out_stall_endpoint_10	96.30	100.00	88.89			100.00
u_out_stall_endpoint_11	96.30	100.00	88.89			100.00
u_out_stall_endpoint_2	96.30	100.00	88.89			100.00
u_out_stall_endpoint_3	96.30	100.00	88.89			100.00
u_out_stall_endpoint_4	96.30	100.00	88.89			100.00
u_out_stall_endpoint_5	96.30	100.00	88.89			100.00
u_out_stall_endpoint_6	96.30	100.00	88.89			100.00
u_out_stall_endpoint_7	96.30	100.00	88.89			100.00
u_out_stall_endpoint_8	96.30	100.00	88.89			100.00
u_out_stall_endpoint_9	96.30	100.00	88.89			100.00
u_phy_config_eop_single_bit	100.00	100.00	100.00			100.00
u_phy_config_pinflip	100.00	100.00	100.00			100.00
u_phy_config_tx_osc_test_mode	100.00	100.00	100.00			100.00
u_phy_config_tx_use_d_se0	100.00	100.00	100.00			100.00
u_phy_config_usb_ref_disable	100.00	100.00	100.00			100.00
u_phy_config_use_diff_rcvr	100.00	100.00	100.00			100.00
u_phy_pins_drive_d_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_en	100.00	100.00	100.00			100.00
u_phy_pins_drive_oe_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_rx_enable_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_se0_o	100.00	100.00	100.00			100.00
u_phy_pins_sense_pwr_sense	66.67	66.67
u_phy_pins_sense_rx_d_i	66.67	66.67
u_phy_pins_sense_rx_dn_i	66.67	66.67
u_phy_pins_sense_rx_dp_i	66.67	66.67
u_phy_pins_sense_tx_d_o	66.67	66.67
u_phy_pins_sense_tx_dn_o	66.67	66.67
u_phy_pins_sense_tx_dp_o	66.67	66.67
u_phy_pins_sense_tx_oe_o	66.67	66.67
u_phy_pins_sense_tx_se0_o	66.67	66.67
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_rxenable_out_out_0	100.00	100.00	100.00			100.00
u_rxenable_out_out_1	100.00	100.00	100.00			100.00
u_rxenable_out_out_10	100.00	100.00	100.00			100.00
u_rxenable_out_out_11	100.00	100.00	100.00			100.00
u_rxenable_out_out_2	100.00	100.00	100.00			100.00
u_rxenable_out_out_3	100.00	100.00	100.00			100.00
u_rxenable_out_out_4	100.00	100.00	100.00			100.00
u_rxenable_out_out_5	100.00	100.00	100.00			100.00
u_rxenable_out_out_6	100.00	100.00	100.00			100.00
u_rxenable_out_out_7	100.00	100.00	100.00			100.00
u_rxenable_out_out_8	100.00	100.00	100.00			100.00
u_rxenable_out_out_9	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_0	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_1	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_10	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_11	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_2	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_3	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_4	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_5	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_6	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_7	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_8	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_9	100.00	100.00	100.00			100.00
u_rxfifo_buffer	100.00	100.00
u_rxfifo_ep	100.00	100.00
u_rxfifo_setup	100.00	100.00
u_rxfifo_size	100.00	100.00
u_set_nak_out_enable_0	100.00	100.00	100.00			100.00
u_set_nak_out_enable_1	100.00	100.00	100.00			100.00
u_set_nak_out_enable_10	100.00	100.00	100.00			100.00
u_set_nak_out_enable_11	100.00	100.00	100.00			100.00
u_set_nak_out_enable_2	100.00	100.00	100.00			100.00
u_set_nak_out_enable_3	100.00	100.00	100.00			100.00
u_set_nak_out_enable_4	100.00	100.00	100.00			100.00
u_set_nak_out_enable_5	100.00	100.00	100.00			100.00
u_set_nak_out_enable_6	100.00	100.00	100.00			100.00
u_set_nak_out_enable_7	100.00	100.00	100.00			100.00
u_set_nak_out_enable_8	100.00	100.00	100.00			100.00
u_set_nak_out_enable_9	100.00	100.00	100.00			100.00
u_socket	98.24	98.75	98.21			96.00	100.00
u_usbctrl0_qe	100.00	100.00				100.00
u_usbctrl_device_address	96.30	100.00	88.89			100.00
u_usbctrl_enable	100.00	100.00	100.00			100.00
u_usbctrl_resume_link_active	100.00	100.00	100.00			100.00
u_usbstat_av_out_depth	66.67	66.67
u_usbstat_av_out_full	66.67	66.67
u_usbstat_av_setup_depth	66.67	66.67
u_usbstat_av_setup_full	66.67	66.67
u_usbstat_frame	66.67	66.67
u_usbstat_host_lost	66.67	66.67
u_usbstat_link_state	66.67	66.67
u_usbstat_rx_depth	66.67	66.67
u_usbstat_rx_empty	66.67	66.67
u_usbstat_sense	66.67	66.67
u_wake_control_cdc	98.13	96.08	96.43			100.00	100.00
u_wake_control_suspend_req	100.00	100.00
u_wake_control_wake_ack	100.00	100.00
u_wake_events_bus_reset	58.89	66.67	50.00			60.00
u_wake_events_cdc	45.74	76.56	25.00			61.40	20.00
u_wake_events_disconnected	58.89	66.67	50.00			60.00
u_wake_events_module_active	58.89	66.67	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
TOTAL		700	698	99.71
ALWAYS	75	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
ALWAYS	132	3	3	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
ALWAYS	717	1	0	0.00
CONT_ASSIGN	744	1	1	100.00
ALWAYS	758	8	8	100.00
CONT_ASSIGN	1773	1	1	100.00
CONT_ASSIGN	1788	1	1	100.00
CONT_ASSIGN	1804	1	1	100.00
CONT_ASSIGN	1820	1	1	100.00
CONT_ASSIGN	1836	1	1	100.00
CONT_ASSIGN	1852	1	1	100.00
CONT_ASSIGN	1868	1	1	100.00
CONT_ASSIGN	1884	1	1	100.00
CONT_ASSIGN	1900	1	1	100.00
CONT_ASSIGN	1916	1	1	100.00
CONT_ASSIGN	1932	1	1	100.00
CONT_ASSIGN	1948	1	1	100.00
CONT_ASSIGN	1964	1	1	100.00
CONT_ASSIGN	1980	1	1	100.00
CONT_ASSIGN	1996	1	1	100.00
CONT_ASSIGN	2012	1	1	100.00
CONT_ASSIGN	2028	1	1	100.00
CONT_ASSIGN	2044	1	1	100.00
CONT_ASSIGN	2060	1	1	100.00
CONT_ASSIGN	2066	1	1	100.00
CONT_ASSIGN	2080	1	1	100.00
CONT_ASSIGN	2148	1	1	100.00
CONT_ASSIGN	3021	1	1	100.00
CONT_ASSIGN	3061	1	1	100.00
CONT_ASSIGN	7077	1	1	100.00
CONT_ASSIGN	7092	1	1	100.00
CONT_ASSIGN	7108	1	1	100.00
CONT_ASSIGN	7114	1	1	100.00
CONT_ASSIGN	7129	1	1	100.00
CONT_ASSIGN	7145	1	1	100.00
CONT_ASSIGN	7697	1	1	100.00
CONT_ASSIGN	7712	1	1	100.00
CONT_ASSIGN	7728	1	1	100.00
CONT_ASSIGN	7733	1	0	0.00
ALWAYS	7819	39	39	100.00
CONT_ASSIGN	7860	1	1	100.00
ALWAYS	7864	1	1	100.00
CONT_ASSIGN	7906	1	1	100.00
CONT_ASSIGN	7908	1	1	100.00
CONT_ASSIGN	7910	1	1	100.00
CONT_ASSIGN	7912	1	1	100.00
CONT_ASSIGN	7914	1	1	100.00
CONT_ASSIGN	7916	1	1	100.00
CONT_ASSIGN	7918	1	1	100.00
CONT_ASSIGN	7920	1	1	100.00
CONT_ASSIGN	7922	1	1	100.00
CONT_ASSIGN	7924	1	1	100.00
CONT_ASSIGN	7926	1	1	100.00
CONT_ASSIGN	7928	1	1	100.00
CONT_ASSIGN	7930	1	1	100.00
CONT_ASSIGN	7932	1	1	100.00
CONT_ASSIGN	7933	1	1	100.00
CONT_ASSIGN	7935	1	1	100.00
CONT_ASSIGN	7937	1	1	100.00
CONT_ASSIGN	7939	1	1	100.00
CONT_ASSIGN	7941	1	1	100.00
CONT_ASSIGN	7943	1	1	100.00
CONT_ASSIGN	7945	1	1	100.00
CONT_ASSIGN	7947	1	1	100.00
CONT_ASSIGN	7949	1	1	100.00
CONT_ASSIGN	7951	1	1	100.00
CONT_ASSIGN	7953	1	1	100.00
CONT_ASSIGN	7955	1	1	100.00
CONT_ASSIGN	7957	1	1	100.00
CONT_ASSIGN	7959	1	1	100.00
CONT_ASSIGN	7961	1	1	100.00
CONT_ASSIGN	7963	1	1	100.00
CONT_ASSIGN	7965	1	1	100.00
CONT_ASSIGN	7967	1	1	100.00
CONT_ASSIGN	7969	1	1	100.00
CONT_ASSIGN	7970	1	1	100.00
CONT_ASSIGN	7972	1	1	100.00
CONT_ASSIGN	7974	1	1	100.00
CONT_ASSIGN	7976	1	1	100.00
CONT_ASSIGN	7978	1	1	100.00
CONT_ASSIGN	7980	1	1	100.00
CONT_ASSIGN	7982	1	1	100.00
CONT_ASSIGN	7984	1	1	100.00
CONT_ASSIGN	7986	1	1	100.00
CONT_ASSIGN	7988	1	1	100.00
CONT_ASSIGN	7990	1	1	100.00
CONT_ASSIGN	7992	1	1	100.00
CONT_ASSIGN	7994	1	1	100.00
CONT_ASSIGN	7996	1	1	100.00
CONT_ASSIGN	7998	1	1	100.00
CONT_ASSIGN	8000	1	1	100.00
CONT_ASSIGN	8002	1	1	100.00
CONT_ASSIGN	8004	1	1	100.00
CONT_ASSIGN	8006	1	1	100.00
CONT_ASSIGN	8007	1	1	100.00
CONT_ASSIGN	8009	1	1	100.00
CONT_ASSIGN	8010	1	1	100.00
CONT_ASSIGN	8012	1	1	100.00
CONT_ASSIGN	8014	1	1	100.00
CONT_ASSIGN	8016	1	1	100.00
CONT_ASSIGN	8017	1	1	100.00
CONT_ASSIGN	8019	1	1	100.00
CONT_ASSIGN	8021	1	1	100.00
CONT_ASSIGN	8023	1	1	100.00
CONT_ASSIGN	8025	1	1	100.00
CONT_ASSIGN	8027	1	1	100.00
CONT_ASSIGN	8029	1	1	100.00
CONT_ASSIGN	8031	1	1	100.00
CONT_ASSIGN	8033	1	1	100.00
CONT_ASSIGN	8035	1	1	100.00
CONT_ASSIGN	8037	1	1	100.00
CONT_ASSIGN	8039	1	1	100.00
CONT_ASSIGN	8041	1	1	100.00
CONT_ASSIGN	8042	1	1	100.00
CONT_ASSIGN	8044	1	1	100.00
CONT_ASSIGN	8046	1	1	100.00
CONT_ASSIGN	8048	1	1	100.00
CONT_ASSIGN	8050	1	1	100.00
CONT_ASSIGN	8052	1	1	100.00
CONT_ASSIGN	8054	1	1	100.00
CONT_ASSIGN	8056	1	1	100.00
CONT_ASSIGN	8058	1	1	100.00
CONT_ASSIGN	8060	1	1	100.00
CONT_ASSIGN	8062	1	1	100.00
CONT_ASSIGN	8064	1	1	100.00
CONT_ASSIGN	8066	1	1	100.00
CONT_ASSIGN	8067	1	1	100.00
CONT_ASSIGN	8068	1	1	100.00
CONT_ASSIGN	8070	1	1	100.00
CONT_ASSIGN	8071	1	1	100.00
CONT_ASSIGN	8073	1	1	100.00
CONT_ASSIGN	8074	1	1	100.00
CONT_ASSIGN	8075	1	1	100.00
CONT_ASSIGN	8077	1	1	100.00
CONT_ASSIGN	8079	1	1	100.00
CONT_ASSIGN	8081	1	1	100.00
CONT_ASSIGN	8083	1	1	100.00
CONT_ASSIGN	8085	1	1	100.00
CONT_ASSIGN	8087	1	1	100.00
CONT_ASSIGN	8089	1	1	100.00
CONT_ASSIGN	8091	1	1	100.00
CONT_ASSIGN	8093	1	1	100.00
CONT_ASSIGN	8095	1	1	100.00
CONT_ASSIGN	8097	1	1	100.00
CONT_ASSIGN	8099	1	1	100.00
CONT_ASSIGN	8100	1	1	100.00
CONT_ASSIGN	8102	1	1	100.00
CONT_ASSIGN	8104	1	1	100.00
CONT_ASSIGN	8106	1	1	100.00
CONT_ASSIGN	8108	1	1	100.00
CONT_ASSIGN	8110	1	1	100.00
CONT_ASSIGN	8112	1	1	100.00
CONT_ASSIGN	8114	1	1	100.00
CONT_ASSIGN	8116	1	1	100.00
CONT_ASSIGN	8118	1	1	100.00
CONT_ASSIGN	8120	1	1	100.00
CONT_ASSIGN	8122	1	1	100.00
CONT_ASSIGN	8124	1	1	100.00
CONT_ASSIGN	8125	1	1	100.00
CONT_ASSIGN	8127	1	1	100.00
CONT_ASSIGN	8129	1	1	100.00
CONT_ASSIGN	8131	1	1	100.00
CONT_ASSIGN	8133	1	1	100.00
CONT_ASSIGN	8135	1	1	100.00
CONT_ASSIGN	8137	1	1	100.00
CONT_ASSIGN	8139	1	1	100.00
CONT_ASSIGN	8141	1	1	100.00
CONT_ASSIGN	8143	1	1	100.00
CONT_ASSIGN	8145	1	1	100.00
CONT_ASSIGN	8147	1	1	100.00
CONT_ASSIGN	8149	1	1	100.00
CONT_ASSIGN	8150	1	1	100.00
CONT_ASSIGN	8152	1	1	100.00
CONT_ASSIGN	8154	1	1	100.00
CONT_ASSIGN	8156	1	1	100.00
CONT_ASSIGN	8158	1	1	100.00
CONT_ASSIGN	8160	1	1	100.00
CONT_ASSIGN	8162	1	1	100.00
CONT_ASSIGN	8164	1	1	100.00
CONT_ASSIGN	8166	1	1	100.00
CONT_ASSIGN	8168	1	1	100.00
CONT_ASSIGN	8170	1	1	100.00
CONT_ASSIGN	8172	1	1	100.00
CONT_ASSIGN	8174	1	1	100.00
CONT_ASSIGN	8175	1	1	100.00
CONT_ASSIGN	8177	1	1	100.00
CONT_ASSIGN	8179	1	1	100.00
CONT_ASSIGN	8181	1	1	100.00
CONT_ASSIGN	8183	1	1	100.00
CONT_ASSIGN	8185	1	1	100.00
CONT_ASSIGN	8187	1	1	100.00
CONT_ASSIGN	8189	1	1	100.00
CONT_ASSIGN	8191	1	1	100.00
CONT_ASSIGN	8193	1	1	100.00
CONT_ASSIGN	8195	1	1	100.00
CONT_ASSIGN	8197	1	1	100.00
CONT_ASSIGN	8199	1	1	100.00
CONT_ASSIGN	8200	1	1	100.00
CONT_ASSIGN	8202	1	1	100.00
CONT_ASSIGN	8204	1	1	100.00
CONT_ASSIGN	8206	1	1	100.00
CONT_ASSIGN	8208	1	1	100.00
CONT_ASSIGN	8210	1	1	100.00
CONT_ASSIGN	8212	1	1	100.00
CONT_ASSIGN	8214	1	1	100.00
CONT_ASSIGN	8216	1	1	100.00
CONT_ASSIGN	8218	1	1	100.00
CONT_ASSIGN	8220	1	1	100.00
CONT_ASSIGN	8222	1	1	100.00
CONT_ASSIGN	8224	1	1	100.00
CONT_ASSIGN	8225	1	1	100.00
CONT_ASSIGN	8227	1	1	100.00
CONT_ASSIGN	8229	1	1	100.00
CONT_ASSIGN	8231	1	1	100.00
CONT_ASSIGN	8233	1	1	100.00
CONT_ASSIGN	8234	1	1	100.00
CONT_ASSIGN	8236	1	1	100.00
CONT_ASSIGN	8238	1	1	100.00
CONT_ASSIGN	8240	1	1	100.00
CONT_ASSIGN	8242	1	1	100.00
CONT_ASSIGN	8243	1	1	100.00
CONT_ASSIGN	8245	1	1	100.00
CONT_ASSIGN	8247	1	1	100.00
CONT_ASSIGN	8249	1	1	100.00
CONT_ASSIGN	8251	1	1	100.00
CONT_ASSIGN	8252	1	1	100.00
CONT_ASSIGN	8254	1	1	100.00
CONT_ASSIGN	8256	1	1	100.00
CONT_ASSIGN	8258	1	1	100.00
CONT_ASSIGN	8260	1	1	100.00
CONT_ASSIGN	8261	1	1	100.00
CONT_ASSIGN	8263	1	1	100.00
CONT_ASSIGN	8265	1	1	100.00
CONT_ASSIGN	8267	1	1	100.00
CONT_ASSIGN	8269	1	1	100.00
CONT_ASSIGN	8270	1	1	100.00
CONT_ASSIGN	8272	1	1	100.00
CONT_ASSIGN	8274	1	1	100.00
CONT_ASSIGN	8276	1	1	100.00
CONT_ASSIGN	8278	1	1	100.00
CONT_ASSIGN	8279	1	1	100.00
CONT_ASSIGN	8281	1	1	100.00
CONT_ASSIGN	8283	1	1	100.00
CONT_ASSIGN	8285	1	1	100.00
CONT_ASSIGN	8287	1	1	100.00
CONT_ASSIGN	8288	1	1	100.00
CONT_ASSIGN	8290	1	1	100.00
CONT_ASSIGN	8292	1	1	100.00
CONT_ASSIGN	8294	1	1	100.00
CONT_ASSIGN	8296	1	1	100.00
CONT_ASSIGN	8297	1	1	100.00
CONT_ASSIGN	8299	1	1	100.00
CONT_ASSIGN	8301	1	1	100.00
CONT_ASSIGN	8303	1	1	100.00
CONT_ASSIGN	8305	1	1	100.00
CONT_ASSIGN	8306	1	1	100.00
CONT_ASSIGN	8308	1	1	100.00
CONT_ASSIGN	8310	1	1	100.00
CONT_ASSIGN	8312	1	1	100.00
CONT_ASSIGN	8314	1	1	100.00
CONT_ASSIGN	8315	1	1	100.00
CONT_ASSIGN	8317	1	1	100.00
CONT_ASSIGN	8319	1	1	100.00
CONT_ASSIGN	8321	1	1	100.00
CONT_ASSIGN	8323	1	1	100.00
CONT_ASSIGN	8324	1	1	100.00
CONT_ASSIGN	8326	1	1	100.00
CONT_ASSIGN	8328	1	1	100.00
CONT_ASSIGN	8330	1	1	100.00
CONT_ASSIGN	8332	1	1	100.00
CONT_ASSIGN	8333	1	1	100.00
CONT_ASSIGN	8335	1	1	100.00
CONT_ASSIGN	8337	1	1	100.00
CONT_ASSIGN	8339	1	1	100.00
CONT_ASSIGN	8341	1	1	100.00
CONT_ASSIGN	8343	1	1	100.00
CONT_ASSIGN	8345	1	1	100.00
CONT_ASSIGN	8347	1	1	100.00
CONT_ASSIGN	8349	1	1	100.00
CONT_ASSIGN	8351	1	1	100.00
CONT_ASSIGN	8353	1	1	100.00
CONT_ASSIGN	8355	1	1	100.00
CONT_ASSIGN	8357	1	1	100.00
CONT_ASSIGN	8358	1	1	100.00
CONT_ASSIGN	8360	1	1	100.00
CONT_ASSIGN	8362	1	1	100.00
CONT_ASSIGN	8364	1	1	100.00
CONT_ASSIGN	8366	1	1	100.00
CONT_ASSIGN	8368	1	1	100.00
CONT_ASSIGN	8370	1	1	100.00
CONT_ASSIGN	8372	1	1	100.00
CONT_ASSIGN	8374	1	1	100.00
CONT_ASSIGN	8376	1	1	100.00
CONT_ASSIGN	8378	1	1	100.00
CONT_ASSIGN	8380	1	1	100.00
CONT_ASSIGN	8382	1	1	100.00
CONT_ASSIGN	8383	1	1	100.00
CONT_ASSIGN	8384	1	1	100.00
CONT_ASSIGN	8386	1	1	100.00
CONT_ASSIGN	8388	1	1	100.00
CONT_ASSIGN	8389	1	1	100.00
CONT_ASSIGN	8390	1	1	100.00
CONT_ASSIGN	8392	1	1	100.00
CONT_ASSIGN	8394	1	1	100.00
CONT_ASSIGN	8395	1	1	100.00
CONT_ASSIGN	8396	1	1	100.00
CONT_ASSIGN	8398	1	1	100.00
CONT_ASSIGN	8400	1	1	100.00
CONT_ASSIGN	8402	1	1	100.00
CONT_ASSIGN	8404	1	1	100.00
CONT_ASSIGN	8406	1	1	100.00
CONT_ASSIGN	8408	1	1	100.00
CONT_ASSIGN	8410	1	1	100.00
CONT_ASSIGN	8412	1	1	100.00
CONT_ASSIGN	8414	1	1	100.00
CONT_ASSIGN	8415	1	1	100.00
CONT_ASSIGN	8417	1	1	100.00
CONT_ASSIGN	8419	1	1	100.00
CONT_ASSIGN	8421	1	1	100.00
CONT_ASSIGN	8423	1	1	100.00
CONT_ASSIGN	8425	1	1	100.00
CONT_ASSIGN	8427	1	1	100.00
CONT_ASSIGN	8428	1	1	100.00
ALWAYS	8434	39	39	100.00
ALWAYS	8477	274	274	100.00
CONT_ASSIGN	8875	1	1	100.00
ALWAYS	8877	4	4	100.00
CONT_ASSIGN	8898	1	1	100.00
CONT_ASSIGN	8899	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
76	1	1
77	1	1
78	1	1
			MISSING_ELSE
84	1	1
102	1	1
103	1	1
105	1	1
106	1	1
132	1	1
138	1	1
139	1	1
			MISSING_ELSE
169	1	1
170	1	1
717	0	1
744	1	1
758	1	1
759	1	1
760	1	1
761	1	1
762	1	1
763	1	1
764	1	1
765	1	1
1773	1	1
1788	1	1
1804	1	1
1820	1	1
1836	1	1
1852	1	1
1868	1	1
1884	1	1
1900	1	1
1916	1	1
1932	1	1
1948	1	1
1964	1	1
1980	1	1
1996	1	1
2012	1	1
2028	1	1
2044	1	1
2060	1	1
2066	1	1
2080	1	1
2148	1	1
3021	1	1
3061	1	1
7077	1	1
7092	1	1
7108	1	1
7114	1	1
7129	1	1
7145	1	1
7697	1	1
7712	1	1
7728	1	1
7733	0	1
7819	1	1
7820	1	1
7821	1	1
7822	1	1
7823	1	1
7824	1	1
7825	1	1
7826	1	1
7827	1	1
7828	1	1
7829	1	1
7830	1	1
7831	1	1
7832	1	1
7833	1	1
7834	1	1
7835	1	1
7836	1	1
7837	1	1
7838	1	1
7839	1	1
7840	1	1
7841	1	1
7842	1	1
7843	1	1
7844	1	1
7845	1	1
7846	1	1
7847	1	1
7848	1	1
7849	1	1
7850	1	1
7851	1	1
7852	1	1
7853	1	1
7854	1	1
7855	1	1
7856	1	1
7857	1	1
7860	1	1
7864	1	1
7906	1	1
7908	1	1
7910	1	1
7912	1	1
7914	1	1
7916	1	1
7918	1	1
7920	1	1
7922	1	1
7924	1	1
7926	1	1
7928	1	1
7930	1	1
7932	1	1
7933	1	1
7935	1	1
7937	1	1
7939	1	1
7941	1	1
7943	1	1
7945	1	1
7947	1	1
7949	1	1
7951	1	1
7953	1	1
7955	1	1
7957	1	1
7959	1	1
7961	1	1
7963	1	1
7965	1	1
7967	1	1
7969	1	1
7970	1	1
7972	1	1
7974	1	1
7976	1	1
7978	1	1
7980	1	1
7982	1	1
7984	1	1
7986	1	1
7988	1	1
7990	1	1
7992	1	1
7994	1	1
7996	1	1
7998	1	1
8000	1	1
8002	1	1
8004	1	1
8006	1	1
8007	1	1
8009	1	1
8010	1	1
8012	1	1
8014	1	1
8016	1	1
8017	1	1
8019	1	1
8021	1	1
8023	1	1
8025	1	1
8027	1	1
8029	1	1
8031	1	1
8033	1	1
8035	1	1
8037	1	1
8039	1	1
8041	1	1
8042	1	1
8044	1	1
8046	1	1
8048	1	1
8050	1	1
8052	1	1
8054	1	1
8056	1	1
8058	1	1
8060	1	1
8062	1	1
8064	1	1
8066	1	1
8067	1	1
8068	1	1
8070	1	1
8071	1	1
8073	1	1
8074	1	1
8075	1	1
8077	1	1
8079	1	1
8081	1	1
8083	1	1
8085	1	1
8087	1	1
8089	1	1
8091	1	1
8093	1	1
8095	1	1
8097	1	1
8099	1	1
8100	1	1
8102	1	1
8104	1	1
8106	1	1
8108	1	1
8110	1	1
8112	1	1
8114	1	1
8116	1	1
8118	1	1
8120	1	1
8122	1	1
8124	1	1
8125	1	1
8127	1	1
8129	1	1
8131	1	1
8133	1	1
8135	1	1
8137	1	1
8139	1	1
8141	1	1
8143	1	1
8145	1	1
8147	1	1
8149	1	1
8150	1	1
8152	1	1
8154	1	1
8156	1	1
8158	1	1
8160	1	1
8162	1	1
8164	1	1
8166	1	1
8168	1	1
8170	1	1
8172	1	1
8174	1	1
8175	1	1
8177	1	1
8179	1	1
8181	1	1
8183	1	1
8185	1	1
8187	1	1
8189	1	1
8191	1	1
8193	1	1
8195	1	1
8197	1	1
8199	1	1
8200	1	1
8202	1	1
8204	1	1
8206	1	1
8208	1	1
8210	1	1
8212	1	1
8214	1	1
8216	1	1
8218	1	1
8220	1	1
8222	1	1
8224	1	1
8225	1	1
8227	1	1
8229	1	1
8231	1	1
8233	1	1
8234	1	1
8236	1	1
8238	1	1
8240	1	1
8242	1	1
8243	1	1
8245	1	1
8247	1	1
8249	1	1
8251	1	1
8252	1	1
8254	1	1
8256	1	1
8258	1	1
8260	1	1
8261	1	1
8263	1	1
8265	1	1
8267	1	1
8269	1	1
8270	1	1
8272	1	1
8274	1	1
8276	1	1
8278	1	1
8279	1	1
8281	1	1
8283	1	1
8285	1	1
8287	1	1
8288	1	1
8290	1	1
8292	1	1
8294	1	1
8296	1	1
8297	1	1
8299	1	1
8301	1	1
8303	1	1
8305	1	1
8306	1	1
8308	1	1
8310	1	1
8312	1	1
8314	1	1
8315	1	1
8317	1	1
8319	1	1
8321	1	1
8323	1	1
8324	1	1
8326	1	1
8328	1	1
8330	1	1
8332	1	1
8333	1	1
8335	1	1
8337	1	1
8339	1	1
8341	1	1
8343	1	1
8345	1	1
8347	1	1
8349	1	1
8351	1	1
8353	1	1
8355	1	1
8357	1	1
8358	1	1
8360	1	1
8362	1	1
8364	1	1
8366	1	1
8368	1	1
8370	1	1
8372	1	1
8374	1	1
8376	1	1
8378	1	1
8380	1	1
8382	1	1
8383	1	1
8384	1	1
8386	1	1
8388	1	1
8389	1	1
8390	1	1
8392	1	1
8394	1	1
8395	1	1
8396	1	1
8398	1	1
8400	1	1
8402	1	1
8404	1	1
8406	1	1
8408	1	1
8410	1	1
8412	1	1
8414	1	1
8415	1	1
8417	1	1
8419	1	1
8421	1	1
8423	1	1
8425	1	1
8427	1	1
8428	1	1
8434	1	1
8435	1	1
8436	1	1
8437	1	1
8438	1	1
8439	1	1
8440	1	1
8441	1	1
8442	1	1
8443	1	1
8444	1	1
8445	1	1
8446	1	1
8447	1	1
8448	1	1
8449	1	1
8450	1	1
8451	1	1
8452	1	1
8453	1	1
8454	1	1
8455	1	1
8456	1	1
8457	1	1
8458	1	1
8459	1	1
8460	1	1
8461	1	1
8462	1	1
8463	1	1
8464	1	1
8465	1	1
8466	1	1
8467	1	1
8468	1	1
8469	1	1
8470	1	1
8471	1	1
8472	1	1
8477	1	1
8478	1	1
8480	1	1
8481	1	1
8482	1	1
8483	1	1
8484	1	1
8485	1	1
8486	1	1
8487	1	1
8488	1	1
8489	1	1
8490	1	1
8491	1	1
8492	1	1
8493	1	1
8494	1	1
8495	1	1
8496	1	1
8497	1	1
8501	1	1
8502	1	1
8503	1	1
8504	1	1
8505	1	1
8506	1	1
8507	1	1
8508	1	1
8509	1	1
8510	1	1
8511	1	1
8512	1	1
8513	1	1
8514	1	1
8515	1	1
8516	1	1
8517	1	1
8518	1	1
8522	1	1
8523	1	1
8524	1	1
8525	1	1
8526	1	1
8527	1	1
8528	1	1
8529	1	1
8530	1	1
8531	1	1
8532	1	1
8533	1	1
8534	1	1
8535	1	1
8536	1	1
8537	1	1
8538	1	1
8539	1	1
8543	1	1
8547	1	1
8548	1	1
8549	1	1
8553	1	1
8554	1	1
8555	1	1
8556	1	1
8557	1	1
8558	1	1
8559	1	1
8560	1	1
8561	1	1
8562	1	1
8563	1	1
8564	1	1
8568	1	1
8569	1	1
8570	1	1
8571	1	1
8572	1	1
8573	1	1
8574	1	1
8575	1	1
8576	1	1
8577	1	1
8578	1	1
8579	1	1
8583	1	1
8584	1	1
8585	1	1
8586	1	1
8587	1	1
8588	1	1
8589	1	1
8590	1	1
8591	1	1
8592	1	1
8596	1	1
8600	1	1
8604	1	1
8605	1	1
8606	1	1
8607	1	1
8611	1	1
8612	1	1
8613	1	1
8614	1	1
8615	1	1
8616	1	1
8617	1	1
8618	1	1
8619	1	1
8620	1	1
8621	1	1
8622	1	1
8626	1	1
8627	1	1
8628	1	1
8629	1	1
8630	1	1
8631	1	1
8632	1	1
8633	1	1
8634	1	1
8635	1	1
8636	1	1
8637	1	1
8641	1	1
8642	1	1
8643	1	1
8644	1	1
8645	1	1
8646	1	1
8647	1	1
8648	1	1
8649	1	1
8650	1	1
8651	1	1
8652	1	1
8656	1	1
8657	1	1
8658	1	1
8659	1	1
8660	1	1
8661	1	1
8662	1	1
8663	1	1
8664	1	1
8665	1	1
8666	1	1
8667	1	1
8671	1	1
8672	1	1
8673	1	1
8674	1	1
8675	1	1
8676	1	1
8677	1	1
8678	1	1
8679	1	1
8680	1	1
8681	1	1
8682	1	1
8686	1	1
8687	1	1
8688	1	1
8689	1	1
8690	1	1
8691	1	1
8692	1	1
8693	1	1
8694	1	1
8695	1	1
8696	1	1
8697	1	1
8701	1	1
8702	1	1
8703	1	1
8704	1	1
8708	1	1
8709	1	1
8710	1	1
8711	1	1
8715	1	1
8716	1	1
8717	1	1
8718	1	1
8722	1	1
8723	1	1
8724	1	1
8725	1	1
8729	1	1
8730	1	1
8731	1	1
8732	1	1
8736	1	1
8737	1	1
8738	1	1
8739	1	1
8743	1	1
8744	1	1
8745	1	1
8746	1	1
8750	1	1
8751	1	1
8752	1	1
8753	1	1
8757	1	1
8758	1	1
8759	1	1
8760	1	1
8764	1	1
8765	1	1
8766	1	1
8767	1	1
8771	1	1
8772	1	1
8773	1	1
8774	1	1
8778	1	1
8779	1	1
8780	1	1
8781	1	1
8785	1	1
8786	1	1
8787	1	1
8788	1	1
8789	1	1
8790	1	1
8791	1	1
8792	1	1
8793	1	1
8794	1	1
8795	1	1
8796	1	1
8800	1	1
8801	1	1
8802	1	1
8803	1	1
8804	1	1
8805	1	1
8806	1	1
8807	1	1
8808	1	1
8809	1	1
8810	1	1
8811	1	1
8815	1	1
8816	1	1
8820	1	1
8821	1	1
8825	1	1
8826	1	1
8827	1	1
8828	1	1
8829	1	1
8830	1	1
8831	1	1
8832	1	1
8833	1	1
8837	1	1
8838	1	1
8839	1	1
8840	1	1
8841	1	1
8842	1	1
8843	1	1
8844	1	1
8845	1	1
8849	1	1
8850	1	1
8851	1	1
8852	1	1
8853	1	1
8854	1	1
8858	1	1
8861	1	1
8875	1	1
8877	1	1
8878	1	1
8880	1	1
8883	1	1
8898	1	1
8899	1	1

---

Cond Coverage for Module : usbdev_reg_top

	Total	Covered	Percent
Conditions	411	403	98.05
Logical	411	403	98.05
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T35,T36,T57
1	1	Covered	T1,T2,T3

 LINE       77
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T33,T37,T38
1	0	Covered	T35,T36,T57

 LINE       84
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T33,T37,T38
0	1	0	Covered	T35,T36,T57
1	0	0	Covered	T33,T37,T38

 LINE       132
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T9

 LINE       170
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T35,T36,T57
0	1	0	Covered	T34,T114,T115
1	0	0	Covered	T115,T116,T117

 LINE       7820
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_STATE_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7821
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_ENABLE_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       7822
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_TEST_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T121,T34

 LINE       7823
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T141,T34,T42

 LINE       7824
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBCTRL_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7825
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_OUT_ENABLE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7826
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_IN_ENABLE_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       7827
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBSTAT_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T34,T42

 LINE       7828
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_AVOUTBUFFER_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       7829
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_AVSETUPBUFFER_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T11

 LINE       7830
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXFIFO_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       7831
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_SETUP_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T7

 LINE       7832
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_OUT_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       7833
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_SET_NAK_OUT_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T20,T21

 LINE       7834
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_SENT_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T6

 LINE       7835
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_STALL_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T121,T34,T42

 LINE       7836
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_STALL_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T76,T121,T34

 LINE       7837
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_0_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T60,T90

 LINE       7838
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_1_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T91,T107,T92

 LINE       7839
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_2_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T12,T94

 LINE       7840
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_3_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T96,T142,T143

 LINE       7841
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_4_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T99,T100

 LINE       7842
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_5_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T10,T101

 LINE       7843
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_6_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T22,T102

 LINE       7844
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_7_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T103,T104

 LINE       7845
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_8_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T12,T105

 LINE       7846
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_9_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T106,T107,T108

 LINE       7847
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_10_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T109,T110,T111

 LINE       7848
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_11_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T112,T113

 LINE       7849
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_ISO_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T100,T34,T42

 LINE       7850
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_ISO_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T42,T43

 LINE       7851
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_DATA_TOGGLE_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T42,T43

 LINE       7852
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_DATA_TOGGLE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T144,T34,T42

 LINE       7853
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_SENSE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T144,T34,T43

 LINE       7854
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_DRIVE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T42,T43

 LINE       7855
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_CONFIG_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T121,T34,T42

 LINE       7856
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_CONTROL_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T97,T121

 LINE       7857
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_EVENTS_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T145,T34,T42

 LINE       7860
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7860
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       7864
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | (addr_hit[37] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T34,T114,T115

 LINE       7864
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b0111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b0111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b0011 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
38 (addr_hit[37] & ((|(4'...	Covered	T145,T34,T35
37 (addr_hit[36] & ((|(4'...	Covered	T121,T34,T35
36 (addr_hit[35] & ((|(4'...	Covered	T34,T35,T36
35 (addr_hit[34] & ((|(4'...	Covered	T34,T35,T36
34 (addr_hit[33] & ((|(4'...	Covered	T144,T34,T114
33 (addr_hit[32] & ((|(4'...	Covered	T144,T35,T57
32 (addr_hit[31] & ((|(4'...	Covered	T35,T57,T114
31 (addr_hit[30] & ((|(4'...	Covered	T34,T35,T36
30 (addr_hit[29] & ((|(4'...	Covered	T34,T35,T36
29 (addr_hit[28] & ((|(4'...	Covered	T121,T34,T35
28 (addr_hit[27] & ((|(4'...	Covered	T34,T35,T36
27 (addr_hit[26] & ((|(4'...	Covered	T121,T34,T35
26 (addr_hit[25] & ((|(4'...	Covered	T28,T146,T34
25 (addr_hit[24] & ((|(4'...	Covered	T34,T35,T36
24 (addr_hit[23] & ((|(4'...	Covered	T147,T121,T34
23 (addr_hit[22] & ((|(4'...	Covered	T34,T35,T36
22 (addr_hit[21] & ((|(4'...	Covered	T143,T34,T35
21 (addr_hit[20] & ((|(4'...	Covered	T142,T143,T148
20 (addr_hit[19] & ((|(4'...	Covered	T12,T73,T121
19 (addr_hit[18] & ((|(4'...	Covered	T107,T149,T34
18 (addr_hit[17] & ((|(4'...	Covered	T121,T35,T36
17 (addr_hit[16] & ((|(4'...	Covered	T121,T34,T35
16 (addr_hit[15] & ((|(4'...	Covered	T121,T34,T35
15 (addr_hit[14] & ((|(4'...	Covered	T4,T8,T10
14 (addr_hit[13] & ((|(4'...	Covered	T14,T150,T35
13 (addr_hit[12] & ((|(4'...	Covered	T20,T76,T77
12 (addr_hit[11] & ((|(4'...	Covered	T74,T34,T35
11 (addr_hit[10] & ((|(4'...	Covered	T1,T4,T6
10 (addr_hit[9] & ((|(4'b...	Covered	T62,T35,T114
9 (addr_hit[8] & ((|(4'b...	Covered	T14,T114,T115
8 (addr_hit[7] & ((|(4'b...	Covered	T4,T35,T57
7 (addr_hit[6] & ((|(4'b...	Covered	T151,T34,T35
6 (addr_hit[5] & ((|(4'b...	Covered	T27,T151,T34
5 (addr_hit[4] & ((|(4'b...	Covered	T76,T97,T121
4 (addr_hit[3] & ((|(4'b...	Covered	T34,T35,T36
3 (addr_hit[2] & ((|(4'b...	Covered	T13,T121,T35
2 (addr_hit[1] & ((|(4'b...	Covered	T152,T34,T35
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T4

 LINE       7864
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       7864
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T152,T34,T35

 LINE       7864
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T42,T43
1	1	Covered	T13,T121,T35

 LINE       7864
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T141,T34,T42
1	1	Covered	T34,T35,T36

 LINE       7864
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T76,T97,T121

 LINE       7864
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T151,T34

 LINE       7864
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T151,T34,T35

 LINE       7864
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T42,T43
1	1	Covered	T4,T35,T57

 LINE       7864
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T14,T114,T115

 LINE       7864
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T5,T7,T11
1	1	Covered	T62,T35,T114

 LINE       7864
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T7
1	1	Covered	T1,T4,T6

 LINE       7864
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T7
1	1	Covered	T74,T34,T35

 LINE       7864
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T20,T76,T77

 LINE       7864
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T20,T21
1	1	Covered	T14,T150,T35

 LINE       7864
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T6
1	1	Covered	T4,T8,T10

 LINE       7864
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T42,T43
1	1	Covered	T121,T34,T35

 LINE       7864
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T76,T121,T34
1	1	Covered	T121,T34,T35

 LINE       7864
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T60,T90
1	1	Covered	T121,T35,T36

 LINE       7864
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T91,T92,T93
1	1	Covered	T107,T149,T34

 LINE       7864
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T94,T95
1	1	Covered	T12,T73,T121

 LINE       7864
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T96,T97,T98
1	1	Covered	T142,T143,T148

 LINE       7864
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T99,T100
1	1	Covered	T143,T34,T35

 LINE       7864
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T10,T101
1	1	Covered	T34,T35,T36

 LINE       7864
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T22,T102
1	1	Covered	T147,T121,T34

 LINE       7864
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T103,T104
1	1	Covered	T34,T35,T36

 LINE       7864
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T12,T105
1	1	Covered	T28,T146,T34

 LINE       7864
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T106,T107,T108
1	1	Covered	T121,T34,T35

 LINE       7864
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T109,T110,T111
1	1	Covered	T34,T35,T36

 LINE       7864
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T112,T113
1	1	Covered	T121,T34,T35

 LINE       7864
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T100,T34,T42
1	1	Covered	T34,T35,T36

 LINE       7864
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T42,T43
1	1	Covered	T34,T35,T36

 LINE       7864
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T42,T43
1	1	Covered	T35,T57,T114

 LINE       7864
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T42,T43
1	1	Covered	T144,T35,T57

 LINE       7864
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T43,T35
1	1	Covered	T144,T34,T114

 LINE       7864
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T42,T43
1	1	Covered	T34,T35,T36

 LINE       7864
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T121,T34,T42
1	1	Covered	T34,T35,T36

 LINE       7864
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T97,T34
1	1	Covered	T121,T34,T35

 LINE       7864
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T42,T43
1	1	Covered	T145,T34,T35

 LINE       7906
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T116,T117,T120
1	1	1	Not Covered

 LINE       7933
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T116,T117,T153
1	1	1	Covered	T1,T2,T4

 LINE       7970
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T149,T121
1	1	0	Covered	T116,T120,T153
1	1	1	Covered	T46,T39,T40

 LINE       8007
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T141,T34,T42
1	1	0	Covered	T116,T117,T154
1	1	1	Covered	T42,T43,T35

 LINE       8010
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T1,T2,T3

 LINE       8017
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T1,T2,T3

 LINE       8042
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T6
1	1	0	Covered	T116,T117,T118
1	1	1	Covered	T1,T4,T6

 LINE       8067
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T34,T42
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       8068
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T1,T3,T4

 LINE       8071
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T7,T11
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T5,T7,T11

 LINE       8074
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       8075
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T5,T7
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T2,T5,T7

 LINE       8100
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T1,T3,T4

 LINE       8125
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T14,T20,T21
1	1	0	Covered	T116,T117,T153
1	1	1	Covered	T14,T20,T21

 LINE       8150
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T4,T6
1	1	0	Covered	T116,T117,T155
1	1	1	Covered	T1,T4,T6

 LINE       8175
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T108,T147,T121
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T34,T42,T43

 LINE       8200
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T76,T121,T34
1	1	0	Covered	T116,T120,T155
1	1	1	Covered	T34,T42,T43

 LINE       8225
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T60,T90
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T1,T60,T90

 LINE       8234
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T91,T107,T92
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T91,T92,T93

 LINE       8243
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T12,T94
1	1	0	Covered	T34,T116,T117
1	1	1	Covered	T6,T94,T95

 LINE       8252
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T96,T142,T156
1	1	0	Covered	T117,T120,T157
1	1	1	Covered	T96,T97,T98

 LINE       8261
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T99,T100
1	1	0	Covered	T114,T120,T153
1	1	1	Covered	T17,T99,T100

 LINE       8270
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T10,T101
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T4,T10,T101

 LINE       8279
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T13,T22,T102
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T13,T22,T102

 LINE       8288
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T16,T103,T104
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T16,T103,T104

 LINE       8297
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T12,T105
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T8,T12,T105

 LINE       8306
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T106,T107,T108
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T106,T107,T108

 LINE       8315
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T109,T110,T111
1	1	0	Covered	T115,T117,T120
1	1	1	Covered	T109,T110,T111

 LINE       8324
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T112,T113
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T15,T112,T113

 LINE       8333
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T100,T34,T42
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T34,T42,T43

 LINE       8358
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T42,T43
1	1	0	Covered	T116,T117,T155
1	1	1	Covered	T34,T42,T43

 LINE       8383
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T42,T43
1	1	0	Not Covered
1	1	1	Covered	T34,T42,T43

 LINE       8384
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T42,T43
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T46,T39,T40

 LINE       8389
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T144,T34,T42
1	1	0	Not Covered
1	1	1	Covered	T34,T42,T43

 LINE       8390
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T144,T34,T42
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T46,T39,T40

 LINE       8395
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T144,T34,T43
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       8396
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T42,T43
1	1	0	Covered	T114,T116,T117
1	1	1	Covered	T34,T42,T43

 LINE       8415
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T121,T34,T42
1	1	0	Covered	T116,T117,T120
1	1	1	Covered	T42,T43,T35

 LINE       8428
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T97,T121
1	1	0	Covered	T120,T155,T153
1	1	1	Covered	T34,T42,T43

 LINE       8875
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T34,T42,T43

---

Branch Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
Branches		51	51	100.00
TERNARY	7860	2	2	100.00
IF	75	3	3	100.00
TERNARY	132	2	2	100.00
IF	138	2	2	100.00
CASE	8478	39	39	100.00
CASE	8878	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	7860	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	77	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T33,T37,T38
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	132	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T57
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	8478	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T4
addr_hit[2]	Covered	T1,T2,T5
addr_hit[3]	Covered	T1,T2,T5
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T4
addr_hit[7]	Covered	T1,T2,T4
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T5
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T5
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T5
addr_hit[14]	Covered	T1,T2,T4
addr_hit[15]	Covered	T1,T2,T5
addr_hit[16]	Covered	T1,T2,T5
addr_hit[17]	Covered	T1,T2,T5
addr_hit[18]	Covered	T1,T2,T5
addr_hit[19]	Covered	T1,T2,T5
addr_hit[20]	Covered	T1,T2,T5
addr_hit[21]	Covered	T1,T2,T5
addr_hit[22]	Covered	T1,T2,T4
addr_hit[23]	Covered	T1,T2,T5
addr_hit[24]	Covered	T1,T2,T5
addr_hit[25]	Covered	T1,T2,T5
addr_hit[26]	Covered	T1,T2,T5
addr_hit[27]	Covered	T1,T2,T5
addr_hit[28]	Covered	T1,T2,T5
addr_hit[29]	Covered	T1,T2,T5
addr_hit[30]	Covered	T1,T2,T5
addr_hit[31]	Covered	T1,T2,T5
addr_hit[32]	Covered	T1,T2,T5
addr_hit[33]	Covered	T1,T2,T5
addr_hit[34]	Covered	T1,T2,T5
addr_hit[35]	Covered	T1,T2,T5
addr_hit[36]	Covered	T1,T2,T4
addr_hit[37]	Covered	T1,T2,T5
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	8878	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[36]	Covered	T1,T2,T4
addr_hit[37]	Covered	T1,T2,T5
default	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	114974898	82221	0	0
reAfterRv	114974898	82221	0	0
rePulse	114974898	56763	0	0
wePulse	114974898	25458	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	82221	0	0
T1	402040	15	0	0
T2	401555	7	0	0
T3	401703	7	0	0
T4	402110	18	0	0
T5	401703	9	0	0
T6	405709	15	0	0
T7	401583	9	0	0
T8	402585	18	0	0
T9	401755	7	0	0
T10	403540	18	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	82221	0	0
T1	402040	15	0	0
T2	401555	7	0	0
T3	401703	7	0	0
T4	402110	18	0	0
T5	401703	9	0	0
T6	405709	15	0	0
T7	401583	9	0	0
T8	402585	18	0	0
T9	401755	7	0	0
T10	403540	18	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	56763	0	0
T1	402040	4	0	0
T2	401555	2	0	0
T3	401703	2	0	0
T4	402110	6	0	0
T5	401703	3	0	0
T6	405709	4	0	0
T7	401583	3	0	0
T8	402585	6	0	0
T9	401755	2	0	0
T10	403540	6	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	114974898	25458	0	0
T1	402040	11	0	0
T2	401555	5	0	0
T3	401703	5	0	0
T4	402110	12	0	0
T5	401703	6	0	0
T6	405709	11	0	0
T7	401583	6	0	0
T8	402585	12	0	0
T9	401755	5	0	0
T10	403540	12	0	0