Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39525	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	52325	1		T1	6		T2	4		T3	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54636	1		T1	4		T2	3		T3	4
values[0x0]	18252	1		T1	4		T2	5		T3	2
values[0x1]	18962	1		T1	1		T2	1		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26799	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	65051	1		T1	7		T2	4		T3	7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	340	1		T170	1		T171	1		T172	15
valid_sources[0x01]	262	1		T33	1		T96	1		T173	1
valid_sources[0x02]	354	1		T174	3		T175	1		T39	1
valid_sources[0x03]	329	1		T176	1		T177	2		T178	3
valid_sources[0x04]	321	1		T94	8		T179	1		T82	1
valid_sources[0x05]	269	1		T36	1		T108	2		T106	1
valid_sources[0x06]	347	1		T107	13		T97	1		T180	1
valid_sources[0x07]	349	1		T34	2		T106	2		T181	1
valid_sources[0x08]	318	1		T11	1		T180	1		T30	1
valid_sources[0x09]	316	1		T17	1		T182	3		T183	1
valid_sources[0x0a]	299	1		T101	4		T184	1		T72	2
valid_sources[0x0b]	331	1		T5	1		T19	1		T21	4
valid_sources[0x0c]	1843	1		T34	1		T185	2		T186	1
valid_sources[0x0d]	349	1		T111	1		T72	1		T187	1
valid_sources[0x0e]	333	1		T114	1		T188	2		T189	9
valid_sources[0x0f]	432	1		T190	1		T176	1		T105	3
valid_sources[0x10]	265	1		T16	1		T60	1		T118	18
valid_sources[0x11]	322	1		T16	1		T96	1		T100	4
valid_sources[0x12]	293	1		T21	1		T191	1		T30	2
valid_sources[0x13]	374	1		T60	1		T114	1		T99	1
valid_sources[0x14]	309	1		T10	1		T60	1		T192	1
valid_sources[0x15]	813	1		T10	1		T36	1		T190	1
valid_sources[0x16]	307	1		T193	5		T194	1		T195	1
valid_sources[0x17]	305	1		T14	2		T196	1		T149	2
valid_sources[0x18]	475	1		T197	3		T198	7		T199	1
valid_sources[0x19]	279	1		T104	1		T200	3		T184	1
valid_sources[0x1a]	300	1		T192	1		T108	3		T76	1
valid_sources[0x1b]	371	1		T201	1		T202	1		T72	1
valid_sources[0x1c]	338	1		T2	9		T5	1		T114	1
valid_sources[0x1d]	399	1		T34	1		T16	5		T59	2
valid_sources[0x1e]	351	1		T6	1		T190	1		T203	3
valid_sources[0x1f]	282	1		T23	1		T204	1		T85	1
valid_sources[0x20]	417	1		T6	1		T10	1		T56	2
valid_sources[0x21]	404	1		T17	1		T14	3		T96	1
valid_sources[0x22]	263	1		T99	1		T78	2		T186	1
valid_sources[0x23]	429	1		T100	2		T116	1		T204	1
valid_sources[0x24]	396	1		T71	9		T205	1		T23	1
valid_sources[0x25]	317	1		T60	1		T62	1		T108	1
valid_sources[0x26]	371	1		T1	9		T7	1		T206	1
valid_sources[0x27]	533	1		T207	18		T208	7		T209	1
valid_sources[0x28]	283	1		T5	1		T114	1		T210	2
valid_sources[0x29]	326	1		T3	1		T5	1		T173	3
valid_sources[0x2a]	401	1		T96	1		T147	4		T39	1
valid_sources[0x2b]	394	1		T5	1		T211	1		T212	1
valid_sources[0x2c]	373	1		T32	1		T109	18		T179	2
valid_sources[0x2d]	272	1		T97	4		T191	1		T75	12
valid_sources[0x2e]	522	1		T60	1		T173	1		T213	1
valid_sources[0x2f]	279	1		T214	1		T215	1		T182	1
valid_sources[0x30]	390	1		T20	1		T106	1		T101	1
valid_sources[0x31]	288	1		T213	1		T216	1		T196	1
valid_sources[0x32]	458	1		T190	1		T215	1		T178	2
valid_sources[0x33]	238	1		T217	1		T218	1		T148	2
valid_sources[0x34]	402	1		T219	1		T220	2		T221	4
valid_sources[0x35]	372	1		T222	1		T74	1		T177	3
valid_sources[0x36]	447	1		T108	1		T223	1		T224	2
valid_sources[0x37]	393	1		T99	1		T142	2		T194	2
valid_sources[0x38]	354	1		T31	4		T99	1		T170	1
valid_sources[0x39]	312	1		T11	1		T21	1		T90	1
valid_sources[0x3a]	393	1		T9	1		T89	1		T108	1
valid_sources[0x3b]	287	1		T21	4		T225	1		T220	1
valid_sources[0x3c]	320	1		T226	2		T183	1		T38	8
valid_sources[0x3d]	313	1		T17	1		T29	1		T97	4
valid_sources[0x3e]	367	1		T191	1		T216	1		T227	7
valid_sources[0x3f]	350	1		T5	1		T87	1		T213	1
valid_sources[0x40]	354	1		T228	1		T218	1		T24	1
valid_sources[0x41]	348	1		T228	1		T24	1		T229	15
valid_sources[0x42]	335	1		T101	1		T78	1		T230	9
valid_sources[0x43]	291	1		T5	1		T14	1		T111	5
valid_sources[0x44]	294	1		T5	1		T10	1		T231	1
valid_sources[0x45]	325	1		T201	1		T86	2		T218	1
valid_sources[0x46]	271	1		T7	1		T114	1		T232	4
valid_sources[0x47]	631	1		T60	1		T192	1		T76	2
valid_sources[0x48]	450	1		T222	2		T24	1		T233	5
valid_sources[0x49]	300	1		T173	1		T113	5		T234	9
valid_sources[0x4a]	331	1		T235	1		T236	1		T215	2
valid_sources[0x4b]	310	1		T36	1		T214	1		T87	2
valid_sources[0x4c]	324	1		T214	1		T216	1		T187	2
valid_sources[0x4d]	342	1		T31	4		T192	1		T87	1
valid_sources[0x4e]	366	1		T35	1		T86	5		T93	12
valid_sources[0x4f]	257	1		T24	1		T237	1		T238	1
valid_sources[0x50]	295	1		T10	1		T58	11		T222	1
valid_sources[0x51]	307	1		T221	3		T239	1		T182	5
valid_sources[0x52]	767	1		T240	1		T68	1		T199	1
valid_sources[0x53]	331	1		T32	2		T105	4		T180	2
valid_sources[0x54]	333	1		T89	3		T99	1		T108	1
valid_sources[0x55]	321	1		T180	1		T241	3		T30	5
valid_sources[0x56]	428	1		T4	1		T5	1		T242	2
valid_sources[0x57]	300	1		T10	1		T35	1		T101	2
valid_sources[0x58]	288	1		T17	1		T114	2		T111	2
valid_sources[0x59]	287	1		T9	1		T32	1		T112	15
valid_sources[0x5a]	384	1		T185	2		T243	1		T23	1
valid_sources[0x5b]	323	1		T95	2		T216	1		T48	1
valid_sources[0x5c]	301	1		T219	2		T210	1		T243	1
valid_sources[0x5d]	482	1		T95	1		T90	3		T244	4
valid_sources[0x5e]	317	1		T245	9		T243	1		T191	1
valid_sources[0x5f]	280	1		T228	1		T78	1		T23	1
valid_sources[0x60]	465	1		T239	1		T186	1		T246	1
valid_sources[0x61]	522	1		T9	1		T247	1		T147	3
valid_sources[0x62]	312	1		T200	1		T51	7		T47	4
valid_sources[0x63]	295	1		T18	7		T248	1		T198	2
valid_sources[0x64]	387	1		T100	4		T179	1		T249	1
valid_sources[0x65]	345	1		T96	2		T184	1		T82	1
valid_sources[0x66]	377	1		T250	1		T74	1		T203	1
valid_sources[0x67]	658	1		T6	2		T100	1		T206	1
valid_sources[0x68]	456	1		T105	3		T193	1		T251	8
valid_sources[0x69]	308	1		T70	1		T38	11		T48	4
valid_sources[0x6a]	359	1		T59	1		T106	4		T111	6
valid_sources[0x6b]	259	1		T11	1		T101	2		T188	1
valid_sources[0x6c]	439	1		T6	1		T24	1		T179	2
valid_sources[0x6d]	303	1		T35	2		T24	1		T252	1
valid_sources[0x6e]	304	1		T5	1		T34	2		T103	1
valid_sources[0x6f]	349	1		T6	1		T99	1		T220	2
valid_sources[0x70]	356	1		T90	1		T185	2		T116	1
valid_sources[0x71]	263	1		T76	4		T239	1		T249	1
valid_sources[0x72]	290	1		T7	1		T34	1		T253	1
valid_sources[0x73]	252	1		T59	1		T21	1		T111	1
valid_sources[0x74]	290	1		T13	18		T202	1		T253	1
valid_sources[0x75]	300	1		T89	1		T223	3		T23	1
valid_sources[0x76]	300	1		T11	1		T28	9		T40	1
valid_sources[0x77]	260	1		T89	1		T235	1		T254	7
valid_sources[0x78]	477	1		T141	9		T174	1		T74	1
valid_sources[0x79]	306	1		T56	1		T62	1		T191	1
valid_sources[0x7a]	387	1		T3	1		T95	1		T184	1
valid_sources[0x7b]	364	1		T56	1		T255	1		T154	1
valid_sources[0x7c]	352	1		T9	1		T32	1		T114	1
valid_sources[0x7d]	314	1		T58	6		T29	1		T243	1
valid_sources[0x7e]	431	1		T59	9		T76	4		T113	3
valid_sources[0x7f]	355	1		T95	1		T105	1		T66	12
valid_sources[0x80]	311	1		T90	1		T106	2		T87	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19640

1

T1

3

T2

1

T3

2

values[0x0]

all_enables

biggest_size

16787

1

T1

2

T2

2

T3

2

values[0x1]

all_enables

biggest_size

15898

1

T1

1

T2

1

T4

3