Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.49	96.38	62.63	93.46		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	114375595	10887	0	0
ep_in_enable_rd_A	114375595	729	0	0
ep_out_enable_rd_A	114375595	814	0	0
in_iso_rd_A	114375595	761	0	0
intr_enable_rd_A	114375595	1146	0	0
out_iso_rd_A	114375595	741	0	0
phy_config_rd_A	114375595	667	0	0
phy_pins_drive_rd_A	114375595	661	0	0
rxenable_setup_rd_A	114375595	975	0	0
set_nak_out_rd_A	114375595	832	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114375595	10887	0	0
T37	11220	761	0	0
T38	2576	5	0	0
T39	2942	468	0	0
T47	6015	16	0	0
T64	3626	8	0	0
T119	3816	17	0	0
T120	2009	7	0	0
T121	2417	10	0	0
T122	3518	14	0	0
T123	5739	13	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114375595	729	0	0
T49	3857	52	0	0
T53	2398	2	0	0
T127	16622	148	0	0
T134	4192	39	0	0
T139	14765	155	0	0
T159	4107	33	0	0
T160	6645	64	0	0
T161	3487	53	0	0
T162	6537	6	0	0
T163	3520	6	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114375595	814	0	0
T45	2710	1	0	0
T49	3857	7	0	0
T53	2398	4	0	0
T127	16622	111	0	0
T134	4192	36	0	0
T139	14765	274	0	0
T159	4107	22	0	0
T160	6645	32	0	0
T161	3487	41	0	0
T162	6537	42	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114375595	761	0	0
T49	3857	8	0	0
T53	2398	43	0	0
T127	16622	146	0	0
T134	4192	38	0	0
T139	14765	177	0	0
T160	6645	52	0	0
T161	3487	34	0	0
T162	6537	47	0	0
T163	3520	12	0	0
T164	2012	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114375595	1146	0	0
T45	2710	3	0	0
T49	3857	16	0	0
T53	2398	71	0	0
T127	16622	140	0	0
T134	4192	51	0	0
T139	14765	320	0	0
T159	4107	48	0	0
T160	6645	78	0	0
T161	3487	4	0	0
T162	6537	128	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114375595	741	0	0
T45	2710	3	0	0
T49	3857	34	0	0
T127	16622	134	0	0
T134	4192	1	0	0
T139	14765	191	0	0
T159	4107	22	0	0
T160	6645	50	0	0
T161	3487	33	0	0
T162	6537	18	0	0
T163	3520	55	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114375595	667	0	0
T45	2710	2	0	0
T49	3857	52	0	0
T53	2398	23	0	0
T127	16622	158	0	0
T134	4192	17	0	0
T139	14765	145	0	0
T160	6645	25	0	0
T162	6537	28	0	0
T163	3520	25	0	0
T164	2012	5	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114375595	661	0	0
T45	2710	3	0	0
T49	3857	33	0	0
T53	2398	33	0	0
T127	16622	145	0	0
T134	4192	46	0	0
T139	14765	122	0	0
T159	4107	2	0	0
T160	6645	48	0	0
T161	3487	20	0	0
T162	6537	31	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114375595	975	0	0
T45	2710	4	0	0
T49	3857	6	0	0
T127	16622	149	0	0
T134	4192	53	0	0
T139	14765	218	0	0
T159	4107	4	0	0
T160	6645	15	0	0
T161	3487	18	0	0
T162	6537	46	0	0
T163	3520	47	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114375595	832	0	0
T45	2710	8	0	0
T49	3857	82	0	0
T53	2398	58	0	0
T127	16622	170	0	0
T134	4192	15	0	0
T139	14765	155	0	0
T157	8380	2	0	0
T159	4107	25	0	0
T160	6645	45	0	0
T161	3487	38	0	0