Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	70003	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	67706	1		T1	250		T2	6		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	64223	1		T1	180		T2	5		T3	8
values[0x0]	36313	1		T1	367		T2	3		T3	6
values[0x1]	37173	1		T1	341		T2	3		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	53562	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	84147	1		T1	329		T2	8		T3	17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	562	1		T1	2		T6	1		T19	3
valid_sources[0x01]	429	1		T1	4		T19	6		T21	8
valid_sources[0x02]	477	1		T1	7		T19	1		T11	1
valid_sources[0x03]	656	1		T1	3		T19	2		T21	12
valid_sources[0x04]	448	1		T1	2		T19	2		T21	2
valid_sources[0x05]	483	1		T1	5		T19	2		T21	8
valid_sources[0x06]	398	1		T1	1		T19	4		T21	7
valid_sources[0x07]	436	1		T1	3		T19	3		T21	2
valid_sources[0x08]	483	1		T1	4		T19	4		T21	7
valid_sources[0x09]	686	1		T1	1		T19	4		T21	20
valid_sources[0x0a]	575	1		T1	1		T3	1		T7	1
valid_sources[0x0b]	459	1		T1	1		T19	2		T21	3
valid_sources[0x0c]	378	1		T1	4		T19	3		T21	6
valid_sources[0x0d]	455	1		T1	8		T19	5		T27	2
valid_sources[0x0e]	492	1		T1	8		T19	6		T21	17
valid_sources[0x0f]	624	1		T1	2		T19	4		T59	5
valid_sources[0x10]	462	1		T1	8		T19	1		T59	1
valid_sources[0x11]	418	1		T1	3		T19	1		T21	1
valid_sources[0x12]	394	1		T1	1		T19	1		T21	13
valid_sources[0x13]	430	1		T1	3		T19	3		T15	22
valid_sources[0x14]	452	1		T1	2		T19	6		T176	1
valid_sources[0x15]	479	1		T1	4		T3	1		T19	4
valid_sources[0x16]	515	1		T1	1		T19	2		T21	1
valid_sources[0x17]	664	1		T1	2		T21	5		T31	11
valid_sources[0x18]	351	1		T1	3		T19	3		T21	11
valid_sources[0x19]	514	1		T1	1		T19	4		T21	1
valid_sources[0x1a]	532	1		T1	9		T3	2		T19	8
valid_sources[0x1b]	459	1		T1	8		T19	3		T21	2
valid_sources[0x1c]	715	1		T1	2		T19	4		T21	22
valid_sources[0x1d]	389	1		T1	2		T3	1		T19	4
valid_sources[0x1e]	439	1		T1	6		T21	11		T8	1
valid_sources[0x1f]	389	1		T1	1		T6	1		T21	2
valid_sources[0x20]	423	1		T1	3		T19	7		T21	8
valid_sources[0x21]	417	1		T1	1		T6	1		T19	3
valid_sources[0x22]	470	1		T1	3		T19	1		T176	5
valid_sources[0x23]	469	1		T1	5		T19	2		T21	2
valid_sources[0x24]	466	1		T1	7		T19	5		T21	8
valid_sources[0x25]	433	1		T1	6		T19	5		T8	1
valid_sources[0x26]	615	1		T1	2		T6	1		T21	6
valid_sources[0x27]	1474	1		T1	3		T19	3		T21	1
valid_sources[0x28]	539	1		T1	3		T3	1		T19	6
valid_sources[0x29]	600	1		T1	1		T19	3		T59	7
valid_sources[0x2a]	516	1		T1	6		T19	1		T21	6
valid_sources[0x2b]	512	1		T1	6		T19	2		T176	8
valid_sources[0x2c]	483	1		T1	1		T19	4		T21	6
valid_sources[0x2d]	586	1		T1	4		T19	4		T21	1
valid_sources[0x2e]	605	1		T1	4		T176	5		T177	23
valid_sources[0x2f]	481	1		T1	3		T19	2		T21	3
valid_sources[0x30]	460	1		T1	4		T19	4		T176	6
valid_sources[0x31]	472	1		T1	1		T19	1		T21	13
valid_sources[0x32]	656	1		T1	4		T19	5		T21	16
valid_sources[0x33]	377	1		T1	6		T2	2		T19	2
valid_sources[0x34]	537	1		T1	7		T19	3		T21	8
valid_sources[0x35]	619	1		T1	9		T19	3		T21	4
valid_sources[0x36]	444	1		T1	2		T3	1		T178	1
valid_sources[0x37]	392	1		T1	1		T23	1		T12	1
valid_sources[0x38]	580	1		T1	4		T18	1		T6	1
valid_sources[0x39]	518	1		T1	4		T2	3		T4	2
valid_sources[0x3a]	422	1		T1	3		T19	4		T59	3
valid_sources[0x3b]	453	1		T1	6		T19	2		T21	3
valid_sources[0x3c]	539	1		T1	5		T18	1		T4	1
valid_sources[0x3d]	414	1		T1	6		T18	2		T19	1
valid_sources[0x3e]	445	1		T1	2		T4	1		T19	4
valid_sources[0x3f]	459	1		T1	6		T19	4		T21	7
valid_sources[0x40]	498	1		T1	2		T59	1		T176	6
valid_sources[0x41]	460	1		T1	1		T3	1		T19	2
valid_sources[0x42]	367	1		T1	2		T19	3		T21	9
valid_sources[0x43]	396	1		T1	11		T19	2		T21	5
valid_sources[0x44]	427	1		T1	5		T19	4		T21	3
valid_sources[0x45]	442	1		T3	1		T19	5		T21	5
valid_sources[0x46]	467	1		T1	10		T19	4		T21	4
valid_sources[0x47]	395	1		T1	7		T19	5		T21	1
valid_sources[0x48]	460	1		T1	5		T19	4		T21	3
valid_sources[0x49]	451	1		T1	2		T19	2		T21	15
valid_sources[0x4a]	539	1		T3	1		T19	1		T21	6
valid_sources[0x4b]	498	1		T1	2		T21	13		T11	1
valid_sources[0x4c]	648	1		T1	5		T59	6		T176	1
valid_sources[0x4d]	665	1		T1	5		T19	4		T21	2
valid_sources[0x4e]	476	1		T1	1		T5	5		T19	7
valid_sources[0x4f]	586	1		T1	6		T19	4		T59	4
valid_sources[0x50]	399	1		T1	4		T7	2		T19	2
valid_sources[0x51]	495	1		T19	5		T21	2		T9	1
valid_sources[0x52]	851	1		T1	6		T59	1		T176	4
valid_sources[0x53]	412	1		T1	3		T19	3		T21	11
valid_sources[0x54]	419	1		T1	1		T19	4		T21	2
valid_sources[0x55]	466	1		T1	4		T19	1		T59	1
valid_sources[0x56]	432	1		T1	13		T19	3		T21	5
valid_sources[0x57]	1402	1		T5	6		T19	2		T59	2
valid_sources[0x58]	421	1		T1	9		T19	3		T21	6
valid_sources[0x59]	475	1		T19	3		T21	10		T8	1
valid_sources[0x5a]	408	1		T1	5		T3	1		T19	2
valid_sources[0x5b]	774	1		T1	3		T19	4		T14	2
valid_sources[0x5c]	464	1		T4	1		T21	12		T176	2
valid_sources[0x5d]	650	1		T1	2		T6	1		T19	3
valid_sources[0x5e]	524	1		T1	3		T3	1		T21	17
valid_sources[0x5f]	415	1		T1	3		T19	2		T59	1
valid_sources[0x60]	420	1		T1	2		T19	7		T21	2
valid_sources[0x61]	415	1		T1	1		T19	1		T21	2
valid_sources[0x62]	421	1		T1	4		T19	3		T176	2
valid_sources[0x63]	663	1		T1	2		T19	4		T21	2
valid_sources[0x64]	425	1		T1	3		T19	3		T59	1
valid_sources[0x65]	603	1		T19	3		T59	6		T176	7
valid_sources[0x66]	581	1		T1	1		T19	6		T21	3
valid_sources[0x67]	558	1		T1	9		T19	9		T21	1
valid_sources[0x68]	620	1		T1	3		T19	5		T21	3
valid_sources[0x69]	543	1		T1	4		T18	3		T19	2
valid_sources[0x6a]	417	1		T1	4		T19	4		T21	3
valid_sources[0x6b]	472	1		T1	4		T19	1		T21	3
valid_sources[0x6c]	534	1		T1	2		T19	2		T12	1
valid_sources[0x6d]	490	1		T1	4		T19	5		T11	1
valid_sources[0x6e]	1127	1		T1	1		T4	1		T19	3
valid_sources[0x6f]	409	1		T1	1		T19	2		T21	5
valid_sources[0x70]	544	1		T1	8		T6	1		T19	1
valid_sources[0x71]	2010	1		T1	4		T19	2		T21	3
valid_sources[0x72]	536	1		T1	7		T27	1		T176	2
valid_sources[0x73]	442	1		T1	4		T19	5		T176	7
valid_sources[0x74]	432	1		T1	3		T21	7		T26	1
valid_sources[0x75]	528	1		T1	4		T19	4		T176	1
valid_sources[0x76]	462	1		T7	3		T19	2		T21	8
valid_sources[0x77]	458	1		T1	5		T19	2		T21	5
valid_sources[0x78]	477	1		T1	1		T19	1		T21	1
valid_sources[0x79]	441	1		T3	1		T19	3		T21	5
valid_sources[0x7a]	564	1		T1	2		T4	1		T19	3
valid_sources[0x7b]	516	1		T1	2		T4	1		T19	5
valid_sources[0x7c]	667	1		T1	4		T19	8		T21	8
valid_sources[0x7d]	360	1		T1	4		T19	2		T176	2
valid_sources[0x7e]	483	1		T1	3		T19	8		T21	12
valid_sources[0x7f]	496	1		T1	4		T19	1		T21	2
valid_sources[0x80]	463	1		T1	9		T19	3		T21	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25353

1

T1

81

T2

3

T3

4

values[0x0]

all_enables

biggest_size

23339

1

T1

117

T2

3

T3

4

values[0x1]

all_enables

biggest_size

19014

1

T1

52

T3

4

T18

1