Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	85317	1		T1	638		T2	5		T3	10
full_word	68756	1		T1	250		T2	6		T3	12

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	153923	1		T1	888		T2	11		T3	22
auto[TlIntgErrCmd]	52	1		T36	3		T37	3		T149	2
auto[TlIntgErrData]	44	1		T36	1		T37	3		T149	3
auto[TlIntgErrBoth]	54	1		T36	6		T37	4		T149	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	66181	1		T1	180		T2	5		T3	8
auto[1]	87892	1		T1	708		T2	6		T3	14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	40587	1		T1	99		T2	2		T3	4
auto[TlIntgErrNone]	partial	auto[1]	44592	1		T1	539		T2	3		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	25530	1		T1	81		T2	3		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	43214	1		T1	169		T2	3		T3	8
auto[TlIntgErrCmd]	partial	auto[0]	22	1		T36	2		T37	1		T149	1
auto[TlIntgErrCmd]	partial	auto[1]	27	1		T36	1		T37	2		T149	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T169	1		T170	1		T171	1
auto[TlIntgErrData]	partial	auto[0]	23	1		T149	1		T169	4		T172	1
auto[TlIntgErrData]	partial	auto[1]	18	1		T36	1		T37	3		T149	1
auto[TlIntgErrData]	full_word	auto[0]	1	1		T149	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1		T170	1		T173	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	16	1		T36	2		T37	2		T149	1
auto[TlIntgErrBoth]	partial	auto[1]	32	1		T36	3		T37	1		T149	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T37	1		T172	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T36	1		T169	1		T174	1