Line Coverage for Instance : tb.dut.u_reg.u_set_nak_out_enable_10.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_set_nak_out_enable_10.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T11,T12 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T11,T12 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T11,T12 |
Branch Coverage for Instance : tb.dut.u_reg.u_set_nak_out_enable_10.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T11,T12 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_set_nak_out_enable_11.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_set_nak_out_enable_11.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T4,T11,T12 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T11,T12 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T11,T12 |
Branch Coverage for Instance : tb.dut.u_reg.u_set_nak_out_enable_11.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T11,T12 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_0.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T68,T97,T98 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T68,T97,T98 |
1 | 1 | Covered | T68,T97,T98 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T68,T97,T98 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_1.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T66,T67,T99 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T66,T67,T99 |
1 | 1 | Covered | T66,T67,T99 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T66,T67,T99 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_2.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T100,T101,T102 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T100,T101,T102 |
1 | 1 | Covered | T100,T101,T102 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T100,T101,T102 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_3.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T103,T104,T105 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T103,T104,T105 |
1 | 1 | Covered | T103,T104,T105 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T103,T104,T105 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_4.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T10,T106 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T10,T106 |
1 | 1 | Covered | T3,T10,T106 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T106 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_5.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T26,T107 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T26,T107 |
1 | 1 | Covered | T13,T26,T107 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T13,T26,T107 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_6.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T108,T109,T110 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T108,T109,T110 |
1 | 1 | Covered | T108,T109,T110 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T108,T109,T110 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_7.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T22,T111,T112 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T22,T111,T112 |
1 | 1 | Covered | T22,T111,T112 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T22,T111,T112 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_8.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_8.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T113,T114,T115 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T113,T114,T115 |
1 | 1 | Covered | T113,T114,T115 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T113,T114,T115 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_9.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_9.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T116,T117,T118 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T116,T117,T118 |
1 | 1 | Covered | T116,T117,T118 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T116,T117,T118 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_10.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_10.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T119,T120,T121 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T119,T120,T121 |
1 | 1 | Covered | T119,T120,T121 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T119,T120,T121 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_11.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
88 |
1 |
1 |
110 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_in_sent_sent_11.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T15,T122,T123 |
1 | 0 | Covered | T3,T10,T13 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T15,T122,T123 |
1 | 1 | Covered | T15,T122,T123 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T15,T122,T123 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T13 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_0.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 7 | 100.00 |
Logical | 7 | 7 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T9 |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_1.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_2.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_3.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_4.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_5.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_6.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_7.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_8.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_8.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_8.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_9.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_9.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_9.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_10.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_10.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_10.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_11.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_11.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_out_stall_endpoint_11.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_0.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 7 | 100.00 |
Logical | 7 | 7 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T6,T7,T9 |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_1.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_2.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_3.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_4.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_5.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
CONT_ASSIGN | 39 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
33 |
1 |
1 |
34 |
1 |
1 |
39 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_6.wr_en_data_arb
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T44,T36,T45 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T44,T36,T45 |
Branch Coverage for Instance : tb.dut.u_reg.u_in_stall_endpoint_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
TERNARY |
34 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 34 ((we == 1'b1)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T44,T36,T45 |
0 |
Covered |
T1,T2,T3 |