Unified Coverage Report :: Module :: usb_fs_nb_pe

Module : usb_fs_nb_pe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	50.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_pe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe	83.33	100.00	50.00				100.00

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	50.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.29	92.86	82.46		54.05	87.08	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.61	97.06	94.20			91.18	100.00	usbdev_impl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_usb_fs_nb_in_pe	77.75	84.26	80.00		50.00	74.47	100.00
u_usb_fs_nb_out_pe	78.31	86.51	75.81		50.00	79.25	100.00
u_usb_fs_rx	93.25	98.92	87.56			93.26
u_usb_fs_tx	86.28	95.61	84.48		58.82	92.50	100.00
u_usb_fs_tx_mux	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_nb_pe

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
CONT_ASSIGN	158	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_pe.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
152	1	1
153	1	1
154	1	1
158	1	1

---

Cond Coverage for Module : usb_fs_nb_pe

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       152
 EXPRESSION (rx_pkt_end & rx_pkt_valid & (usb_pid_e'(rx_pid) == UsbPidSof))
             -----1----   ------2-----   ----------------3----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T2,T3,T18
1	1	1	Not Covered

 LINE       152
 SUB-EXPRESSION (usb_pid_e'(rx_pid) == UsbPidSof)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T13

---

Assert Coverage for Module : usb_fs_nb_pe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumOutEpsEqualsNumInEps_A	326	326	0	0
ParamMaxPktSizeByteValid	326	326	0	0
ParamNumEpsOutAndInEqual	326	326	0	0
ParamNumInEpsValid	326	326	0	0
ParamNumOutEpsValid	326	326	0	0

NumOutEpsEqualsNumInEps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326	326	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ParamMaxPktSizeByteValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	326	326	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ParamNumEpsOutAndInEqual

Name	Attempts	Real Successes	Failures	Incomplete
Total	326	326	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ParamNumInEpsValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	326	326	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

ParamNumOutEpsValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	326	326	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0