Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58708	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	62466	1		T1	5		T2	5		T3	274

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52825	1		T1	4		T2	5		T3	185
values[0x0]	33736	1		T1	1		T2	2		T3	391
values[0x1]	34613	1		T1	7		T2	4		T3	408

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45032	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	76142	1		T1	9		T2	10		T3	369

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	518	1		T231	3		T232	1		T233	3
valid_sources[0x01]	368	1		T74	4		T76	4		T234	6
valid_sources[0x02]	390	1		T3	5		T43	4		T44	5
valid_sources[0x03]	394	1		T3	3		T5	1		T76	1
valid_sources[0x04]	471	1		T7	1		T43	1		T44	3
valid_sources[0x05]	346	1		T3	3		T44	2		T30	9
valid_sources[0x06]	360	1		T3	2		T43	1		T74	6
valid_sources[0x07]	2105	1		T3	19		T43	1		T44	5
valid_sources[0x08]	448	1		T17	8		T44	7		T235	1
valid_sources[0x09]	608	1		T3	5		T231	1		T43	13
valid_sources[0x0a]	348	1		T3	6		T12	1		T16	1
valid_sources[0x0b]	363	1		T44	1		T74	5		T76	10
valid_sources[0x0c]	347	1		T44	1		T74	4		T233	10
valid_sources[0x0d]	519	1		T3	3		T44	2		T236	1
valid_sources[0x0e]	420	1		T3	19		T11	2		T76	2
valid_sources[0x0f]	350	1		T3	3		T74	6		T232	1
valid_sources[0x10]	357	1		T21	1		T17	2		T44	3
valid_sources[0x11]	367	1		T3	1		T74	4		T76	1
valid_sources[0x12]	360	1		T3	13		T74	3		T76	11
valid_sources[0x13]	329	1		T44	5		T74	7		T76	4
valid_sources[0x14]	405	1		T3	7		T21	1		T43	21
valid_sources[0x15]	327	1		T3	4		T44	3		T35	2
valid_sources[0x16]	375	1		T44	4		T107	2		T74	6
valid_sources[0x17]	431	1		T3	10		T74	5		T83	2
valid_sources[0x18]	344	1		T3	3		T8	7		T74	4
valid_sources[0x19]	427	1		T74	2		T233	11		T121	1
valid_sources[0x1a]	559	1		T43	4		T44	8		T237	2
valid_sources[0x1b]	491	1		T3	17		T16	1		T44	10
valid_sources[0x1c]	582	1		T22	4		T44	3		T33	1
valid_sources[0x1d]	400	1		T44	3		T29	2		T74	2
valid_sources[0x1e]	347	1		T16	1		T19	1		T44	4
valid_sources[0x1f]	396	1		T44	3		T74	2		T237	2
valid_sources[0x20]	597	1		T5	1		T76	1		T237	4
valid_sources[0x21]	378	1		T7	1		T44	17		T33	2
valid_sources[0x22]	394	1		T3	2		T44	5		T74	6
valid_sources[0x23]	415	1		T3	16		T8	1		T12	1
valid_sources[0x24]	347	1		T3	5		T44	1		T84	1
valid_sources[0x25]	470	1		T43	6		T44	7		T84	1
valid_sources[0x26]	360	1		T3	6		T44	4		T74	9
valid_sources[0x27]	475	1		T3	8		T44	5		T76	30
valid_sources[0x28]	424	1		T14	1		T84	1		T35	1
valid_sources[0x29]	370	1		T3	6		T9	1		T12	1
valid_sources[0x2a]	418	1		T16	1		T44	4		T74	4
valid_sources[0x2b]	351	1		T14	1		T107	1		T74	3
valid_sources[0x2c]	348	1		T44	3		T74	3		T83	2
valid_sources[0x2d]	448	1		T3	18		T5	1		T9	1
valid_sources[0x2e]	347	1		T3	20		T43	7		T74	4
valid_sources[0x2f]	432	1		T3	22		T44	1		T74	10
valid_sources[0x30]	454	1		T3	13		T43	28		T74	2
valid_sources[0x31]	417	1		T11	1		T12	1		T43	1
valid_sources[0x32]	444	1		T4	1		T44	2		T33	1
valid_sources[0x33]	462	1		T3	5		T32	10		T44	4
valid_sources[0x34]	391	1		T3	2		T43	7		T44	10
valid_sources[0x35]	438	1		T3	28		T43	6		T44	12
valid_sources[0x36]	367	1		T3	2		T4	2		T44	3
valid_sources[0x37]	619	1		T3	4		T43	25		T44	4
valid_sources[0x38]	416	1		T3	5		T20	2		T44	12
valid_sources[0x39]	322	1		T44	8		T74	2		T76	1
valid_sources[0x3a]	1044	1		T3	16		T5	2		T35	1
valid_sources[0x3b]	485	1		T3	6		T14	1		T15	13
valid_sources[0x3c]	400	1		T2	11		T3	18		T19	1
valid_sources[0x3d]	656	1		T3	3		T14	2		T74	7
valid_sources[0x3e]	557	1		T20	5		T235	1		T74	5
valid_sources[0x3f]	344	1		T9	1		T44	1		T74	5
valid_sources[0x40]	396	1		T18	2		T238	3		T74	3
valid_sources[0x41]	495	1		T3	1		T16	1		T44	5
valid_sources[0x42]	476	1		T3	6		T14	1		T74	4
valid_sources[0x43]	384	1		T3	1		T9	1		T16	1
valid_sources[0x44]	388	1		T19	1		T44	16		T74	6
valid_sources[0x45]	381	1		T16	1		T44	4		T74	2
valid_sources[0x46]	416	1		T3	7		T74	5		T233	18
valid_sources[0x47]	392	1		T18	3		T74	2		T233	13
valid_sources[0x48]	353	1		T14	1		T76	2		T234	2
valid_sources[0x49]	537	1		T3	6		T43	11		T35	1
valid_sources[0x4a]	341	1		T3	2		T44	3		T107	1
valid_sources[0x4b]	441	1		T43	3		T44	6		T74	3
valid_sources[0x4c]	557	1		T231	1		T44	9		T74	2
valid_sources[0x4d]	295	1		T1	12		T44	5		T83	2
valid_sources[0x4e]	504	1		T3	3		T11	1		T44	2
valid_sources[0x4f]	607	1		T5	1		T43	12		T44	3
valid_sources[0x50]	413	1		T16	1		T44	7		T76	1
valid_sources[0x51]	324	1		T16	1		T44	10		T74	2
valid_sources[0x52]	345	1		T21	1		T16	1		T43	5
valid_sources[0x53]	3501	1		T3	3		T44	1		T74	5
valid_sources[0x54]	403	1		T3	4		T43	8		T44	2
valid_sources[0x55]	432	1		T43	8		T239	4		T74	7
valid_sources[0x56]	337	1		T44	2		T74	5		T240	1
valid_sources[0x57]	459	1		T43	2		T44	11		T33	2
valid_sources[0x58]	356	1		T231	1		T16	1		T19	1
valid_sources[0x59]	430	1		T3	2		T44	3		T35	1
valid_sources[0x5a]	547	1		T3	3		T11	1		T241	10
valid_sources[0x5b]	399	1		T3	21		T44	4		T74	4
valid_sources[0x5c]	402	1		T3	35		T43	24		T19	1
valid_sources[0x5d]	323	1		T18	1		T44	2		T29	1
valid_sources[0x5e]	340	1		T3	8		T44	4		T76	7
valid_sources[0x5f]	476	1		T3	18		T13	5		T44	12
valid_sources[0x60]	497	1		T3	9		T43	3		T17	2
valid_sources[0x61]	505	1		T3	17		T44	3		T238	1
valid_sources[0x62]	390	1		T44	1		T76	19		T237	4
valid_sources[0x63]	348	1		T3	9		T28	2		T76	7
valid_sources[0x64]	916	1		T3	10		T34	8		T43	3
valid_sources[0x65]	461	1		T3	8		T43	2		T44	4
valid_sources[0x66]	405	1		T74	6		T233	30		T237	1
valid_sources[0x67]	423	1		T74	3		T36	1		T234	4
valid_sources[0x68]	505	1		T43	47		T74	4		T76	1
valid_sources[0x69]	389	1		T3	27		T242	7		T44	6
valid_sources[0x6a]	427	1		T43	11		T107	1		T243	1
valid_sources[0x6b]	352	1		T3	2		T43	4		T44	2
valid_sources[0x6c]	387	1		T3	8		T43	11		T44	3
valid_sources[0x6d]	373	1		T3	14		T7	1		T231	1
valid_sources[0x6e]	325	1		T21	1		T43	3		T74	4
valid_sources[0x6f]	388	1		T74	12		T244	1		T237	6
valid_sources[0x70]	427	1		T16	1		T74	6		T76	1
valid_sources[0x71]	1183	1		T4	2		T44	2		T74	7
valid_sources[0x72]	274	1		T33	1		T74	5		T237	2
valid_sources[0x73]	319	1		T7	1		T16	1		T74	1
valid_sources[0x74]	481	1		T19	1		T44	8		T74	2
valid_sources[0x75]	423	1		T16	1		T43	4		T44	9
valid_sources[0x76]	388	1		T43	23		T44	1		T234	3
valid_sources[0x77]	508	1		T43	3		T74	1		T76	5
valid_sources[0x78]	395	1		T3	4		T5	1		T44	1
valid_sources[0x79]	417	1		T3	5		T74	8		T76	2
valid_sources[0x7a]	372	1		T3	3		T7	1		T31	3
valid_sources[0x7b]	400	1		T6	2		T43	19		T243	4
valid_sources[0x7c]	425	1		T3	11		T43	13		T44	3
valid_sources[0x7d]	357	1		T3	15		T16	1		T44	2
valid_sources[0x7e]	382	1		T4	1		T5	2		T21	1
valid_sources[0x7f]	390	1		T5	1		T74	2		T76	5
valid_sources[0x80]	365	1		T3	5		T76	7		T233	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22383

1

T1

4

T2

2

T3

90

values[0x0]

all_enables

biggest_size

21932

1

T1

1

T2

2

T3

121

values[0x1]

all_enables

biggest_size

18151

1

T2

1

T3

63

T4

2