Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	73764	1		T1	7		T2	6		T3	710
full_word	63552	1		T1	5		T2	5		T3	274

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	137216	1		T1	12		T2	11		T3	984
auto[TlIntgErrCmd]	33	1		T79	2		T142	3		T141	5
auto[TlIntgErrData]	37	1		T79	7		T142	3		T141	1
auto[TlIntgErrBoth]	30	1		T79	1		T142	4		T141	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	54912	1		T1	4		T2	5		T3	185
auto[1]	82404	1		T1	8		T2	6		T3	799

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	32277	1		T2	3		T3	95		T4	1
auto[TlIntgErrNone]	partial	auto[1]	41397	1		T1	7		T2	3		T3	615
auto[TlIntgErrNone]	full_word	auto[0]	22590	1		T1	4		T2	2		T3	90
auto[TlIntgErrNone]	full_word	auto[1]	40952	1		T1	1		T2	3		T3	184
auto[TlIntgErrCmd]	partial	auto[0]	11	1		T79	1		T142	1		T228	2
auto[TlIntgErrCmd]	partial	auto[1]	20	1		T79	1		T142	2		T141	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T213	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T141	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	16	1		T79	2		T141	1		T228	2
auto[TlIntgErrData]	partial	auto[1]	18	1		T79	5		T142	2		T228	2
auto[TlIntgErrData]	full_word	auto[0]	1	1		T142	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1		T213	1		T229	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	14	1		T79	1		T141	2		T228	3
auto[TlIntgErrBoth]	partial	auto[1]	11	1		T142	3		T141	2		T213	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T142	1		T213	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T228	1		T212	1		T230	1