Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.76	96.45	63.89	93.46		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	213346323	12215	0	0
ep_in_enable_rd_A	213346323	844	0	0
ep_out_enable_rd_A	213346323	1071	0	0
in_iso_rd_A	213346323	713	0	0
intr_enable_rd_A	213346323	1507	0	0
out_iso_rd_A	213346323	786	0	0
phy_config_rd_A	213346323	679	0	0
phy_pins_drive_rd_A	213346323	632	0	0
rxenable_setup_rd_A	213346323	1037	0	0
set_nak_out_rd_A	213346323	754	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213346323	12215	0	0
T45	5821	18	0	0
T46	3589	12	0	0
T47	3970	220	0	0
T51	3306	8	0	0
T52	8174	14	0	0
T78	3379	25	0	0
T79	5986	3	0	0
T137	5375	342	0	0
T138	13129	772	0	0
T142	6428	5	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213346323	844	0	0
T52	8174	40	0	0
T53	5035	39	0	0
T140	3891	49	0	0
T145	2435	7	0	0
T155	3475	14	0	0
T156	10078	124	0	0
T161	7639	43	0	0
T206	4521	22	0	0
T207	6315	97	0	0
T208	6999	30	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213346323	1071	0	0
T52	8174	135	0	0
T53	5035	26	0	0
T140	3891	59	0	0
T145	2435	7	0	0
T148	3885	8	0	0
T161	7639	42	0	0
T206	4521	8	0	0
T207	6315	22	0	0
T208	6999	40	0	0
T209	3909	20	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213346323	713	0	0
T52	8174	48	0	0
T53	5035	31	0	0
T140	3891	62	0	0
T145	2435	4	0	0
T148	3885	8	0	0
T151	2272	36	0	0
T161	7639	39	0	0
T206	4521	17	0	0
T207	6315	44	0	0
T208	6999	20	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213346323	1507	0	0
T52	8174	161	0	0
T53	5035	29	0	0
T60	1510	20	0	0
T140	3891	68	0	0
T145	2435	38	0	0
T148	3885	35	0	0
T161	7639	44	0	0
T206	4521	4	0	0
T210	1258	9	0	0
T211	1465	25	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213346323	786	0	0
T52	8174	60	0	0
T53	5035	19	0	0
T140	3891	7	0	0
T145	2435	23	0	0
T148	3885	20	0	0
T151	2272	8	0	0
T161	7639	58	0	0
T206	4521	47	0	0
T207	6315	14	0	0
T209	3909	12	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213346323	679	0	0
T52	8174	45	0	0
T53	5035	11	0	0
T140	3891	12	0	0
T145	2435	10	0	0
T148	3885	28	0	0
T161	7639	45	0	0
T206	4521	11	0	0
T207	6315	42	0	0
T208	6999	24	0	0
T209	3909	3	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213346323	632	0	0
T52	8174	70	0	0
T53	5035	14	0	0
T140	3891	12	0	0
T145	2435	4	0	0
T148	3885	15	0	0
T161	7639	53	0	0
T206	4521	43	0	0
T207	6315	63	0	0
T208	6999	15	0	0
T209	3909	19	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213346323	1037	0	0
T52	8174	43	0	0
T53	5035	37	0	0
T140	3891	10	0	0
T145	2435	30	0	0
T148	3885	19	0	0
T151	2272	23	0	0
T161	7639	19	0	0
T206	4521	14	0	0
T207	6315	16	0	0
T209	3909	11	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	213346323	754	0	0
T52	8174	98	0	0
T53	5035	28	0	0
T137	5375	5	0	0
T140	3891	44	0	0
T145	2435	28	0	0
T148	3885	4	0	0
T151	2272	3	0	0
T161	7639	61	0	0
T206	4521	18	0	0
T209	3909	14	0	0