Module Definition
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Module : usbdev_iomux
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.62 81.25 50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_iomux.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.i_usbdev_iomux 65.62 81.25 50.00



Module Instance : tb.dut.i_usbdev_iomux

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
65.62 81.25 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 88.89 44.44 83.33 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.76 96.45 63.89 93.46 85.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
cdc_io_to_usb 100.00 100.00 100.00
i_mux_tx_d 64.81 100.00 44.44 50.00
i_mux_tx_dn 64.81 100.00 44.44 50.00
i_mux_tx_dp 64.81 100.00 44.44 50.00
i_mux_tx_oe 64.81 100.00 44.44 50.00
i_mux_tx_se0 64.81 100.00 44.44 50.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usbdev_iomux
Line No.TotalCoveredPercent
TOTAL161381.25
CONT_ASSIGN7311100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
ALWAYS887457.14
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_iomux.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_iomux.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
73 1 1
74 1 1
75 1 1
76 1 1
77 1 1
78 1 1
79 1 1
80 1 1
81 1 1
88 1 1
90 0 1
91 0 1
92 0 1
95 1 1
96 1 1
97 1 1


Branch Coverage for Module : usbdev_iomux
Line No.TotalCoveredPercent
Branches 2 1 50.00
IF 88 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_iomux.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_iomux.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 if (reg2hw_drive_i.en.q)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%