Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66905	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	69000	1		T1	7		T2	10		T3	11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	63442	1		T1	3		T2	8		T3	7
values[0x0]	36041	1		T1	4		T2	5		T3	4
values[0x1]	36422	1		T1	3		T2	9		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50962	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	84943	1		T1	7		T2	16		T3	12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	418	1		T24	1		T40	1		T119	1
valid_sources[0x01]	572	1		T38	1		T40	3		T68	1
valid_sources[0x02]	515	1		T38	1		T40	3		T233	5
valid_sources[0x03]	491	1		T38	5		T36	1		T40	5
valid_sources[0x04]	1422	1		T38	2		T68	1		T233	9
valid_sources[0x05]	519	1		T38	1		T40	9		T68	2
valid_sources[0x06]	474	1		T38	2		T10	3		T36	1
valid_sources[0x07]	381	1		T40	1		T68	1		T173	5
valid_sources[0x08]	449	1		T38	3		T14	2		T40	4
valid_sources[0x09]	566	1		T38	4		T70	1		T71	1
valid_sources[0x0a]	422	1		T8	1		T38	8		T40	3
valid_sources[0x0b]	438	1		T38	4		T22	1		T31	1
valid_sources[0x0c]	454	1		T1	7		T38	1		T40	3
valid_sources[0x0d]	415	1		T38	4		T13	7		T40	2
valid_sources[0x0e]	399	1		T2	10		T38	1		T40	8
valid_sources[0x0f]	429	1		T38	3		T35	4		T40	4
valid_sources[0x10]	420	1		T38	5		T13	2		T40	2
valid_sources[0x11]	413	1		T38	2		T40	2		T67	1
valid_sources[0x12]	401	1		T38	7		T40	5		T32	1
valid_sources[0x13]	364	1		T5	8		T38	9		T11	1
valid_sources[0x14]	442	1		T38	1		T10	1		T40	6
valid_sources[0x15]	502	1		T38	6		T11	2		T119	2
valid_sources[0x16]	449	1		T38	3		T14	1		T40	2
valid_sources[0x17]	497	1		T38	3		T233	3		T173	4
valid_sources[0x18]	357	1		T38	1		T108	1		T69	1
valid_sources[0x19]	392	1		T38	1		T40	5		T233	3
valid_sources[0x1a]	523	1		T38	1		T111	1		T40	4
valid_sources[0x1b]	494	1		T40	3		T233	2		T173	3
valid_sources[0x1c]	443	1		T38	4		T40	1		T234	2
valid_sources[0x1d]	421	1		T1	2		T38	4		T40	1
valid_sources[0x1e]	602	1		T235	12		T31	1		T40	4
valid_sources[0x1f]	417	1		T38	8		T40	5		T177	1
valid_sources[0x20]	457	1		T2	1		T40	4		T233	4
valid_sources[0x21]	539	1		T38	3		T40	3		T67	1
valid_sources[0x22]	454	1		T38	5		T10	2		T40	1
valid_sources[0x23]	383	1		T2	8		T38	1		T40	3
valid_sources[0x24]	1206	1		T1	1		T38	3		T25	2
valid_sources[0x25]	380	1		T38	4		T40	2		T23	2
valid_sources[0x26]	434	1		T6	16		T38	4		T233	10
valid_sources[0x27]	445	1		T38	1		T40	1		T233	4
valid_sources[0x28]	407	1		T40	6		T78	1		T69	1
valid_sources[0x29]	317	1		T38	3		T14	1		T40	2
valid_sources[0x2a]	323	1		T2	3		T38	7		T40	2
valid_sources[0x2b]	471	1		T9	1		T24	3		T40	4
valid_sources[0x2c]	364	1		T38	2		T10	1		T40	3
valid_sources[0x2d]	424	1		T38	4		T11	1		T40	2
valid_sources[0x2e]	510	1		T38	11		T40	2		T233	3
valid_sources[0x2f]	478	1		T38	6		T11	1		T16	39
valid_sources[0x30]	376	1		T38	3		T40	4		T233	4
valid_sources[0x31]	377	1		T38	2		T70	1		T124	1
valid_sources[0x32]	854	1		T38	2		T40	5		T124	2
valid_sources[0x33]	460	1		T38	3		T40	5		T126	1
valid_sources[0x34]	629	1		T38	3		T40	2		T126	2
valid_sources[0x35]	308	1		T38	1		T40	1		T233	5
valid_sources[0x36]	636	1		T38	1		T77	1		T111	1
valid_sources[0x37]	635	1		T38	5		T40	1		T177	3
valid_sources[0x38]	362	1		T38	5		T40	11		T233	1
valid_sources[0x39]	419	1		T38	3		T70	1		T14	2
valid_sources[0x3a]	407	1		T38	3		T40	6		T32	2
valid_sources[0x3b]	541	1		T38	1		T36	1		T40	4
valid_sources[0x3c]	418	1		T38	2		T77	1		T40	3
valid_sources[0x3d]	427	1		T38	5		T40	4		T68	1
valid_sources[0x3e]	445	1		T38	5		T40	4		T233	3
valid_sources[0x3f]	595	1		T38	3		T11	1		T40	2
valid_sources[0x40]	392	1		T38	7		T40	2		T236	6
valid_sources[0x41]	569	1		T38	7		T70	1		T29	1
valid_sources[0x42]	407	1		T17	9		T9	1		T38	6
valid_sources[0x43]	1113	1		T38	1		T237	3		T40	4
valid_sources[0x44]	667	1		T38	2		T11	2		T124	1
valid_sources[0x45]	436	1		T38	3		T40	2		T69	1
valid_sources[0x46]	325	1		T38	1		T40	1		T32	1
valid_sources[0x47]	425	1		T38	1		T40	2		T108	1
valid_sources[0x48]	509	1		T3	20		T38	1		T40	1
valid_sources[0x49]	481	1		T38	3		T37	12		T40	5
valid_sources[0x4a]	384	1		T38	3		T11	1		T29	1
valid_sources[0x4b]	376	1		T38	2		T14	1		T40	3
valid_sources[0x4c]	522	1		T31	1		T40	1		T233	1
valid_sources[0x4d]	451	1		T38	1		T11	1		T14	2
valid_sources[0x4e]	314	1		T8	1		T34	8		T40	1
valid_sources[0x4f]	598	1		T38	2		T238	1		T40	2
valid_sources[0x50]	387	1		T38	7		T119	2		T233	2
valid_sources[0x51]	393	1		T38	2		T40	2		T239	8
valid_sources[0x52]	1774	1		T38	7		T36	2		T124	3
valid_sources[0x53]	399	1		T38	1		T14	1		T40	1
valid_sources[0x54]	708	1		T38	9		T237	1		T40	2
valid_sources[0x55]	548	1		T38	6		T238	1		T40	4
valid_sources[0x56]	899	1		T8	2		T38	9		T40	3
valid_sources[0x57]	550	1		T38	7		T20	9		T77	1
valid_sources[0x58]	326	1		T14	1		T40	1		T233	3
valid_sources[0x59]	358	1		T38	7		T40	2		T233	3
valid_sources[0x5a]	484	1		T38	5		T35	3		T40	4
valid_sources[0x5b]	346	1		T38	1		T14	1		T111	1
valid_sources[0x5c]	573	1		T38	2		T77	1		T40	1
valid_sources[0x5d]	718	1		T38	4		T71	3		T40	2
valid_sources[0x5e]	1470	1		T40	2		T233	6		T173	4
valid_sources[0x5f]	384	1		T38	3		T40	1		T240	1
valid_sources[0x60]	396	1		T38	4		T40	3		T241	1
valid_sources[0x61]	421	1		T38	2		T40	1		T33	1
valid_sources[0x62]	405	1		T242	1		T233	6		T243	3
valid_sources[0x63]	338	1		T38	2		T10	1		T14	2
valid_sources[0x64]	565	1		T38	4		T10	1		T77	1
valid_sources[0x65]	423	1		T38	3		T14	1		T77	1
valid_sources[0x66]	471	1		T38	2		T67	1		T233	5
valid_sources[0x67]	513	1		T38	2		T14	1		T40	4
valid_sources[0x68]	483	1		T38	2		T40	3		T233	2
valid_sources[0x69]	492	1		T38	1		T40	3		T177	4
valid_sources[0x6a]	523	1		T38	5		T40	1		T124	1
valid_sources[0x6b]	1697	1		T38	4		T13	3		T40	1
valid_sources[0x6c]	449	1		T38	1		T40	1		T112	2
valid_sources[0x6d]	478	1		T7	8		T38	1		T40	2
valid_sources[0x6e]	393	1		T40	5		T233	5		T173	3
valid_sources[0x6f]	611	1		T38	8		T40	2		T233	10
valid_sources[0x70]	707	1		T38	4		T14	1		T40	1
valid_sources[0x71]	629	1		T38	1		T11	3		T40	4
valid_sources[0x72]	477	1		T40	1		T69	2		T233	3
valid_sources[0x73]	369	1		T38	3		T40	2		T233	2
valid_sources[0x74]	1110	1		T38	4		T233	5		T173	1
valid_sources[0x75]	577	1		T4	3		T38	1		T24	2
valid_sources[0x76]	528	1		T38	3		T21	12		T40	5
valid_sources[0x77]	591	1		T38	3		T14	1		T40	3
valid_sources[0x78]	656	1		T38	1		T14	1		T40	6
valid_sources[0x79]	445	1		T4	4		T14	1		T24	1
valid_sources[0x7a]	504	1		T38	3		T25	5		T40	1
valid_sources[0x7b]	557	1		T38	1		T71	1		T40	1
valid_sources[0x7c]	521	1		T38	1		T14	1		T40	4
valid_sources[0x7d]	455	1		T40	5		T67	1		T233	3
valid_sources[0x7e]	486	1		T38	3		T40	5		T124	1
valid_sources[0x7f]	305	1		T38	2		T14	2		T40	4
valid_sources[0x80]	484	1		T38	3		T77	1		T40	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26219

1

T1

2

T2

3

T3

2

values[0x0]

all_enables

biggest_size

23759

1

T1

3

T2

3

T3

3

values[0x1]

all_enables

biggest_size

19022

1

T1

2

T2

4

T3

6