Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.67	91.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	91.67	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.67	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	2	14	87.50

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	2	14	87.50	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	79844	1		T1	3		T2	12		T3	9
full_word	69869	1		T1	7		T2	10		T3	11

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	149573	1		T1	10		T2	22		T3	20
auto[TlIntgErrCmd]	35	1		T43	2		T74	5		T158	4
auto[TlIntgErrData]	62	1		T42	7		T43	2		T74	10
auto[TlIntgErrBoth]	43	1		T42	3		T43	6		T74	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	65038	1		T1	3		T2	8		T3	7
auto[1]	84675	1		T1	7		T2	14		T3	13

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	38594	1		T1	1		T2	5		T3	5
auto[TlIntgErrNone]	partial	auto[1]	41120	1		T1	2		T2	7		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	26380	1		T1	2		T2	3		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	43479	1		T1	5		T2	7		T3	9
auto[TlIntgErrCmd]	partial	auto[0]	12	1		T43	2		T74	1		T158	1
auto[TlIntgErrCmd]	partial	auto[1]	22	1		T74	4		T158	3		T208	3
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T209	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	29	1		T42	2		T43	1		T74	6
auto[TlIntgErrData]	partial	auto[1]	27	1		T42	3		T43	1		T74	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T42	2		T208	1		T210	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T74	1		T211	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	19	1		T42	1		T43	1		T74	1
auto[TlIntgErrBoth]	partial	auto[1]	21	1		T42	2		T43	3		T74	4
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T43	2		T211	1		-	-