Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.85	96.45	63.89	93.93		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	211709320	10617	0	0
ep_in_enable_rd_A	211709320	1348	0	0
ep_out_enable_rd_A	211709320	1309	0	0
in_iso_rd_A	211709320	1381	0	0
intr_enable_rd_A	211709320	1879	0	0
out_iso_rd_A	211709320	1472	0	0
phy_config_rd_A	211709320	847	0	0
phy_pins_drive_rd_A	211709320	1219	0	0
rxenable_setup_rd_A	211709320	1401	0	0
set_nak_out_rd_A	211709320	1050	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	10617	0	0
T41	12391	710	0	0
T43	8726	2	0	0
T74	23897	3	0	0
T75	2357	7	0	0
T151	7024	527	0	0
T152	3650	4	0	0
T153	4015	614	0	0
T154	6944	564	0	0
T155	3799	25	0	0
T158	12354	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	1348	0	0
T41	12391	3	0	0
T42	23003	268	0	0
T48	8063	30	0	0
T152	3650	4	0	0
T157	6771	55	0	0
T160	18603	148	0	0
T161	2544	29	0	0
T165	3343	7	0	0
T203	4090	53	0	0
T205	3815	19	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	1309	0	0
T42	23003	174	0	0
T48	8063	22	0	0
T152	3650	14	0	0
T157	6771	16	0	0
T160	18603	121	0	0
T161	2544	6	0	0
T165	3343	79	0	0
T203	4090	48	0	0
T205	3815	29	0	0
T206	7704	55	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	1381	0	0
T41	12391	2	0	0
T42	23003	219	0	0
T48	8063	54	0	0
T152	3650	16	0	0
T157	6771	10	0	0
T160	18603	178	0	0
T161	2544	35	0	0
T165	3343	88	0	0
T203	4090	48	0	0
T205	3815	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	1879	0	0
T42	23003	379	0	0
T48	8063	35	0	0
T152	3650	3	0	0
T157	6771	81	0	0
T160	18603	136	0	0
T161	2544	68	0	0
T165	3343	150	0	0
T203	4090	71	0	0
T205	3815	4	0	0
T206	7704	29	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	1472	0	0
T41	12391	4	0	0
T42	23003	386	0	0
T48	8063	40	0	0
T152	3650	26	0	0
T157	6771	46	0	0
T160	18603	155	0	0
T165	3343	94	0	0
T203	4090	57	0	0
T205	3815	54	0	0
T206	7704	30	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	847	0	0
T42	23003	162	0	0
T48	8063	47	0	0
T152	3650	3	0	0
T157	6771	9	0	0
T160	18603	142	0	0
T165	3343	9	0	0
T203	4090	17	0	0
T205	3815	28	0	0
T206	7704	53	0	0
T207	3279	12	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	1219	0	0
T42	23003	294	0	0
T48	8063	12	0	0
T152	3650	45	0	0
T157	6771	38	0	0
T160	18603	147	0	0
T161	2544	1	0	0
T165	3343	38	0	0
T203	4090	9	0	0
T205	3815	19	0	0
T206	7704	64	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	1401	0	0
T42	23003	305	0	0
T48	8063	69	0	0
T152	3650	2	0	0
T157	6771	29	0	0
T160	18603	160	0	0
T161	2544	26	0	0
T165	3343	36	0	0
T203	4090	65	0	0
T205	3815	19	0	0
T206	7704	34	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	1050	0	0
T42	23003	232	0	0
T48	8063	34	0	0
T152	3650	8	0	0
T157	6771	10	0	0
T160	18603	122	0	0
T161	2544	38	0	0
T165	3343	1	0	0
T203	4090	9	0	0
T205	3815	8	0	0
T206	7704	32	0	0