Unified Coverage Report :: Module :: usbdev_reg_top

Module : usbdev_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57	99.72	98.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.57	99.72	98.57			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57	99.72	98.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.91	97.90	96.86	100.00		97.72	87.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.85	96.45	63.89	93.93		85.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_avoutbuffer	100.00	100.00	100.00			100.00
u_avoutbuffer0_qe	100.00	100.00				100.00
u_avsetupbuffer	100.00	100.00	100.00			100.00
u_avsetupbuffer0_qe	100.00	100.00				100.00
u_chk	100.00	100.00		100.00			100.00
u_configin_0_buffer_0	100.00	100.00	100.00			100.00
u_configin_0_pend_0	97.22	100.00	91.67			100.00
u_configin_0_rdy_0	100.00	100.00	100.00			100.00
u_configin_0_size_0	100.00	100.00	100.00			100.00
u_configin_10_buffer_10	100.00	100.00	100.00			100.00
u_configin_10_pend_10	97.22	100.00	91.67			100.00
u_configin_10_rdy_10	100.00	100.00	100.00			100.00
u_configin_10_size_10	100.00	100.00	100.00			100.00
u_configin_11_buffer_11	100.00	100.00	100.00			100.00
u_configin_11_pend_11	97.22	100.00	91.67			100.00
u_configin_11_rdy_11	100.00	100.00	100.00			100.00
u_configin_11_size_11	100.00	100.00	100.00			100.00
u_configin_1_buffer_1	100.00	100.00	100.00			100.00
u_configin_1_pend_1	97.22	100.00	91.67			100.00
u_configin_1_rdy_1	100.00	100.00	100.00			100.00
u_configin_1_size_1	100.00	100.00	100.00			100.00
u_configin_2_buffer_2	100.00	100.00	100.00			100.00
u_configin_2_pend_2	97.22	100.00	91.67			100.00
u_configin_2_rdy_2	100.00	100.00	100.00			100.00
u_configin_2_size_2	100.00	100.00	100.00			100.00
u_configin_3_buffer_3	100.00	100.00	100.00			100.00
u_configin_3_pend_3	97.22	100.00	91.67			100.00
u_configin_3_rdy_3	100.00	100.00	100.00			100.00
u_configin_3_size_3	100.00	100.00	100.00			100.00
u_configin_4_buffer_4	100.00	100.00	100.00			100.00
u_configin_4_pend_4	94.44	100.00	83.33			100.00
u_configin_4_rdy_4	100.00	100.00	100.00			100.00
u_configin_4_size_4	100.00	100.00	100.00			100.00
u_configin_5_buffer_5	100.00	100.00	100.00			100.00
u_configin_5_pend_5	97.22	100.00	91.67			100.00
u_configin_5_rdy_5	100.00	100.00	100.00			100.00
u_configin_5_size_5	100.00	100.00	100.00			100.00
u_configin_6_buffer_6	100.00	100.00	100.00			100.00
u_configin_6_pend_6	97.22	100.00	91.67			100.00
u_configin_6_rdy_6	100.00	100.00	100.00			100.00
u_configin_6_size_6	100.00	100.00	100.00			100.00
u_configin_7_buffer_7	100.00	100.00	100.00			100.00
u_configin_7_pend_7	97.22	100.00	91.67			100.00
u_configin_7_rdy_7	100.00	100.00	100.00			100.00
u_configin_7_size_7	100.00	100.00	100.00			100.00
u_configin_8_buffer_8	100.00	100.00	100.00			100.00
u_configin_8_pend_8	97.22	100.00	91.67			100.00
u_configin_8_rdy_8	100.00	100.00	100.00			100.00
u_configin_8_size_8	100.00	100.00	100.00			100.00
u_configin_9_buffer_9	100.00	100.00	100.00			100.00
u_configin_9_pend_9	97.22	100.00	91.67			100.00
u_configin_9_rdy_9	100.00	100.00	100.00			100.00
u_configin_9_size_9	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_in_enable_enable_9	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_0	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_1	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_10	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_11	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_2	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_3	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_4	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_5	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_6	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_7	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_8	100.00	100.00	100.00			100.00
u_ep_out_enable_enable_9	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_avout_rst	100.00	100.00	100.00			100.00
u_fifo_ctrl_avsetup_rst	100.00	100.00	100.00			100.00
u_fifo_ctrl_rx_rst	100.00	100.00	100.00			100.00
u_in_data_toggle_mask	60.00	60.00
u_in_data_toggle_status	100.00	100.00
u_in_iso_iso_0	100.00	100.00	100.00			100.00
u_in_iso_iso_1	100.00	100.00	100.00			100.00
u_in_iso_iso_10	100.00	100.00	100.00			100.00
u_in_iso_iso_11	100.00	100.00	100.00			100.00
u_in_iso_iso_2	100.00	100.00	100.00			100.00
u_in_iso_iso_3	100.00	100.00	100.00			100.00
u_in_iso_iso_4	100.00	100.00	100.00			100.00
u_in_iso_iso_5	100.00	100.00	100.00			100.00
u_in_iso_iso_6	100.00	100.00	100.00			100.00
u_in_iso_iso_7	100.00	100.00	100.00			100.00
u_in_iso_iso_8	100.00	100.00	100.00			100.00
u_in_iso_iso_9	100.00	100.00	100.00			100.00
u_in_sent_sent_0	100.00	100.00	100.00			100.00
u_in_sent_sent_1	100.00	100.00	100.00			100.00
u_in_sent_sent_10	100.00	100.00	100.00			100.00
u_in_sent_sent_11	100.00	100.00	100.00			100.00
u_in_sent_sent_2	100.00	100.00	100.00			100.00
u_in_sent_sent_3	100.00	100.00	100.00			100.00
u_in_sent_sent_4	100.00	100.00	100.00			100.00
u_in_sent_sent_5	100.00	100.00	100.00			100.00
u_in_sent_sent_6	100.00	100.00	100.00			100.00
u_in_sent_sent_7	100.00	100.00	100.00			100.00
u_in_sent_sent_8	100.00	100.00	100.00			100.00
u_in_sent_sent_9	100.00	100.00	100.00			100.00
u_in_stall_endpoint_0	100.00	100.00	100.00			100.00
u_in_stall_endpoint_1	100.00	100.00	100.00			100.00
u_in_stall_endpoint_10	100.00	100.00	100.00			100.00
u_in_stall_endpoint_11	100.00	100.00	100.00			100.00
u_in_stall_endpoint_2	100.00	100.00	100.00			100.00
u_in_stall_endpoint_3	100.00	100.00	100.00			100.00
u_in_stall_endpoint_4	100.00	100.00	100.00			100.00
u_in_stall_endpoint_5	100.00	100.00	100.00			100.00
u_in_stall_endpoint_6	100.00	100.00	100.00			100.00
u_in_stall_endpoint_7	100.00	100.00	100.00			100.00
u_in_stall_endpoint_8	100.00	100.00	100.00			100.00
u_in_stall_endpoint_9	100.00	100.00	100.00			100.00
u_intr_enable_av_out_empty	100.00	100.00	100.00			100.00
u_intr_enable_av_overflow	100.00	100.00	100.00			100.00
u_intr_enable_av_setup_empty	100.00	100.00	100.00			100.00
u_intr_enable_disconnected	100.00	100.00	100.00			100.00
u_intr_enable_frame	100.00	100.00	100.00			100.00
u_intr_enable_host_lost	100.00	100.00	100.00			100.00
u_intr_enable_link_in_err	100.00	100.00	100.00			100.00
u_intr_enable_link_out_err	100.00	100.00	100.00			100.00
u_intr_enable_link_reset	100.00	100.00	100.00			100.00
u_intr_enable_link_resume	100.00	100.00	100.00			100.00
u_intr_enable_link_suspend	100.00	100.00	100.00			100.00
u_intr_enable_pkt_received	100.00	100.00	100.00			100.00
u_intr_enable_pkt_sent	100.00	100.00	100.00			100.00
u_intr_enable_powered	100.00	100.00	100.00			100.00
u_intr_enable_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_full	100.00	100.00	100.00			100.00
u_intr_enable_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_state_av_out_empty	62.59	77.78	50.00			60.00
u_intr_state_av_overflow	100.00	100.00	100.00			100.00
u_intr_state_av_setup_empty	62.59	77.78	50.00			60.00
u_intr_state_disconnected	100.00	100.00	100.00			100.00
u_intr_state_frame	100.00	100.00	100.00			100.00
u_intr_state_host_lost	100.00	100.00	100.00			100.00
u_intr_state_link_in_err	100.00	100.00	100.00			100.00
u_intr_state_link_out_err	100.00	100.00	100.00			100.00
u_intr_state_link_reset	100.00	100.00	100.00			100.00
u_intr_state_link_resume	100.00	100.00	100.00			100.00
u_intr_state_link_suspend	100.00	100.00	100.00			100.00
u_intr_state_pkt_received	62.59	77.78	50.00			60.00
u_intr_state_pkt_sent	62.59	77.78	50.00			60.00
u_intr_state_powered	100.00	100.00	100.00			100.00
u_intr_state_rx_bitstuff_err	100.00	100.00	100.00			100.00
u_intr_state_rx_crc_err	100.00	100.00	100.00			100.00
u_intr_state_rx_full	62.59	77.78	50.00			60.00
u_intr_state_rx_pid_err	100.00	100.00	100.00			100.00
u_intr_test_av_out_empty	100.00	100.00
u_intr_test_av_overflow	100.00	100.00
u_intr_test_av_setup_empty	100.00	100.00
u_intr_test_disconnected	100.00	100.00
u_intr_test_frame	100.00	100.00
u_intr_test_host_lost	100.00	100.00
u_intr_test_link_in_err	100.00	100.00
u_intr_test_link_out_err	100.00	100.00
u_intr_test_link_reset	100.00	100.00
u_intr_test_link_resume	100.00	100.00
u_intr_test_link_suspend	100.00	100.00
u_intr_test_pkt_received	100.00	100.00
u_intr_test_pkt_sent	100.00	100.00
u_intr_test_powered	100.00	100.00
u_intr_test_rx_bitstuff_err	100.00	100.00
u_intr_test_rx_crc_err	100.00	100.00
u_intr_test_rx_full	100.00	100.00
u_intr_test_rx_pid_err	100.00	100.00
u_out_data_toggle_mask	60.00	60.00
u_out_data_toggle_status	100.00	100.00
u_out_iso_iso_0	100.00	100.00	100.00			100.00
u_out_iso_iso_1	100.00	100.00	100.00			100.00
u_out_iso_iso_10	100.00	100.00	100.00			100.00
u_out_iso_iso_11	100.00	100.00	100.00			100.00
u_out_iso_iso_2	100.00	100.00	100.00			100.00
u_out_iso_iso_3	100.00	100.00	100.00			100.00
u_out_iso_iso_4	100.00	100.00	100.00			100.00
u_out_iso_iso_5	100.00	100.00	100.00			100.00
u_out_iso_iso_6	100.00	100.00	100.00			100.00
u_out_iso_iso_7	100.00	100.00	100.00			100.00
u_out_iso_iso_8	100.00	100.00	100.00			100.00
u_out_iso_iso_9	100.00	100.00	100.00			100.00
u_out_stall_endpoint_0	100.00	100.00	100.00			100.00
u_out_stall_endpoint_1	100.00	100.00	100.00			100.00
u_out_stall_endpoint_10	100.00	100.00	100.00			100.00
u_out_stall_endpoint_11	100.00	100.00	100.00			100.00
u_out_stall_endpoint_2	100.00	100.00	100.00			100.00
u_out_stall_endpoint_3	100.00	100.00	100.00			100.00
u_out_stall_endpoint_4	100.00	100.00	100.00			100.00
u_out_stall_endpoint_5	100.00	100.00	100.00			100.00
u_out_stall_endpoint_6	100.00	100.00	100.00			100.00
u_out_stall_endpoint_7	100.00	100.00	100.00			100.00
u_out_stall_endpoint_8	100.00	100.00	100.00			100.00
u_out_stall_endpoint_9	100.00	100.00	100.00			100.00
u_phy_config_eop_single_bit	100.00	100.00	100.00			100.00
u_phy_config_pinflip	100.00	100.00	100.00			100.00
u_phy_config_tx_osc_test_mode	100.00	100.00	100.00			100.00
u_phy_config_tx_use_d_se0	100.00	100.00	100.00			100.00
u_phy_config_usb_ref_disable	100.00	100.00	100.00			100.00
u_phy_config_use_diff_rcvr	100.00	100.00	100.00			100.00
u_phy_pins_drive_d_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dn_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_dp_pullup_en_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_en	100.00	100.00	100.00			100.00
u_phy_pins_drive_oe_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_rx_enable_o	100.00	100.00	100.00			100.00
u_phy_pins_drive_se0_o	100.00	100.00	100.00			100.00
u_phy_pins_sense_pwr_sense	66.67	66.67
u_phy_pins_sense_rx_d_i	66.67	66.67
u_phy_pins_sense_rx_dn_i	66.67	66.67
u_phy_pins_sense_rx_dp_i	66.67	66.67
u_phy_pins_sense_tx_d_o	66.67	66.67
u_phy_pins_sense_tx_dn_o	66.67	66.67
u_phy_pins_sense_tx_dp_o	66.67	66.67
u_phy_pins_sense_tx_oe_o	66.67	66.67
u_phy_pins_sense_tx_se0_o	66.67	66.67
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_rxenable_out_out_0	100.00	100.00	100.00			100.00
u_rxenable_out_out_1	100.00	100.00	100.00			100.00
u_rxenable_out_out_10	100.00	100.00	100.00			100.00
u_rxenable_out_out_11	100.00	100.00	100.00			100.00
u_rxenable_out_out_2	100.00	100.00	100.00			100.00
u_rxenable_out_out_3	100.00	100.00	100.00			100.00
u_rxenable_out_out_4	100.00	100.00	100.00			100.00
u_rxenable_out_out_5	100.00	100.00	100.00			100.00
u_rxenable_out_out_6	100.00	100.00	100.00			100.00
u_rxenable_out_out_7	100.00	100.00	100.00			100.00
u_rxenable_out_out_8	100.00	100.00	100.00			100.00
u_rxenable_out_out_9	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_0	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_1	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_10	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_11	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_2	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_3	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_4	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_5	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_6	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_7	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_8	100.00	100.00	100.00			100.00
u_rxenable_setup_setup_9	100.00	100.00	100.00			100.00
u_rxfifo_buffer	100.00	100.00
u_rxfifo_ep	100.00	100.00
u_rxfifo_setup	100.00	100.00
u_rxfifo_size	100.00	100.00
u_set_nak_out_enable_0	100.00	100.00	100.00			100.00
u_set_nak_out_enable_1	100.00	100.00	100.00			100.00
u_set_nak_out_enable_10	100.00	100.00	100.00			100.00
u_set_nak_out_enable_11	100.00	100.00	100.00			100.00
u_set_nak_out_enable_2	100.00	100.00	100.00			100.00
u_set_nak_out_enable_3	100.00	100.00	100.00			100.00
u_set_nak_out_enable_4	100.00	100.00	100.00			100.00
u_set_nak_out_enable_5	100.00	100.00	100.00			100.00
u_set_nak_out_enable_6	100.00	100.00	100.00			100.00
u_set_nak_out_enable_7	100.00	100.00	100.00			100.00
u_set_nak_out_enable_8	100.00	100.00	100.00			100.00
u_set_nak_out_enable_9	100.00	100.00	100.00			100.00
u_socket	98.24	98.75	98.21			96.00	100.00
u_usbctrl0_qe	100.00	100.00				100.00
u_usbctrl_device_address	96.30	100.00	88.89			100.00
u_usbctrl_enable	100.00	100.00	100.00			100.00
u_usbctrl_resume_link_active	100.00	100.00	100.00			100.00
u_usbstat_av_out_depth	100.00	100.00
u_usbstat_av_out_full	100.00	100.00
u_usbstat_av_setup_depth	100.00	100.00
u_usbstat_av_setup_full	100.00	100.00
u_usbstat_frame	100.00	100.00
u_usbstat_host_lost	100.00	100.00
u_usbstat_link_state	100.00	100.00
u_usbstat_rx_depth	100.00	100.00
u_usbstat_rx_empty	100.00	100.00
u_usbstat_sense	100.00	100.00
u_wake_control_cdc	98.13	96.08	96.43			100.00	100.00
u_wake_control_suspend_req	100.00	100.00
u_wake_control_wake_ack	100.00	100.00
u_wake_events_bus_reset	58.89	66.67	50.00			60.00
u_wake_events_cdc	45.74	76.56	25.00			61.40	20.00
u_wake_events_disconnected	58.89	66.67	50.00			60.00
u_wake_events_module_active	58.89	66.67	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
TOTAL		712	710	99.72
ALWAYS	75	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
ALWAYS	132	3	3	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
ALWAYS	721	1	0	0.00
CONT_ASSIGN	748	1	1	100.00
ALWAYS	762	8	8	100.00
CONT_ASSIGN	1777	1	1	100.00
CONT_ASSIGN	1792	1	1	100.00
CONT_ASSIGN	1808	1	1	100.00
CONT_ASSIGN	1824	1	1	100.00
CONT_ASSIGN	1840	1	1	100.00
CONT_ASSIGN	1856	1	1	100.00
CONT_ASSIGN	1872	1	1	100.00
CONT_ASSIGN	1888	1	1	100.00
CONT_ASSIGN	1904	1	1	100.00
CONT_ASSIGN	1920	1	1	100.00
CONT_ASSIGN	1936	1	1	100.00
CONT_ASSIGN	1952	1	1	100.00
CONT_ASSIGN	1968	1	1	100.00
CONT_ASSIGN	1984	1	1	100.00
CONT_ASSIGN	2000	1	1	100.00
CONT_ASSIGN	2016	1	1	100.00
CONT_ASSIGN	2032	1	1	100.00
CONT_ASSIGN	2048	1	1	100.00
CONT_ASSIGN	2064	1	1	100.00
CONT_ASSIGN	2070	1	1	100.00
CONT_ASSIGN	2084	1	1	100.00
CONT_ASSIGN	2152	1	1	100.00
CONT_ASSIGN	3025	1	1	100.00
CONT_ASSIGN	3065	1	1	100.00
CONT_ASSIGN	7081	1	1	100.00
CONT_ASSIGN	7096	1	1	100.00
CONT_ASSIGN	7112	1	1	100.00
CONT_ASSIGN	7118	1	1	100.00
CONT_ASSIGN	7133	1	1	100.00
CONT_ASSIGN	7149	1	1	100.00
CONT_ASSIGN	7701	1	1	100.00
CONT_ASSIGN	7716	1	1	100.00
CONT_ASSIGN	7732	1	1	100.00
CONT_ASSIGN	7737	1	0	0.00
CONT_ASSIGN	7858	1	1	100.00
CONT_ASSIGN	7886	1	1	100.00
CONT_ASSIGN	7914	1	1	100.00
ALWAYS	7920	40	40	100.00
CONT_ASSIGN	7962	1	1	100.00
ALWAYS	7966	1	1	100.00
CONT_ASSIGN	8009	1	1	100.00
CONT_ASSIGN	8011	1	1	100.00
CONT_ASSIGN	8013	1	1	100.00
CONT_ASSIGN	8015	1	1	100.00
CONT_ASSIGN	8017	1	1	100.00
CONT_ASSIGN	8019	1	1	100.00
CONT_ASSIGN	8021	1	1	100.00
CONT_ASSIGN	8023	1	1	100.00
CONT_ASSIGN	8025	1	1	100.00
CONT_ASSIGN	8027	1	1	100.00
CONT_ASSIGN	8029	1	1	100.00
CONT_ASSIGN	8031	1	1	100.00
CONT_ASSIGN	8033	1	1	100.00
CONT_ASSIGN	8035	1	1	100.00
CONT_ASSIGN	8036	1	1	100.00
CONT_ASSIGN	8038	1	1	100.00
CONT_ASSIGN	8040	1	1	100.00
CONT_ASSIGN	8042	1	1	100.00
CONT_ASSIGN	8044	1	1	100.00
CONT_ASSIGN	8046	1	1	100.00
CONT_ASSIGN	8048	1	1	100.00
CONT_ASSIGN	8050	1	1	100.00
CONT_ASSIGN	8052	1	1	100.00
CONT_ASSIGN	8054	1	1	100.00
CONT_ASSIGN	8056	1	1	100.00
CONT_ASSIGN	8058	1	1	100.00
CONT_ASSIGN	8060	1	1	100.00
CONT_ASSIGN	8062	1	1	100.00
CONT_ASSIGN	8064	1	1	100.00
CONT_ASSIGN	8066	1	1	100.00
CONT_ASSIGN	8068	1	1	100.00
CONT_ASSIGN	8070	1	1	100.00
CONT_ASSIGN	8072	1	1	100.00
CONT_ASSIGN	8073	1	1	100.00
CONT_ASSIGN	8075	1	1	100.00
CONT_ASSIGN	8077	1	1	100.00
CONT_ASSIGN	8079	1	1	100.00
CONT_ASSIGN	8081	1	1	100.00
CONT_ASSIGN	8083	1	1	100.00
CONT_ASSIGN	8085	1	1	100.00
CONT_ASSIGN	8087	1	1	100.00
CONT_ASSIGN	8089	1	1	100.00
CONT_ASSIGN	8091	1	1	100.00
CONT_ASSIGN	8093	1	1	100.00
CONT_ASSIGN	8095	1	1	100.00
CONT_ASSIGN	8097	1	1	100.00
CONT_ASSIGN	8099	1	1	100.00
CONT_ASSIGN	8101	1	1	100.00
CONT_ASSIGN	8103	1	1	100.00
CONT_ASSIGN	8105	1	1	100.00
CONT_ASSIGN	8107	1	1	100.00
CONT_ASSIGN	8109	1	1	100.00
CONT_ASSIGN	8110	1	1	100.00
CONT_ASSIGN	8112	1	1	100.00
CONT_ASSIGN	8113	1	1	100.00
CONT_ASSIGN	8115	1	1	100.00
CONT_ASSIGN	8117	1	1	100.00
CONT_ASSIGN	8119	1	1	100.00
CONT_ASSIGN	8120	1	1	100.00
CONT_ASSIGN	8122	1	1	100.00
CONT_ASSIGN	8124	1	1	100.00
CONT_ASSIGN	8126	1	1	100.00
CONT_ASSIGN	8128	1	1	100.00
CONT_ASSIGN	8130	1	1	100.00
CONT_ASSIGN	8132	1	1	100.00
CONT_ASSIGN	8134	1	1	100.00
CONT_ASSIGN	8136	1	1	100.00
CONT_ASSIGN	8138	1	1	100.00
CONT_ASSIGN	8140	1	1	100.00
CONT_ASSIGN	8142	1	1	100.00
CONT_ASSIGN	8144	1	1	100.00
CONT_ASSIGN	8145	1	1	100.00
CONT_ASSIGN	8147	1	1	100.00
CONT_ASSIGN	8149	1	1	100.00
CONT_ASSIGN	8151	1	1	100.00
CONT_ASSIGN	8153	1	1	100.00
CONT_ASSIGN	8155	1	1	100.00
CONT_ASSIGN	8157	1	1	100.00
CONT_ASSIGN	8159	1	1	100.00
CONT_ASSIGN	8161	1	1	100.00
CONT_ASSIGN	8163	1	1	100.00
CONT_ASSIGN	8165	1	1	100.00
CONT_ASSIGN	8167	1	1	100.00
CONT_ASSIGN	8169	1	1	100.00
CONT_ASSIGN	8170	1	1	100.00
CONT_ASSIGN	8171	1	1	100.00
CONT_ASSIGN	8173	1	1	100.00
CONT_ASSIGN	8174	1	1	100.00
CONT_ASSIGN	8176	1	1	100.00
CONT_ASSIGN	8177	1	1	100.00
CONT_ASSIGN	8178	1	1	100.00
CONT_ASSIGN	8180	1	1	100.00
CONT_ASSIGN	8182	1	1	100.00
CONT_ASSIGN	8184	1	1	100.00
CONT_ASSIGN	8186	1	1	100.00
CONT_ASSIGN	8188	1	1	100.00
CONT_ASSIGN	8190	1	1	100.00
CONT_ASSIGN	8192	1	1	100.00
CONT_ASSIGN	8194	1	1	100.00
CONT_ASSIGN	8196	1	1	100.00
CONT_ASSIGN	8198	1	1	100.00
CONT_ASSIGN	8200	1	1	100.00
CONT_ASSIGN	8202	1	1	100.00
CONT_ASSIGN	8203	1	1	100.00
CONT_ASSIGN	8205	1	1	100.00
CONT_ASSIGN	8207	1	1	100.00
CONT_ASSIGN	8209	1	1	100.00
CONT_ASSIGN	8211	1	1	100.00
CONT_ASSIGN	8213	1	1	100.00
CONT_ASSIGN	8215	1	1	100.00
CONT_ASSIGN	8217	1	1	100.00
CONT_ASSIGN	8219	1	1	100.00
CONT_ASSIGN	8221	1	1	100.00
CONT_ASSIGN	8223	1	1	100.00
CONT_ASSIGN	8225	1	1	100.00
CONT_ASSIGN	8227	1	1	100.00
CONT_ASSIGN	8228	1	1	100.00
CONT_ASSIGN	8230	1	1	100.00
CONT_ASSIGN	8232	1	1	100.00
CONT_ASSIGN	8234	1	1	100.00
CONT_ASSIGN	8236	1	1	100.00
CONT_ASSIGN	8238	1	1	100.00
CONT_ASSIGN	8240	1	1	100.00
CONT_ASSIGN	8242	1	1	100.00
CONT_ASSIGN	8244	1	1	100.00
CONT_ASSIGN	8246	1	1	100.00
CONT_ASSIGN	8248	1	1	100.00
CONT_ASSIGN	8250	1	1	100.00
CONT_ASSIGN	8252	1	1	100.00
CONT_ASSIGN	8253	1	1	100.00
CONT_ASSIGN	8255	1	1	100.00
CONT_ASSIGN	8257	1	1	100.00
CONT_ASSIGN	8259	1	1	100.00
CONT_ASSIGN	8261	1	1	100.00
CONT_ASSIGN	8263	1	1	100.00
CONT_ASSIGN	8265	1	1	100.00
CONT_ASSIGN	8267	1	1	100.00
CONT_ASSIGN	8269	1	1	100.00
CONT_ASSIGN	8271	1	1	100.00
CONT_ASSIGN	8273	1	1	100.00
CONT_ASSIGN	8275	1	1	100.00
CONT_ASSIGN	8277	1	1	100.00
CONT_ASSIGN	8278	1	1	100.00
CONT_ASSIGN	8280	1	1	100.00
CONT_ASSIGN	8282	1	1	100.00
CONT_ASSIGN	8284	1	1	100.00
CONT_ASSIGN	8286	1	1	100.00
CONT_ASSIGN	8288	1	1	100.00
CONT_ASSIGN	8290	1	1	100.00
CONT_ASSIGN	8292	1	1	100.00
CONT_ASSIGN	8294	1	1	100.00
CONT_ASSIGN	8296	1	1	100.00
CONT_ASSIGN	8298	1	1	100.00
CONT_ASSIGN	8300	1	1	100.00
CONT_ASSIGN	8302	1	1	100.00
CONT_ASSIGN	8303	1	1	100.00
CONT_ASSIGN	8305	1	1	100.00
CONT_ASSIGN	8307	1	1	100.00
CONT_ASSIGN	8309	1	1	100.00
CONT_ASSIGN	8311	1	1	100.00
CONT_ASSIGN	8313	1	1	100.00
CONT_ASSIGN	8315	1	1	100.00
CONT_ASSIGN	8317	1	1	100.00
CONT_ASSIGN	8319	1	1	100.00
CONT_ASSIGN	8321	1	1	100.00
CONT_ASSIGN	8323	1	1	100.00
CONT_ASSIGN	8325	1	1	100.00
CONT_ASSIGN	8327	1	1	100.00
CONT_ASSIGN	8328	1	1	100.00
CONT_ASSIGN	8330	1	1	100.00
CONT_ASSIGN	8332	1	1	100.00
CONT_ASSIGN	8334	1	1	100.00
CONT_ASSIGN	8336	1	1	100.00
CONT_ASSIGN	8337	1	1	100.00
CONT_ASSIGN	8339	1	1	100.00
CONT_ASSIGN	8341	1	1	100.00
CONT_ASSIGN	8343	1	1	100.00
CONT_ASSIGN	8345	1	1	100.00
CONT_ASSIGN	8346	1	1	100.00
CONT_ASSIGN	8348	1	1	100.00
CONT_ASSIGN	8350	1	1	100.00
CONT_ASSIGN	8352	1	1	100.00
CONT_ASSIGN	8354	1	1	100.00
CONT_ASSIGN	8355	1	1	100.00
CONT_ASSIGN	8357	1	1	100.00
CONT_ASSIGN	8359	1	1	100.00
CONT_ASSIGN	8361	1	1	100.00
CONT_ASSIGN	8363	1	1	100.00
CONT_ASSIGN	8364	1	1	100.00
CONT_ASSIGN	8366	1	1	100.00
CONT_ASSIGN	8368	1	1	100.00
CONT_ASSIGN	8370	1	1	100.00
CONT_ASSIGN	8372	1	1	100.00
CONT_ASSIGN	8373	1	1	100.00
CONT_ASSIGN	8375	1	1	100.00
CONT_ASSIGN	8377	1	1	100.00
CONT_ASSIGN	8379	1	1	100.00
CONT_ASSIGN	8381	1	1	100.00
CONT_ASSIGN	8382	1	1	100.00
CONT_ASSIGN	8384	1	1	100.00
CONT_ASSIGN	8386	1	1	100.00
CONT_ASSIGN	8388	1	1	100.00
CONT_ASSIGN	8390	1	1	100.00
CONT_ASSIGN	8391	1	1	100.00
CONT_ASSIGN	8393	1	1	100.00
CONT_ASSIGN	8395	1	1	100.00
CONT_ASSIGN	8397	1	1	100.00
CONT_ASSIGN	8399	1	1	100.00
CONT_ASSIGN	8400	1	1	100.00
CONT_ASSIGN	8402	1	1	100.00
CONT_ASSIGN	8404	1	1	100.00
CONT_ASSIGN	8406	1	1	100.00
CONT_ASSIGN	8408	1	1	100.00
CONT_ASSIGN	8409	1	1	100.00
CONT_ASSIGN	8411	1	1	100.00
CONT_ASSIGN	8413	1	1	100.00
CONT_ASSIGN	8415	1	1	100.00
CONT_ASSIGN	8417	1	1	100.00
CONT_ASSIGN	8418	1	1	100.00
CONT_ASSIGN	8420	1	1	100.00
CONT_ASSIGN	8422	1	1	100.00
CONT_ASSIGN	8424	1	1	100.00
CONT_ASSIGN	8426	1	1	100.00
CONT_ASSIGN	8427	1	1	100.00
CONT_ASSIGN	8429	1	1	100.00
CONT_ASSIGN	8431	1	1	100.00
CONT_ASSIGN	8433	1	1	100.00
CONT_ASSIGN	8435	1	1	100.00
CONT_ASSIGN	8436	1	1	100.00
CONT_ASSIGN	8438	1	1	100.00
CONT_ASSIGN	8440	1	1	100.00
CONT_ASSIGN	8442	1	1	100.00
CONT_ASSIGN	8444	1	1	100.00
CONT_ASSIGN	8446	1	1	100.00
CONT_ASSIGN	8448	1	1	100.00
CONT_ASSIGN	8450	1	1	100.00
CONT_ASSIGN	8452	1	1	100.00
CONT_ASSIGN	8454	1	1	100.00
CONT_ASSIGN	8456	1	1	100.00
CONT_ASSIGN	8458	1	1	100.00
CONT_ASSIGN	8460	1	1	100.00
CONT_ASSIGN	8461	1	1	100.00
CONT_ASSIGN	8463	1	1	100.00
CONT_ASSIGN	8465	1	1	100.00
CONT_ASSIGN	8467	1	1	100.00
CONT_ASSIGN	8469	1	1	100.00
CONT_ASSIGN	8471	1	1	100.00
CONT_ASSIGN	8473	1	1	100.00
CONT_ASSIGN	8475	1	1	100.00
CONT_ASSIGN	8477	1	1	100.00
CONT_ASSIGN	8479	1	1	100.00
CONT_ASSIGN	8481	1	1	100.00
CONT_ASSIGN	8483	1	1	100.00
CONT_ASSIGN	8485	1	1	100.00
CONT_ASSIGN	8486	1	1	100.00
CONT_ASSIGN	8487	1	1	100.00
CONT_ASSIGN	8489	1	1	100.00
CONT_ASSIGN	8491	1	1	100.00
CONT_ASSIGN	8492	1	1	100.00
CONT_ASSIGN	8493	1	1	100.00
CONT_ASSIGN	8495	1	1	100.00
CONT_ASSIGN	8497	1	1	100.00
CONT_ASSIGN	8498	1	1	100.00
CONT_ASSIGN	8499	1	1	100.00
CONT_ASSIGN	8501	1	1	100.00
CONT_ASSIGN	8503	1	1	100.00
CONT_ASSIGN	8505	1	1	100.00
CONT_ASSIGN	8507	1	1	100.00
CONT_ASSIGN	8509	1	1	100.00
CONT_ASSIGN	8511	1	1	100.00
CONT_ASSIGN	8513	1	1	100.00
CONT_ASSIGN	8515	1	1	100.00
CONT_ASSIGN	8517	1	1	100.00
CONT_ASSIGN	8518	1	1	100.00
CONT_ASSIGN	8520	1	1	100.00
CONT_ASSIGN	8522	1	1	100.00
CONT_ASSIGN	8524	1	1	100.00
CONT_ASSIGN	8526	1	1	100.00
CONT_ASSIGN	8528	1	1	100.00
CONT_ASSIGN	8530	1	1	100.00
CONT_ASSIGN	8531	1	1	100.00
CONT_ASSIGN	8534	1	1	100.00
CONT_ASSIGN	8536	1	1	100.00
CONT_ASSIGN	8538	1	1	100.00
CONT_ASSIGN	8540	1	1	100.00
ALWAYS	8544	40	40	100.00
ALWAYS	8588	277	277	100.00
CONT_ASSIGN	8992	1	1	100.00
ALWAYS	8994	4	4	100.00
CONT_ASSIGN	9015	1	1	100.00
CONT_ASSIGN	9016	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
75	1	1
76	1	1
77	1	1
78	1	1
			MISSING_ELSE
84	1	1
102	1	1
103	1	1
105	1	1
106	1	1
132	1	1
138	1	1
139	1	1
			MISSING_ELSE
169	1	1
170	1	1
721	0	1
748	1	1
762	1	1
763	1	1
764	1	1
765	1	1
766	1	1
767	1	1
768	1	1
769	1	1
1777	1	1
1792	1	1
1808	1	1
1824	1	1
1840	1	1
1856	1	1
1872	1	1
1888	1	1
1904	1	1
1920	1	1
1936	1	1
1952	1	1
1968	1	1
1984	1	1
2000	1	1
2016	1	1
2032	1	1
2048	1	1
2064	1	1
2070	1	1
2084	1	1
2152	1	1
3025	1	1
3065	1	1
7081	1	1
7096	1	1
7112	1	1
7118	1	1
7133	1	1
7149	1	1
7701	1	1
7716	1	1
7732	1	1
7737	0	1
7858	1	1
7886	1	1
7914	1	1
7920	1	1
7921	1	1
7922	1	1
7923	1	1
7924	1	1
7925	1	1
7926	1	1
7927	1	1
7928	1	1
7929	1	1
7930	1	1
7931	1	1
7932	1	1
7933	1	1
7934	1	1
7935	1	1
7936	1	1
7937	1	1
7938	1	1
7939	1	1
7940	1	1
7941	1	1
7942	1	1
7943	1	1
7944	1	1
7945	1	1
7946	1	1
7947	1	1
7948	1	1
7949	1	1
7950	1	1
7951	1	1
7952	1	1
7953	1	1
7954	1	1
7955	1	1
7956	1	1
7957	1	1
7958	1	1
7959	1	1
7962	1	1
7966	1	1
8009	1	1
8011	1	1
8013	1	1
8015	1	1
8017	1	1
8019	1	1
8021	1	1
8023	1	1
8025	1	1
8027	1	1
8029	1	1
8031	1	1
8033	1	1
8035	1	1
8036	1	1
8038	1	1
8040	1	1
8042	1	1
8044	1	1
8046	1	1
8048	1	1
8050	1	1
8052	1	1
8054	1	1
8056	1	1
8058	1	1
8060	1	1
8062	1	1
8064	1	1
8066	1	1
8068	1	1
8070	1	1
8072	1	1
8073	1	1
8075	1	1
8077	1	1
8079	1	1
8081	1	1
8083	1	1
8085	1	1
8087	1	1
8089	1	1
8091	1	1
8093	1	1
8095	1	1
8097	1	1
8099	1	1
8101	1	1
8103	1	1
8105	1	1
8107	1	1
8109	1	1
8110	1	1
8112	1	1
8113	1	1
8115	1	1
8117	1	1
8119	1	1
8120	1	1
8122	1	1
8124	1	1
8126	1	1
8128	1	1
8130	1	1
8132	1	1
8134	1	1
8136	1	1
8138	1	1
8140	1	1
8142	1	1
8144	1	1
8145	1	1
8147	1	1
8149	1	1
8151	1	1
8153	1	1
8155	1	1
8157	1	1
8159	1	1
8161	1	1
8163	1	1
8165	1	1
8167	1	1
8169	1	1
8170	1	1
8171	1	1
8173	1	1
8174	1	1
8176	1	1
8177	1	1
8178	1	1
8180	1	1
8182	1	1
8184	1	1
8186	1	1
8188	1	1
8190	1	1
8192	1	1
8194	1	1
8196	1	1
8198	1	1
8200	1	1
8202	1	1
8203	1	1
8205	1	1
8207	1	1
8209	1	1
8211	1	1
8213	1	1
8215	1	1
8217	1	1
8219	1	1
8221	1	1
8223	1	1
8225	1	1
8227	1	1
8228	1	1
8230	1	1
8232	1	1
8234	1	1
8236	1	1
8238	1	1
8240	1	1
8242	1	1
8244	1	1
8246	1	1
8248	1	1
8250	1	1
8252	1	1
8253	1	1
8255	1	1
8257	1	1
8259	1	1
8261	1	1
8263	1	1
8265	1	1
8267	1	1
8269	1	1
8271	1	1
8273	1	1
8275	1	1
8277	1	1
8278	1	1
8280	1	1
8282	1	1
8284	1	1
8286	1	1
8288	1	1
8290	1	1
8292	1	1
8294	1	1
8296	1	1
8298	1	1
8300	1	1
8302	1	1
8303	1	1
8305	1	1
8307	1	1
8309	1	1
8311	1	1
8313	1	1
8315	1	1
8317	1	1
8319	1	1
8321	1	1
8323	1	1
8325	1	1
8327	1	1
8328	1	1
8330	1	1
8332	1	1
8334	1	1
8336	1	1
8337	1	1
8339	1	1
8341	1	1
8343	1	1
8345	1	1
8346	1	1
8348	1	1
8350	1	1
8352	1	1
8354	1	1
8355	1	1
8357	1	1
8359	1	1
8361	1	1
8363	1	1
8364	1	1
8366	1	1
8368	1	1
8370	1	1
8372	1	1
8373	1	1
8375	1	1
8377	1	1
8379	1	1
8381	1	1
8382	1	1
8384	1	1
8386	1	1
8388	1	1
8390	1	1
8391	1	1
8393	1	1
8395	1	1
8397	1	1
8399	1	1
8400	1	1
8402	1	1
8404	1	1
8406	1	1
8408	1	1
8409	1	1
8411	1	1
8413	1	1
8415	1	1
8417	1	1
8418	1	1
8420	1	1
8422	1	1
8424	1	1
8426	1	1
8427	1	1
8429	1	1
8431	1	1
8433	1	1
8435	1	1
8436	1	1
8438	1	1
8440	1	1
8442	1	1
8444	1	1
8446	1	1
8448	1	1
8450	1	1
8452	1	1
8454	1	1
8456	1	1
8458	1	1
8460	1	1
8461	1	1
8463	1	1
8465	1	1
8467	1	1
8469	1	1
8471	1	1
8473	1	1
8475	1	1
8477	1	1
8479	1	1
8481	1	1
8483	1	1
8485	1	1
8486	1	1
8487	1	1
8489	1	1
8491	1	1
8492	1	1
8493	1	1
8495	1	1
8497	1	1
8498	1	1
8499	1	1
8501	1	1
8503	1	1
8505	1	1
8507	1	1
8509	1	1
8511	1	1
8513	1	1
8515	1	1
8517	1	1
8518	1	1
8520	1	1
8522	1	1
8524	1	1
8526	1	1
8528	1	1
8530	1	1
8531	1	1
8534	1	1
8536	1	1
8538	1	1
8540	1	1
8544	1	1
8545	1	1
8546	1	1
8547	1	1
8548	1	1
8549	1	1
8550	1	1
8551	1	1
8552	1	1
8553	1	1
8554	1	1
8555	1	1
8556	1	1
8557	1	1
8558	1	1
8559	1	1
8560	1	1
8561	1	1
8562	1	1
8563	1	1
8564	1	1
8565	1	1
8566	1	1
8567	1	1
8568	1	1
8569	1	1
8570	1	1
8571	1	1
8572	1	1
8573	1	1
8574	1	1
8575	1	1
8576	1	1
8577	1	1
8578	1	1
8579	1	1
8580	1	1
8581	1	1
8582	1	1
8583	1	1
8588	1	1
8589	1	1
8591	1	1
8592	1	1
8593	1	1
8594	1	1
8595	1	1
8596	1	1
8597	1	1
8598	1	1
8599	1	1
8600	1	1
8601	1	1
8602	1	1
8603	1	1
8604	1	1
8605	1	1
8606	1	1
8607	1	1
8608	1	1
8612	1	1
8613	1	1
8614	1	1
8615	1	1
8616	1	1
8617	1	1
8618	1	1
8619	1	1
8620	1	1
8621	1	1
8622	1	1
8623	1	1
8624	1	1
8625	1	1
8626	1	1
8627	1	1
8628	1	1
8629	1	1
8633	1	1
8634	1	1
8635	1	1
8636	1	1
8637	1	1
8638	1	1
8639	1	1
8640	1	1
8641	1	1
8642	1	1
8643	1	1
8644	1	1
8645	1	1
8646	1	1
8647	1	1
8648	1	1
8649	1	1
8650	1	1
8654	1	1
8658	1	1
8659	1	1
8660	1	1
8664	1	1
8665	1	1
8666	1	1
8667	1	1
8668	1	1
8669	1	1
8670	1	1
8671	1	1
8672	1	1
8673	1	1
8674	1	1
8675	1	1
8679	1	1
8680	1	1
8681	1	1
8682	1	1
8683	1	1
8684	1	1
8685	1	1
8686	1	1
8687	1	1
8688	1	1
8689	1	1
8690	1	1
8694	1	1
8695	1	1
8696	1	1
8697	1	1
8698	1	1
8699	1	1
8700	1	1
8701	1	1
8702	1	1
8703	1	1
8707	1	1
8711	1	1
8715	1	1
8716	1	1
8717	1	1
8718	1	1
8722	1	1
8723	1	1
8724	1	1
8725	1	1
8726	1	1
8727	1	1
8728	1	1
8729	1	1
8730	1	1
8731	1	1
8732	1	1
8733	1	1
8737	1	1
8738	1	1
8739	1	1
8740	1	1
8741	1	1
8742	1	1
8743	1	1
8744	1	1
8745	1	1
8746	1	1
8747	1	1
8748	1	1
8752	1	1
8753	1	1
8754	1	1
8755	1	1
8756	1	1
8757	1	1
8758	1	1
8759	1	1
8760	1	1
8761	1	1
8762	1	1
8763	1	1
8767	1	1
8768	1	1
8769	1	1
8770	1	1
8771	1	1
8772	1	1
8773	1	1
8774	1	1
8775	1	1
8776	1	1
8777	1	1
8778	1	1
8782	1	1
8783	1	1
8784	1	1
8785	1	1
8786	1	1
8787	1	1
8788	1	1
8789	1	1
8790	1	1
8791	1	1
8792	1	1
8793	1	1
8797	1	1
8798	1	1
8799	1	1
8800	1	1
8801	1	1
8802	1	1
8803	1	1
8804	1	1
8805	1	1
8806	1	1
8807	1	1
8808	1	1
8812	1	1
8813	1	1
8814	1	1
8815	1	1
8819	1	1
8820	1	1
8821	1	1
8822	1	1
8826	1	1
8827	1	1
8828	1	1
8829	1	1
8833	1	1
8834	1	1
8835	1	1
8836	1	1
8840	1	1
8841	1	1
8842	1	1
8843	1	1
8847	1	1
8848	1	1
8849	1	1
8850	1	1
8854	1	1
8855	1	1
8856	1	1
8857	1	1
8861	1	1
8862	1	1
8863	1	1
8864	1	1
8868	1	1
8869	1	1
8870	1	1
8871	1	1
8875	1	1
8876	1	1
8877	1	1
8878	1	1
8882	1	1
8883	1	1
8884	1	1
8885	1	1
8889	1	1
8890	1	1
8891	1	1
8892	1	1
8896	1	1
8897	1	1
8898	1	1
8899	1	1
8900	1	1
8901	1	1
8902	1	1
8903	1	1
8904	1	1
8905	1	1
8906	1	1
8907	1	1
8911	1	1
8912	1	1
8913	1	1
8914	1	1
8915	1	1
8916	1	1
8917	1	1
8918	1	1
8919	1	1
8920	1	1
8921	1	1
8922	1	1
8926	1	1
8927	1	1
8931	1	1
8932	1	1
8936	1	1
8937	1	1
8938	1	1
8939	1	1
8940	1	1
8941	1	1
8942	1	1
8943	1	1
8944	1	1
8948	1	1
8949	1	1
8950	1	1
8951	1	1
8952	1	1
8953	1	1
8954	1	1
8955	1	1
8956	1	1
8960	1	1
8961	1	1
8962	1	1
8963	1	1
8964	1	1
8965	1	1
8969	1	1
8972	1	1
8975	1	1
8976	1	1
8977	1	1
8992	1	1
8994	1	1
8995	1	1
8997	1	1
9000	1	1
9015	1	1
9016	1	1

---

Cond Coverage for Module : usbdev_reg_top

	Total	Covered	Percent
Conditions	421	415	98.57
Logical	421	415	98.57
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T42,T43
1	1	Covered	T1,T2,T3

 LINE       77
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T45,T46
1	0	Covered	T42,T43,T74

 LINE       84
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T46
0	1	0	Covered	T42,T43,T74
1	0	0	Covered	T44,T45,T46

 LINE       132
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 1'b0 : 1'b1)
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T17,T18

 LINE       170
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T42,T43,T74
0	1	0	Covered	T41,T75,T151
1	0	0	Covered	T41,T151,T153

 LINE       7921
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_STATE_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7922
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_ENABLE_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       7923
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_INTR_TEST_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T173,T174,T175

 LINE       7924
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T124,T173,T176

 LINE       7925
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBCTRL_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7926
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_OUT_ENABLE_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7927
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_EP_IN_ENABLE_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       7928
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_USBSTAT_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T39,T40

 LINE       7929
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_AVOUTBUFFER_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7930
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_AVSETUPBUFFER_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T14,T15

 LINE       7931
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXFIFO_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       7932
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_SETUP_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T14,T15

 LINE       7933
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_RXENABLE_OUT_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7934
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_SET_NAK_OUT_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T12,T13

 LINE       7935
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_SENT_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       7936
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_STALL_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T22,T23

 LINE       7937
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_STALL_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T177,T112,T173

 LINE       7938
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_0_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T40,T108

 LINE       7939
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_1_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T77,T40,T173

 LINE       7940
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_2_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T14,T111

 LINE       7941
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_3_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T67,T69

 LINE       7942
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_4_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T15,T115

 LINE       7943
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_5_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T31,T173,T176

 LINE       7944
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_6_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T31,T40

 LINE       7945
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_7_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T16,T124,T122

 LINE       7946
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_8_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T124,T173

 LINE       7947
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_9_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T124,T126,T178

 LINE       7948
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_10_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T40,T129

 LINE       7949
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_CONFIGIN_11_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T16,T36

 LINE       7950
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_ISO_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T69,T173,T174

 LINE       7951
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_ISO_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T176,T179,T180

 LINE       7952
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_OUT_DATA_TOGGLE_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T67,T176

 LINE       7953
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_IN_DATA_TOGGLE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T181,T173

 LINE       7954
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_SENSE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T112,T176

 LINE       7955
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_PINS_DRIVE_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T173,T176,T174

 LINE       7956
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_PHY_CONFIG_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T69,T173

 LINE       7957
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_CONTROL_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T173,T176,T174

 LINE       7958
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_WAKE_EVENTS_OFFSET)
            ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T40,T174,T138

 LINE       7959
 EXPRESSION (reg_addr == usbdev_reg_pkg::USBDEV_FIFO_CTRL_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T38,T34,T39

 LINE       7962
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       7962
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       7966
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | (addr_hit[37] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T41,T75,T151

 LINE       7966
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b0111 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0111 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b0111 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b0111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b0011 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b0011 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b0111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b0111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b0011 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
39 (addr_hit[38] & ((|(4'...	Covered	T34,T182,T183
38 (addr_hit[37] & ((|(4'...	Covered	T174,T138,T63
37 (addr_hit[36] & ((|(4'...	Covered	T173,T176,T174
36 (addr_hit[35] & ((|(4'...	Covered	T40,T69,T184
35 (addr_hit[34] & ((|(4'...	Covered	T173,T176,T174
34 (addr_hit[33] & ((|(4'...	Covered	T40,T112,T176
33 (addr_hit[32] & ((|(4'...	Covered	T40,T181,T173
32 (addr_hit[31] & ((|(4'...	Covered	T40,T67,T176
31 (addr_hit[30] & ((|(4'...	Covered	T176,T179,T180
30 (addr_hit[29] & ((|(4'...	Covered	T69,T173,T174
29 (addr_hit[28] & ((|(4'...	Covered	T16,T108,T173
28 (addr_hit[27] & ((|(4'...	Covered	T40,T173,T185
27 (addr_hit[26] & ((|(4'...	Covered	T124,T178,T186
26 (addr_hit[25] & ((|(4'...	Covered	T40,T173,T187
25 (addr_hit[24] & ((|(4'...	Covered	T124,T176,T174
24 (addr_hit[23] & ((|(4'...	Covered	T16,T31,T40
23 (addr_hit[22] & ((|(4'...	Covered	T31,T173,T176
22 (addr_hit[21] & ((|(4'...	Covered	T188,T189,T190
21 (addr_hit[20] & ((|(4'...	Covered	T40,T67,T179
20 (addr_hit[19] & ((|(4'...	Covered	T40,T173,T94
19 (addr_hit[18] & ((|(4'...	Covered	T40,T173,T174
18 (addr_hit[17] & ((|(4'...	Covered	T40,T176,T178
17 (addr_hit[16] & ((|(4'...	Covered	T177,T112,T173
16 (addr_hit[15] & ((|(4'...	Covered	T173,T174,T178
15 (addr_hit[14] & ((|(4'...	Covered	T2,T3,T14
14 (addr_hit[13] & ((|(4'...	Covered	T179,T191,T192
13 (addr_hit[12] & ((|(4'...	Covered	T13,T40,T174
12 (addr_hit[11] & ((|(4'...	Covered	T14,T173,T179
11 (addr_hit[10] & ((|(4'...	Covered	T4,T5,T7
10 (addr_hit[9] & ((|(4'b...	Covered	T40,T176,T178
9 (addr_hit[8] & ((|(4'b...	Covered	T173,T179,T182
8 (addr_hit[7] & ((|(4'b...	Covered	T38,T39,T40
7 (addr_hit[6] & ((|(4'b...	Covered	T173,T176,T128
6 (addr_hit[5] & ((|(4'b...	Covered	T176,T174,T179
5 (addr_hit[4] & ((|(4'b...	Covered	T69,T173,T182
4 (addr_hit[3] & ((|(4'b...	Covered	T124,T176,T193
3 (addr_hit[2] & ((|(4'b...	Covered	T174,T175,T187
2 (addr_hit[1] & ((|(4'b...	Covered	T14,T40,T126
1 (addr_hit[0] & ((|(4'b...	Covered	T1,T2,T3

 LINE       7966
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       7966
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T17
1	1	Covered	T14,T40,T126

 LINE       7966
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T194,T48
1	1	Covered	T174,T175,T187

 LINE       7966
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T176,T187
1	1	Covered	T124,T176,T193

 LINE       7966
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T69,T173,T182

 LINE       7966
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T176,T174,T179

 LINE       7966
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T173,T176,T128

 LINE       7966
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T38,T39,T40
1	1	Covered	T38,T39,T40

 LINE       7966
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T173,T179,T182

 LINE       7966
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T38,T14,T15
1	1	Covered	T40,T176,T178

 LINE       7966
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T6
1	1	Covered	T4,T5,T7

 LINE       7966
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T14,T15
1	1	Covered	T14,T173,T179

 LINE       7966
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T40,T174

 LINE       7966
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T12,T13
1	1	Covered	T179,T191,T192

 LINE       7966
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T2,T3,T14

 LINE       7966
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T22,T23
1	1	Covered	T173,T174,T178

 LINE       7966
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T173,T178,T195
1	1	Covered	T177,T112,T173

 LINE       7966
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T108,T27
1	1	Covered	T40,T176,T178

 LINE       7966
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T109,T110
1	1	Covered	T40,T173,T174

 LINE       7966
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T14,T111
1	1	Covered	T40,T173,T94

 LINE       7966
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T69,T113
1	1	Covered	T40,T67,T179

 LINE       7966
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T115
1	1	Covered	T188,T189,T190

 LINE       7966
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T116,T117,T118
1	1	Covered	T31,T173,T176

 LINE       7966
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T119,T120
1	1	Covered	T16,T31,T40

 LINE       7966
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T122,T123
1	1	Covered	T124,T176,T174

 LINE       7966
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T124,T125,T28
1	1	Covered	T40,T173,T187

 LINE       7966
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T126,T127,T128
1	1	Covered	T124,T178,T186

 LINE       7966
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T40,T129
1	1	Covered	T40,T173,T185

 LINE       7966
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T36,T30
1	1	Covered	T16,T108,T173

 LINE       7966
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T48,T42
1	1	Covered	T69,T173,T174

 LINE       7966
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T197,T198
1	1	Covered	T176,T179,T180

 LINE       7966
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T133,T48
1	1	Covered	T40,T67,T176

 LINE       7966
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T47,T73
1	1	Covered	T40,T181,T173

 LINE       7966
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T48,T41
1	1	Covered	T40,T112,T176

 LINE       7966
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T176,T199,T48
1	1	Covered	T173,T176,T174

 LINE       7966
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T173,T186
1	1	Covered	T40,T69,T184

 LINE       7966
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T183,T197
1	1	Covered	T173,T176,T174

 LINE       7966
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T46,T194
1	1	Covered	T174,T138,T63

 LINE       7966
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T38,T39,T40
1	1	Covered	T34,T182,T183

 LINE       8009
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T151,T153,T156
1	1	1	Covered	T1,T2,T3

 LINE       8036
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T17
1	1	0	Covered	T41,T151,T153
1	1	1	Covered	T2,T3,T17

 LINE       8073
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T173,T174,T175
1	1	0	Covered	T41,T153,T156
1	1	1	Covered	T52,T53,T47

 LINE       8110
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T124,T173,T176
1	1	0	Covered	T41,T153,T156
1	1	1	Covered	T48,T42,T49

 LINE       8113
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T41,T153,T201
1	1	1	Covered	T1,T2,T3

 LINE       8120
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T151,T153,T155
1	1	1	Covered	T1,T2,T3

 LINE       8145
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T151,T153,T201
1	1	1	Covered	T2,T3,T10

 LINE       8170
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T39,T40
1	1	0	Not Covered
1	1	1	Covered	T38,T39,T40

 LINE       8171
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T151,T157,T201
1	1	1	Covered	T1,T2,T3

 LINE       8174
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T14,T15
1	1	0	Covered	T41,T151,T153
1	1	1	Covered	T38,T14,T15

 LINE       8177
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       8178
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T17,T14,T15
1	1	0	Covered	T41,T151,T153
1	1	1	Covered	T17,T14,T15

 LINE       8203
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T41,T153,T156
1	1	1	Covered	T1,T2,T3

 LINE       8228
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T12,T13
1	1	0	Covered	T41,T151,T156
1	1	1	Covered	T6,T12,T13

 LINE       8253
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T151,T153,T156
1	1	1	Covered	T2,T3,T10

 LINE       8278
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T22,T23
1	1	0	Covered	T151,T153,T156
1	1	1	Covered	T1,T22,T23

 LINE       8303
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T177,T112,T173
1	1	0	Covered	T41,T151,T153
1	1	1	Covered	T48,T42,T49

 LINE       8328
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T40,T108
1	1	0	Covered	T41,T152,T156
1	1	1	Covered	T2,T108,T27

 LINE       8337
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T77,T40,T69
1	1	0	Covered	T41,T153,T156
1	1	1	Covered	T77,T109,T110

 LINE       8346
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T21,T14,T111
1	1	0	Covered	T41,T153,T156
1	1	1	Covered	T14,T111,T112

 LINE       8355
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T40,T67,T69
1	1	0	Covered	T41,T151,T153
1	1	1	Covered	T69,T113,T114

 LINE       8364
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T15,T115
1	1	0	Covered	T41,T153,T201
1	1	1	Covered	T3,T15,T115

 LINE       8373
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T173,T176
1	1	0	Covered	T41,T153,T156
1	1	1	Covered	T116,T117,T118

 LINE       8382
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T16,T31,T40
1	1	0	Covered	T41,T151,T201
1	1	1	Covered	T119,T120,T121

 LINE       8391
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T16,T124,T122
1	1	0	Covered	T41,T153,T202
1	1	1	Covered	T16,T122,T123

 LINE       8400
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T40,T124,T173
1	1	0	Covered	T151,T153,T156
1	1	1	Covered	T124,T125,T28

 LINE       8409
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T124,T126,T178
1	1	0	Covered	T41,T151,T153
1	1	1	Covered	T126,T127,T128

 LINE       8418
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T40,T129
1	1	0	Covered	T41,T151,T153
1	1	1	Covered	T11,T129,T130

 LINE       8427
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T16,T36
1	1	0	Covered	T41,T75,T151
1	1	1	Covered	T10,T36,T30

 LINE       8436
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T69,T173,T174
1	1	0	Covered	T41,T151,T153
1	1	1	Covered	T48,T42,T49

 LINE       8461
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T176,T179,T180
1	1	0	Covered	T41,T151,T153
1	1	1	Covered	T48,T42,T49

 LINE       8486
 EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T40,T67,T176
1	1	0	Not Covered
1	1	1	Covered	T48,T47,T73

 LINE       8487
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T40,T67,T176
1	1	0	Covered	T151,T201,T203
1	1	1	Covered	T47,T76,T50

 LINE       8492
 EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T40,T181,T173
1	1	0	Not Covered
1	1	1	Covered	T48,T47,T73

 LINE       8493
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T40,T181,T173
1	1	0	Covered	T41,T151,T153
1	1	1	Covered	T47,T76,T50

 LINE       8498
 EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T40,T112,T176
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       8499
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T173,T176,T174
1	1	0	Covered	T41,T151,T153
1	1	1	Covered	T48,T42,T49

 LINE       8518
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T40,T69,T173
1	1	0	Covered	T151,T153,T156
1	1	1	Covered	T48,T42,T49

 LINE       8531
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T173,T176,T174
1	1	0	Covered	T41,T153,T201
1	1	1	Covered	T48,T42,T49

 LINE       8534
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T34,T39
1	1	0	Covered	T41,T153,T156
1	1	1	Covered	T38,T39,T40

 LINE       8992
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T48,T42,T49

---

Branch Coverage for Module : usbdev_reg_top

	Line No.	Total	Covered	Percent
Branches		52	52	100.00
TERNARY	7962	2	2	100.00
IF	75	3	3	100.00
TERNARY	132	2	2	100.00
IF	138	2	2	100.00
CASE	8589	40	40	100.00
CASE	8995	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	7962	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	75	if ((!rst_ni))
-2-:	77	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T44,T45,T46
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	132	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T17,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T74
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	8589	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	8995	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	211709320	111018	0	0
reAfterRv	211709320	111018	0	0
rePulse	211709320	55947	0	0
wePulse	211709320	55071	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	111018	0	0
T1	401953	10	0	0
T2	406099	22	0	0
T3	404913	20	0	0
T4	402230	8	0	0
T5	401561	8	0	0
T6	404149	16	0	0
T7	401640	8	0	0
T8	403858	8	0	0
T9	401577	8	0	0
T17	401346	9	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	111018	0	0
T1	401953	10	0	0
T2	406099	22	0	0
T3	404913	20	0	0
T4	402230	8	0	0
T5	401561	8	0	0
T6	404149	16	0	0
T7	401640	8	0	0
T8	403858	8	0	0
T9	401577	8	0	0
T17	401346	9	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	55947	0	0
T1	401953	3	0	0
T2	406099	8	0	0
T3	404913	7	0	0
T4	402230	3	0	0
T5	401561	3	0	0
T6	404149	6	0	0
T7	401640	3	0	0
T8	403858	3	0	0
T9	401577	3	0	0
T17	401346	3	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	211709320	55071	0	0
T1	401953	7	0	0
T2	406099	14	0	0
T3	404913	13	0	0
T4	402230	5	0	0
T5	401561	5	0	0
T6	404149	10	0	0
T7	401640	5	0	0
T8	403858	5	0	0
T9	401577	5	0	0
T17	401346	6	0	0