Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	78287	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	81390	1		T1	3		T2	6		T3	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	75164	1		T1	3		T2	6		T3	3
values[0x0]	41881	1		T1	3		T2	5		T3	1
values[0x1]	42632	1		T1	2		T2	6		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59982	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	99695	1		T1	5		T2	8		T3	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	571	1		T33	2		T78	2		T43	1
valid_sources[0x01]	613	1		T46	81		T33	6		T72	3
valid_sources[0x02]	579	1		T33	11		T78	2		T23	1
valid_sources[0x03]	623	1		T77	15		T78	1		T43	1
valid_sources[0x04]	500	1		T33	3		T11	4		T78	2
valid_sources[0x05]	524	1		T10	1		T33	4		T48	27
valid_sources[0x06]	661	1		T9	1		T48	7		T78	3
valid_sources[0x07]	1415	1		T21	1		T33	3		T48	9
valid_sources[0x08]	521	1		T48	9		T236	5		T72	1
valid_sources[0x09]	456	1		T33	1		T78	2		T128	2
valid_sources[0x0a]	531	1		T45	1		T33	12		T78	1
valid_sources[0x0b]	504	1		T26	1		T185	5		T237	3
valid_sources[0x0c]	532	1		T47	2		T33	1		T78	13
valid_sources[0x0d]	519	1		T78	3		T123	1		T128	1
valid_sources[0x0e]	518	1		T33	6		T78	2		T72	1
valid_sources[0x0f]	584	1		T46	44		T47	1		T78	1
valid_sources[0x10]	526	1		T78	3		T72	9		T75	10
valid_sources[0x11]	464	1		T33	1		T48	24		T78	1
valid_sources[0x12]	436	1		T22	3		T24	1		T75	16
valid_sources[0x13]	460	1		T78	8		T26	2		T35	1
valid_sources[0x14]	473	1		T78	3		T198	1		T75	12
valid_sources[0x15]	827	1		T33	9		T22	1		T78	10
valid_sources[0x16]	461	1		T21	1		T33	6		T78	6
valid_sources[0x17]	509	1		T8	1		T33	2		T78	5
valid_sources[0x18]	1541	1		T33	1		T78	1		T85	2
valid_sources[0x19]	591	1		T6	8		T33	2		T48	37
valid_sources[0x1a]	485	1		T78	5		T72	8		T36	1
valid_sources[0x1b]	515	1		T33	9		T72	6		T75	13
valid_sources[0x1c]	532	1		T9	1		T48	11		T78	1
valid_sources[0x1d]	543	1		T33	2		T78	3		T72	5
valid_sources[0x1e]	1309	1		T33	1		T78	5		T85	1
valid_sources[0x1f]	615	1		T33	1		T78	1		T198	1
valid_sources[0x20]	574	1		T33	1		T78	6		T75	5
valid_sources[0x21]	561	1		T33	11		T48	20		T11	3
valid_sources[0x22]	589	1		T33	3		T78	5		T75	8
valid_sources[0x23]	587	1		T48	12		T22	1		T11	8
valid_sources[0x24]	514	1		T33	6		T78	7		T43	2
valid_sources[0x25]	600	1		T33	1		T22	2		T78	1
valid_sources[0x26]	830	1		T33	1		T78	3		T85	1
valid_sources[0x27]	796	1		T33	4		T48	5		T41	1
valid_sources[0x28]	501	1		T21	1		T78	5		T198	1
valid_sources[0x29]	570	1		T5	11		T33	5		T48	22
valid_sources[0x2a]	531	1		T33	3		T78	5		T36	1
valid_sources[0x2b]	579	1		T33	5		T78	4		T72	9
valid_sources[0x2c]	474	1		T21	1		T33	5		T48	5
valid_sources[0x2d]	535	1		T10	1		T33	1		T78	2
valid_sources[0x2e]	724	1		T48	29		T77	52		T78	5
valid_sources[0x2f]	543	1		T33	9		T78	4		T44	2
valid_sources[0x30]	435	1		T78	3		T238	8		T75	4
valid_sources[0x31]	468	1		T4	2		T78	2		T192	1
valid_sources[0x32]	478	1		T33	9		T78	4		T28	1
valid_sources[0x33]	540	1		T33	6		T78	3		T72	1
valid_sources[0x34]	616	1		T1	1		T78	5		T72	13
valid_sources[0x35]	605	1		T47	1		T33	3		T78	11
valid_sources[0x36]	550	1		T33	7		T78	2		T35	1
valid_sources[0x37]	565	1		T33	4		T78	1		T85	1
valid_sources[0x38]	524	1		T33	2		T78	1		T23	1
valid_sources[0x39]	647	1		T46	14		T33	3		T48	15
valid_sources[0x3a]	573	1		T33	3		T78	1		T43	1
valid_sources[0x3b]	507	1		T13	1		T78	1		T27	1
valid_sources[0x3c]	691	1		T2	17		T3	8		T33	4
valid_sources[0x3d]	1846	1		T46	76		T33	1		T78	3
valid_sources[0x3e]	581	1		T46	55		T33	6		T11	9
valid_sources[0x3f]	614	1		T33	8		T11	1		T78	3
valid_sources[0x40]	445	1		T1	1		T8	3		T13	4
valid_sources[0x41]	493	1		T48	1		T78	6		T201	8
valid_sources[0x42]	573	1		T33	7		T79	1		T77	45
valid_sources[0x43]	508	1		T9	1		T33	8		T78	6
valid_sources[0x44]	663	1		T9	1		T33	1		T78	6
valid_sources[0x45]	569	1		T10	1		T46	49		T78	6
valid_sources[0x46]	692	1		T33	3		T48	5		T77	53
valid_sources[0x47]	513	1		T33	1		T78	8		T35	1
valid_sources[0x48]	607	1		T77	132		T78	2		T75	1
valid_sources[0x49]	637	1		T33	5		T78	7		T23	1
valid_sources[0x4a]	514	1		T33	6		T28	1		T239	5
valid_sources[0x4b]	468	1		T9	1		T47	1		T78	5
valid_sources[0x4c]	583	1		T33	4		T78	2		T72	8
valid_sources[0x4d]	1021	1		T1	1		T78	1		T237	3
valid_sources[0x4e]	552	1		T10	1		T18	5		T33	1
valid_sources[0x4f]	636	1		T33	2		T48	11		T78	1
valid_sources[0x50]	611	1		T46	114		T33	1		T78	10
valid_sources[0x51]	499	1		T33	3		T78	4		T113	1
valid_sources[0x52]	549	1		T77	84		T78	1		T27	1
valid_sources[0x53]	536	1		T10	1		T33	2		T48	17
valid_sources[0x54]	605	1		T113	1		T185	2		T240	4
valid_sources[0x55]	586	1		T9	1		T46	27		T33	1
valid_sources[0x56]	464	1		T33	3		T78	5		T14	1
valid_sources[0x57]	496	1		T33	1		T78	7		T75	7
valid_sources[0x58]	796	1		T33	6		T78	2		T42	1
valid_sources[0x59]	686	1		T48	2		T78	1		T72	1
valid_sources[0x5a]	465	1		T33	1		T48	12		T78	6
valid_sources[0x5b]	743	1		T33	5		T78	3		T85	1
valid_sources[0x5c]	537	1		T33	1		T78	6		T72	12
valid_sources[0x5d]	599	1		T79	5		T78	1		T14	4
valid_sources[0x5e]	910	1		T10	1		T78	7		T85	1
valid_sources[0x5f]	581	1		T18	2		T33	6		T22	1
valid_sources[0x60]	1570	1		T1	1		T34	1022		T43	2
valid_sources[0x61]	544	1		T33	2		T11	1		T77	10
valid_sources[0x62]	687	1		T33	1		T11	4		T78	3
valid_sources[0x63]	767	1		T33	5		T77	92		T78	3
valid_sources[0x64]	903	1		T33	1		T78	2		T72	1
valid_sources[0x65]	689	1		T33	2		T48	3		T78	2
valid_sources[0x66]	467	1		T33	1		T48	2		T78	5
valid_sources[0x67]	533	1		T21	1		T78	2		T85	1
valid_sources[0x68]	674	1		T33	1		T78	3		T236	2
valid_sources[0x69]	505	1		T33	2		T48	46		T78	1
valid_sources[0x6a]	543	1		T48	9		T78	3		T14	1
valid_sources[0x6b]	588	1		T47	1		T33	3		T79	1
valid_sources[0x6c]	566	1		T33	4		T78	2		T85	1
valid_sources[0x6d]	445	1		T33	4		T48	2		T72	5
valid_sources[0x6e]	572	1		T78	3		T241	1		T123	1
valid_sources[0x6f]	520	1		T33	4		T78	1		T72	1
valid_sources[0x70]	598	1		T33	2		T77	43		T78	6
valid_sources[0x71]	570	1		T33	6		T78	4		T23	1
valid_sources[0x72]	474	1		T21	1		T33	4		T11	2
valid_sources[0x73]	529	1		T33	1		T78	2		T242	1
valid_sources[0x74]	666	1		T33	4		T78	1		T123	1
valid_sources[0x75]	464	1		T8	1		T78	7		T16	9
valid_sources[0x76]	622	1		T78	13		T27	1		T242	1
valid_sources[0x77]	571	1		T33	1		T78	1		T75	2
valid_sources[0x78]	646	1		T9	1		T33	3		T48	5
valid_sources[0x79]	650	1		T8	1		T45	1		T33	3
valid_sources[0x7a]	662	1		T33	2		T77	32		T78	10
valid_sources[0x7b]	538	1		T9	1		T33	1		T48	7
valid_sources[0x7c]	602	1		T33	20		T48	7		T78	1
valid_sources[0x7d]	522	1		T33	4		T78	6		T25	11
valid_sources[0x7e]	524	1		T33	2		T78	4		T27	1
valid_sources[0x7f]	887	1		T33	3		T22	1		T78	1
valid_sources[0x80]	1554	1		T48	18		T78	6		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

31889

1

T1

1

T6

1

T4

1

values[0x0]

all_enables

biggest_size

27367

1

T1

2

T2

4

T3

1

values[0x1]

all_enables

biggest_size

22134

1

T2

2

T4

1

T5

1