Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.67	91.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	91.67	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.67	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	2	14	87.50

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	2	14	87.50	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	92977	1		T1	5		T2	11		T3	7
full_word	82431	1		T1	3		T2	6		T3	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	175288	1		T1	8		T2	17		T3	8
auto[TlIntgErrCmd]	36	1		T83	2		T164	3		T167	3
auto[TlIntgErrData]	39	1		T83	3		T164	5		T167	2
auto[TlIntgErrBoth]	45	1		T83	5		T164	2		T167	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	77183	1		T1	3		T2	6		T3	3
auto[1]	98225	1		T1	5		T2	11		T3	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	45035	1		T1	2		T2	6		T3	3
auto[TlIntgErrNone]	partial	auto[1]	47827	1		T1	3		T2	5		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	32090	1		T1	1		T6	1		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	50336	1		T1	2		T2	6		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	15	1		T83	2		T167	3		T218	1
auto[TlIntgErrCmd]	partial	auto[1]	20	1		T164	2		T218	1		T184	3
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T164	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	21	1		T83	1		T164	5		T167	1
auto[TlIntgErrData]	partial	auto[1]	15	1		T83	1		T218	2		T219	1
auto[TlIntgErrData]	full_word	auto[0]	1	1		T167	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1		T83	1		T220	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	20	1		T83	3		T167	2		T218	2
auto[TlIntgErrBoth]	partial	auto[1]	24	1		T83	2		T164	2		T167	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T167	1		-	-		-	-