Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Totals	5	5	100.00
Total Bits	78	78	100.00
Total Bits 0->1	39	39	100.00
Total Bits 1->0	39	39	100.00

Ports	5	5	100.00
Port Bits	78	78	100.00
Port Bits 0->1	39	39	100.00
Port Bits 1->0	39	39	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
oh_i[6:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[7]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[9:8]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
oh_i[10]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[32:11]	Yes	Yes	*T4,*T11,*T12	Yes	T4,T11,T12	INPUT
oh_i[33]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[36:34]	Yes	Yes	*T23,*T24,T52	Yes	T23,T24,T52	INPUT
oh_i[37]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[38]	Yes	Yes	T46,T33,T48	Yes	T46,T33,T48	INPUT
addr_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
err_o	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT

*Tests covering at least one bit in the range