Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_wake_events_cdc 57.45 82.35 30.77 66.67 50.00
tb.dut.u_reg.u_wake_control_cdc 97.73 100.00 90.91 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_events_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
57.45 82.35 30.77 66.67 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
45.74 76.56 25.00 61.40 20.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.64 99.73 98.81 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 37.10 72.45 22.45 53.49 0.00
u_src_to_dst_req 58.33 100.00 33.33 100.00 0.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.13 96.08 96.43 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.64 99.73 98.81 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.88 87.50 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT49,T58,T59

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT49,T58,T59
11CoveredT49,T58,T59

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT49,T58,T59

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT49,T58,T59
11CoveredT49,T58,T59

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T49,T58,T59
0 0 1 Covered T49,T58,T59
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T49,T58,T59
0 0 1 Covered T49,T58,T59
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 436061064 5380 0 0
DstReqKnown_A 181689126 181459040 0 0
SrcAckBusyChk_A 436061064 730 0 0
SrcBusyKnown_A 436061064 435831220 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 436061064 5380 0 0
T49 3214 15 0 0
T51 4144 14 0 0
T55 2073 12 0 0
T58 8091 73 0 0
T59 6702 128 0 0
T80 6541 13 0 0
T81 2656 41 0 0
T82 2172 8 0 0
T83 13137 81 0 0
T84 5976 51 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181689126 181459040 0 0
T1 285296 285176 0 0
T2 372262 372018 0 0
T3 368240 368138 0 0
T4 384534 384248 0 0
T5 368986 368738 0 0
T6 267790 267650 0 0
T7 387846 387514 0 0
T8 385610 385304 0 0
T9 303152 302894 0 0
T10 301242 300808 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 436061064 730 0 0
T49 3214 2 0 0
T51 4144 2 0 0
T55 2073 1 0 0
T58 8091 10 0 0
T59 6702 14 0 0
T80 6541 2 0 0
T81 2656 5 0 0
T82 2172 1 0 0
T83 13137 10 0 0
T84 5976 6 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 436061064 435831220 0 0
T1 805566 805390 0 0
T2 812234 811930 0 0
T3 803460 803334 0 0
T4 802516 802178 0 0
T5 805086 804822 0 0
T6 803390 803246 0 0
T7 809432 809136 0 0
T8 804764 804480 0 0
T9 808434 808142 0 0
T10 803334 802914 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
TOTAL171482.35
CONT_ASSIGN5400
ALWAYS605480.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS1047571.43
CONT_ASSIGN13900
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 unreachable
60 1 1
61 1 1
62 1 1
63 unreachable
64 1 1
65 0 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 unreachable
113 unreachable
114 1 1
123 0 1
124 0 1
MISSING_ELSE
139 unreachable
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalCoveredPercent
Conditions13430.77
Logical13430.77
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
Branches 6 4 66.67
IF 60 3 2 66.67
IF 104 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 218030532 0 0 0
DstReqKnown_A 90844563 90729520 0 0
SrcAckBusyChk_A 218030532 0 0 0
SrcBusyKnown_A 218030532 217915610 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218030532 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 90844563 90729520 0 0
T1 142648 142588 0 0
T2 186131 186009 0 0
T3 184120 184069 0 0
T4 192267 192124 0 0
T5 184493 184369 0 0
T6 133895 133825 0 0
T7 193923 193757 0 0
T8 192805 192652 0 0
T9 151576 151447 0 0
T10 150621 150404 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218030532 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218030532 217915610 0 0
T1 402783 402695 0 0
T2 406117 405965 0 0
T3 401730 401667 0 0
T4 401258 401089 0 0
T5 402543 402411 0 0
T6 401695 401623 0 0
T7 404716 404568 0 0
T8 402382 402240 0 0
T9 404217 404071 0 0
T10 401667 401457 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT49,T58,T59

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT49,T58,T59
11CoveredT49,T58,T59

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT49,T58,T59

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT49,T58,T59
11CoveredT49,T58,T59

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T49,T58,T59
0 0 1 Covered T49,T58,T59
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T49,T58,T59
0 0 1 Covered T49,T58,T59
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 218030532 5380 0 0
DstReqKnown_A 90844563 90729520 0 0
SrcAckBusyChk_A 218030532 730 0 0
SrcBusyKnown_A 218030532 217915610 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218030532 5380 0 0
T49 3214 15 0 0
T51 4144 14 0 0
T55 2073 12 0 0
T58 8091 73 0 0
T59 6702 128 0 0
T80 6541 13 0 0
T81 2656 41 0 0
T82 2172 8 0 0
T83 13137 81 0 0
T84 5976 51 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 90844563 90729520 0 0
T1 142648 142588 0 0
T2 186131 186009 0 0
T3 184120 184069 0 0
T4 192267 192124 0 0
T5 184493 184369 0 0
T6 133895 133825 0 0
T7 193923 193757 0 0
T8 192805 192652 0 0
T9 151576 151447 0 0
T10 150621 150404 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218030532 730 0 0
T49 3214 2 0 0
T51 4144 2 0 0
T55 2073 1 0 0
T58 8091 10 0 0
T59 6702 14 0 0
T80 6541 2 0 0
T81 2656 5 0 0
T82 2172 1 0 0
T83 13137 10 0 0
T84 5976 6 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218030532 217915610 0 0
T1 402783 402695 0 0
T2 406117 405965 0 0
T3 401730 401667 0 0
T4 401258 401089 0 0
T5 402543 402411 0 0
T6 401695 401623 0 0
T7 404716 404568 0 0
T8 402382 402240 0 0
T9 404217 404071 0 0
T10 401667 401457 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%