Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 14 | 10 | 71.43 |
Logical | 14 | 10 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T49,T58,T59 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T49,T58,T59 |
1 | 1 | Covered | T49,T58,T59 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T49,T58,T59 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T49,T58,T59 |
1 | 1 | Covered | T49,T58,T59 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T49,T58,T59 |
0 |
0 |
1 |
Covered |
T49,T58,T59 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T49,T58,T59 |
0 |
0 |
1 |
Covered |
T49,T58,T59 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
436061064 |
5380 |
0 |
0 |
T49 |
3214 |
15 |
0 |
0 |
T51 |
4144 |
14 |
0 |
0 |
T55 |
2073 |
12 |
0 |
0 |
T58 |
8091 |
73 |
0 |
0 |
T59 |
6702 |
128 |
0 |
0 |
T80 |
6541 |
13 |
0 |
0 |
T81 |
2656 |
41 |
0 |
0 |
T82 |
2172 |
8 |
0 |
0 |
T83 |
13137 |
81 |
0 |
0 |
T84 |
5976 |
51 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
181689126 |
181459040 |
0 |
0 |
T1 |
285296 |
285176 |
0 |
0 |
T2 |
372262 |
372018 |
0 |
0 |
T3 |
368240 |
368138 |
0 |
0 |
T4 |
384534 |
384248 |
0 |
0 |
T5 |
368986 |
368738 |
0 |
0 |
T6 |
267790 |
267650 |
0 |
0 |
T7 |
387846 |
387514 |
0 |
0 |
T8 |
385610 |
385304 |
0 |
0 |
T9 |
303152 |
302894 |
0 |
0 |
T10 |
301242 |
300808 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
436061064 |
730 |
0 |
0 |
T49 |
3214 |
2 |
0 |
0 |
T51 |
4144 |
2 |
0 |
0 |
T55 |
2073 |
1 |
0 |
0 |
T58 |
8091 |
10 |
0 |
0 |
T59 |
6702 |
14 |
0 |
0 |
T80 |
6541 |
2 |
0 |
0 |
T81 |
2656 |
5 |
0 |
0 |
T82 |
2172 |
1 |
0 |
0 |
T83 |
13137 |
10 |
0 |
0 |
T84 |
5976 |
6 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
436061064 |
435831220 |
0 |
0 |
T1 |
805566 |
805390 |
0 |
0 |
T2 |
812234 |
811930 |
0 |
0 |
T3 |
803460 |
803334 |
0 |
0 |
T4 |
802516 |
802178 |
0 |
0 |
T5 |
805086 |
804822 |
0 |
0 |
T6 |
803390 |
803246 |
0 |
0 |
T7 |
809432 |
809136 |
0 |
0 |
T8 |
804764 |
804480 |
0 |
0 |
T9 |
808434 |
808142 |
0 |
0 |
T10 |
803334 |
802914 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 17 | 14 | 82.35 |
CONT_ASSIGN | 54 | 0 | 0 | |
ALWAYS | 60 | 5 | 4 | 80.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 7 | 5 | 71.43 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
|
unreachable |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
|
unreachable |
64 |
1 |
1 |
65 |
0 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
|
unreachable |
113 |
|
unreachable |
114 |
1 |
1 |
123 |
0 |
1 |
124 |
0 |
1 |
|
|
|
MISSING_ELSE |
139 |
|
unreachable |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Total | Covered | Percent |
Conditions | 13 | 4 | 30.77 |
Logical | 13 | 4 | 30.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
4 |
66.67 |
IF |
60 |
3 |
2 |
66.67 |
IF |
104 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
218030532 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
90844563 |
90729520 |
0 |
0 |
T1 |
142648 |
142588 |
0 |
0 |
T2 |
186131 |
186009 |
0 |
0 |
T3 |
184120 |
184069 |
0 |
0 |
T4 |
192267 |
192124 |
0 |
0 |
T5 |
184493 |
184369 |
0 |
0 |
T6 |
133895 |
133825 |
0 |
0 |
T7 |
193923 |
193757 |
0 |
0 |
T8 |
192805 |
192652 |
0 |
0 |
T9 |
151576 |
151447 |
0 |
0 |
T10 |
150621 |
150404 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
218030532 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
218030532 |
217915610 |
0 |
0 |
T1 |
402783 |
402695 |
0 |
0 |
T2 |
406117 |
405965 |
0 |
0 |
T3 |
401730 |
401667 |
0 |
0 |
T4 |
401258 |
401089 |
0 |
0 |
T5 |
402543 |
402411 |
0 |
0 |
T6 |
401695 |
401623 |
0 |
0 |
T7 |
404716 |
404568 |
0 |
0 |
T8 |
402382 |
402240 |
0 |
0 |
T9 |
404217 |
404071 |
0 |
0 |
T10 |
401667 |
401457 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T49,T58,T59 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T49,T58,T59 |
1 | 1 | Covered | T49,T58,T59 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T49,T58,T59 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T49,T58,T59 |
1 | 1 | Covered | T49,T58,T59 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T49,T58,T59 |
0 |
0 |
1 |
Covered |
T49,T58,T59 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T49,T58,T59 |
0 |
0 |
1 |
Covered |
T49,T58,T59 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
218030532 |
5380 |
0 |
0 |
T49 |
3214 |
15 |
0 |
0 |
T51 |
4144 |
14 |
0 |
0 |
T55 |
2073 |
12 |
0 |
0 |
T58 |
8091 |
73 |
0 |
0 |
T59 |
6702 |
128 |
0 |
0 |
T80 |
6541 |
13 |
0 |
0 |
T81 |
2656 |
41 |
0 |
0 |
T82 |
2172 |
8 |
0 |
0 |
T83 |
13137 |
81 |
0 |
0 |
T84 |
5976 |
51 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
90844563 |
90729520 |
0 |
0 |
T1 |
142648 |
142588 |
0 |
0 |
T2 |
186131 |
186009 |
0 |
0 |
T3 |
184120 |
184069 |
0 |
0 |
T4 |
192267 |
192124 |
0 |
0 |
T5 |
184493 |
184369 |
0 |
0 |
T6 |
133895 |
133825 |
0 |
0 |
T7 |
193923 |
193757 |
0 |
0 |
T8 |
192805 |
192652 |
0 |
0 |
T9 |
151576 |
151447 |
0 |
0 |
T10 |
150621 |
150404 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
218030532 |
730 |
0 |
0 |
T49 |
3214 |
2 |
0 |
0 |
T51 |
4144 |
2 |
0 |
0 |
T55 |
2073 |
1 |
0 |
0 |
T58 |
8091 |
10 |
0 |
0 |
T59 |
6702 |
14 |
0 |
0 |
T80 |
6541 |
2 |
0 |
0 |
T81 |
2656 |
5 |
0 |
0 |
T82 |
2172 |
1 |
0 |
0 |
T83 |
13137 |
10 |
0 |
0 |
T84 |
5976 |
6 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
218030532 |
217915610 |
0 |
0 |
T1 |
402783 |
402695 |
0 |
0 |
T2 |
406117 |
405965 |
0 |
0 |
T3 |
401730 |
401667 |
0 |
0 |
T4 |
401258 |
401089 |
0 |
0 |
T5 |
402543 |
402411 |
0 |
0 |
T6 |
401695 |
401623 |
0 |
0 |
T7 |
404716 |
404568 |
0 |
0 |
T8 |
402382 |
402240 |
0 |
0 |
T9 |
404217 |
404071 |
0 |
0 |
T10 |
401667 |
401457 |
0 |
0 |