Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	82749	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	76172	1		T1	8		T2	4		T3	8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	78858	1		T1	5		T2	3		T3	6
values[0x0]	39536	1		T1	3		T2	4		T3	6
values[0x1]	40527	1		T1	3		T2	3		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62183	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	96738	1		T1	10		T2	5		T3	12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	484	1		T8	5		T38	5		T223	1
valid_sources[0x01]	539	1		T8	10		T38	2		T224	1
valid_sources[0x02]	514	1		T43	1		T60	1		T38	3
valid_sources[0x03]	733	1		T8	4		T38	3		T224	2
valid_sources[0x04]	730	1		T8	6		T38	5		T121	2
valid_sources[0x05]	422	1		T8	2		T25	1		T38	2
valid_sources[0x06]	546	1		T8	6		T38	1		T134	1
valid_sources[0x07]	578	1		T6	39		T8	2		T38	3
valid_sources[0x08]	506	1		T8	9		T28	1		T60	1
valid_sources[0x09]	546	1		T8	1		T38	2		T122	1
valid_sources[0x0a]	620	1		T8	3		T225	3		T226	2
valid_sources[0x0b]	707	1		T8	1		T38	2		T127	1
valid_sources[0x0c]	583	1		T8	4		T38	5		T29	1
valid_sources[0x0d]	486	1		T8	1		T38	3		T102	1
valid_sources[0x0e]	544	1		T8	7		T38	1		T17	1
valid_sources[0x0f]	516	1		T8	2		T38	4		T23	1
valid_sources[0x10]	556	1		T8	1		T28	1		T224	1
valid_sources[0x11]	515	1		T8	3		T38	3		T18	1
valid_sources[0x12]	594	1		T8	6		T38	4		T120	1
valid_sources[0x13]	662	1		T8	5		T38	1		T61	2
valid_sources[0x14]	442	1		T8	3		T25	3		T115	1
valid_sources[0x15]	575	1		T25	1		T38	4		T227	8
valid_sources[0x16]	559	1		T8	3		T25	1		T38	1
valid_sources[0x17]	1030	1		T38	3		T62	1		T108	1
valid_sources[0x18]	665	1		T8	2		T38	6		T93	1
valid_sources[0x19]	580	1		T8	1		T38	3		T228	1
valid_sources[0x1a]	929	1		T2	1		T8	5		T38	1
valid_sources[0x1b]	803	1		T8	2		T38	4		T68	3
valid_sources[0x1c]	651	1		T8	5		T25	2		T38	2
valid_sources[0x1d]	564	1		T8	2		T60	1		T25	1
valid_sources[0x1e]	1730	1		T8	8		T25	2		T38	3
valid_sources[0x1f]	529	1		T2	1		T8	3		T38	1
valid_sources[0x20]	753	1		T8	1		T38	4		T121	1
valid_sources[0x21]	478	1		T8	3		T38	3		T37	1
valid_sources[0x22]	702	1		T8	6		T38	1		T229	47
valid_sources[0x23]	533	1		T8	3		T38	2		T21	1
valid_sources[0x24]	485	1		T8	1		T25	2		T38	4
valid_sources[0x25]	651	1		T8	9		T38	2		T230	10
valid_sources[0x26]	488	1		T8	3		T38	4		T134	1
valid_sources[0x27]	483	1		T8	3		T38	4		T226	8
valid_sources[0x28]	495	1		T8	3		T38	1		T21	1
valid_sources[0x29]	548	1		T8	3		T38	6		T23	1
valid_sources[0x2a]	565	1		T8	9		T38	4		T62	2
valid_sources[0x2b]	552	1		T8	6		T38	3		T17	1
valid_sources[0x2c]	522	1		T8	1		T225	12		T226	3
valid_sources[0x2d]	620	1		T8	6		T38	7		T231	5
valid_sources[0x2e]	627	1		T5	8		T8	6		T38	3
valid_sources[0x2f]	548	1		T8	3		T38	2		T29	1
valid_sources[0x30]	483	1		T8	7		T38	3		T232	4
valid_sources[0x31]	641	1		T8	1		T38	2		T22	1
valid_sources[0x32]	588	1		T8	2		T38	3		T23	1
valid_sources[0x33]	593	1		T8	4		T38	1		T21	1
valid_sources[0x34]	453	1		T8	2		T38	4		T29	1
valid_sources[0x35]	459	1		T8	3		T38	6		T93	1
valid_sources[0x36]	452	1		T8	9		T38	6		T233	2
valid_sources[0x37]	441	1		T8	3		T26	1		T120	1
valid_sources[0x38]	500	1		T8	2		T38	1		T234	1
valid_sources[0x39]	539	1		T8	4		T38	4		T228	1
valid_sources[0x3a]	399	1		T8	3		T38	4		T107	1
valid_sources[0x3b]	679	1		T8	3		T13	3		T38	4
valid_sources[0x3c]	564	1		T8	10		T38	2		T235	1
valid_sources[0x3d]	542	1		T8	4		T38	7		T108	3
valid_sources[0x3e]	546	1		T8	2		T16	16		T38	2
valid_sources[0x3f]	613	1		T8	6		T38	3		T17	1
valid_sources[0x40]	516	1		T8	2		T25	1		T38	5
valid_sources[0x41]	628	1		T8	5		T38	2		T27	39
valid_sources[0x42]	498	1		T8	5		T38	6		T30	1
valid_sources[0x43]	486	1		T8	5		T38	4		T122	3
valid_sources[0x44]	521	1		T8	3		T28	1		T38	1
valid_sources[0x45]	494	1		T38	4		T102	2		T69	1
valid_sources[0x46]	513	1		T8	2		T38	1		T232	2
valid_sources[0x47]	457	1		T8	7		T38	4		T62	1
valid_sources[0x48]	526	1		T8	8		T38	7		T225	18
valid_sources[0x49]	584	1		T8	4		T24	11		T61	1
valid_sources[0x4a]	439	1		T8	2		T10	2		T11	1
valid_sources[0x4b]	469	1		T8	4		T26	2		T38	1
valid_sources[0x4c]	603	1		T1	2		T8	5		T38	3
valid_sources[0x4d]	611	1		T8	1		T60	1		T38	1
valid_sources[0x4e]	430	1		T8	1		T38	1		T29	2
valid_sources[0x4f]	605	1		T8	2		T38	3		T17	1
valid_sources[0x50]	631	1		T8	6		T38	4		T236	8
valid_sources[0x51]	548	1		T8	7		T28	1		T23	1
valid_sources[0x52]	1553	1		T8	6		T38	2		T237	5
valid_sources[0x53]	618	1		T8	7		T11	1		T38	4
valid_sources[0x54]	572	1		T8	6		T60	1		T38	6
valid_sources[0x55]	581	1		T8	3		T38	6		T102	1
valid_sources[0x56]	617	1		T8	2		T38	2		T115	1
valid_sources[0x57]	865	1		T8	4		T38	5		T238	1
valid_sources[0x58]	524	1		T8	3		T38	3		T93	1
valid_sources[0x59]	573	1		T8	3		T13	2		T38	2
valid_sources[0x5a]	480	1		T8	2		T38	6		T120	1
valid_sources[0x5b]	614	1		T8	6		T10	1		T38	6
valid_sources[0x5c]	712	1		T8	13		T38	3		T17	2
valid_sources[0x5d]	645	1		T8	2		T38	4		T122	1
valid_sources[0x5e]	663	1		T8	12		T26	5		T38	3
valid_sources[0x5f]	829	1		T25	1		T38	2		T224	1
valid_sources[0x60]	535	1		T8	2		T38	3		T239	2
valid_sources[0x61]	572	1		T8	3		T12	39		T25	2
valid_sources[0x62]	612	1		T8	4		T38	8		T127	1
valid_sources[0x63]	490	1		T8	1		T38	4		T240	1
valid_sources[0x64]	413	1		T8	4		T38	4		T225	1
valid_sources[0x65]	443	1		T8	2		T11	2		T38	1
valid_sources[0x66]	630	1		T8	4		T26	8		T38	1
valid_sources[0x67]	520	1		T8	4		T10	1		T28	1
valid_sources[0x68]	461	1		T8	2		T38	3		T241	1
valid_sources[0x69]	616	1		T8	4		T242	1		T225	1
valid_sources[0x6a]	659	1		T8	2		T38	6		T127	1
valid_sources[0x6b]	511	1		T2	1		T8	1		T11	4
valid_sources[0x6c]	512	1		T8	4		T25	1		T38	7
valid_sources[0x6d]	486	1		T8	6		T10	1		T38	3
valid_sources[0x6e]	834	1		T2	1		T8	1		T38	3
valid_sources[0x6f]	699	1		T8	8		T43	1		T38	1
valid_sources[0x70]	629	1		T8	6		T38	5		T226	18
valid_sources[0x71]	1155	1		T8	2		T10	1		T38	2
valid_sources[0x72]	498	1		T8	9		T25	1		T38	5
valid_sources[0x73]	547	1		T8	6		T38	2		T120	1
valid_sources[0x74]	1645	1		T8	4		T38	3		T62	6
valid_sources[0x75]	528	1		T8	2		T38	5		T224	1
valid_sources[0x76]	406	1		T8	3		T11	1		T127	3
valid_sources[0x77]	661	1		T8	6		T38	4		T120	1
valid_sources[0x78]	1033	1		T8	2		T28	1		T38	3
valid_sources[0x79]	1523	1		T10	1		T38	5		T121	1
valid_sources[0x7a]	511	1		T8	7		T38	6		T62	1
valid_sources[0x7b]	502	1		T8	4		T38	2		T22	1
valid_sources[0x7c]	530	1		T8	1		T38	4		T228	1
valid_sources[0x7d]	604	1		T8	6		T38	9		T93	1
valid_sources[0x7e]	614	1		T8	10		T25	1		T26	3
valid_sources[0x7f]	720	1		T8	1		T38	1		T243	1
valid_sources[0x80]	528	1		T8	4		T38	1		T102	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28279

1

T1

3

T3

3

T5

1

values[0x0]

all_enables

biggest_size

26331

1

T1

3

T2

3

T3

4

values[0x1]

all_enables

biggest_size

21562

1

T1

2

T2

1

T3

1