Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	95091	1		T1	3		T2	6		T3	8
full_word	77025	1		T1	8		T2	4		T3	8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	171906	1		T1	11		T2	10		T3	16
auto[TlIntgErrCmd]	63	1		T50	3		T144	9		T161	4
auto[TlIntgErrData]	75	1		T50	4		T144	6		T161	9
auto[TlIntgErrBoth]	72	1		T50	3		T144	5		T161	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	80476	1		T1	5		T2	3		T3	6
auto[1]	91640	1		T1	6		T2	7		T3	10

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	51959	1		T1	2		T2	3		T3	3
auto[TlIntgErrNone]	partial	auto[1]	42944	1		T1	1		T2	3		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	28423	1		T1	3		T3	3		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	48580	1		T1	5		T2	4		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	21	1		T50	2		T144	2		T161	1
auto[TlIntgErrCmd]	partial	auto[1]	34	1		T144	6		T161	3		T201	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T144	1		T219	1		T220	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T50	1		T218	1		T221	1
auto[TlIntgErrData]	partial	auto[0]	34	1		T50	1		T144	2		T161	3
auto[TlIntgErrData]	partial	auto[1]	35	1		T50	3		T144	3		T161	5
auto[TlIntgErrData]	full_word	auto[0]	3	1		T161	1		T218	1		T221	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T144	1		T219	1		T218	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T50	2		T144	1		T161	2
auto[TlIntgErrBoth]	partial	auto[1]	37	1		T50	1		T144	4		T161	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T219	1		T221	1		T222	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T161	1		T201	1		T217	1