Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.08	96.75	67.23	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	217646856	11012	0	0
ep_in_enable_rd_A	217646856	1477	0	0
ep_out_enable_rd_A	217646856	1503	0	0
in_iso_rd_A	217646856	1281	0	0
intr_enable_rd_A	217646856	2143	0	0
out_iso_rd_A	217646856	1755	0	0
phy_config_rd_A	217646856	844	0	0
phy_pins_drive_rd_A	217646856	1156	0	0
rxenable_setup_rd_A	217646856	1480	0	0
set_nak_out_rd_A	217646856	1326	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217646856	11012	0	0
T40	2917	332	0	0
T41	9748	682	0	0
T42	11518	1090	0	0
T50	16362	2	0	0
T137	2188	190	0	0
T138	13964	855	0	0
T139	4118	173	0	0
T140	11470	752	0	0
T141	6959	376	0	0
T144	12535	1	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217646856	1477	0	0
T50	16362	196	0	0
T51	4699	24	0	0
T53	2276	29	0	0
T153	3918	103	0	0
T197	4202	8	0	0
T198	2628	47	0	0
T199	4210	5	0	0
T200	2463	3	0	0
T201	16570	361	0	0
T202	7563	100	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217646856	1503	0	0
T50	16362	242	0	0
T51	4699	36	0	0
T53	2276	13	0	0
T153	3918	52	0	0
T197	4202	65	0	0
T198	2628	41	0	0
T199	4210	16	0	0
T200	2463	63	0	0
T201	16570	226	0	0
T202	7563	49	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217646856	1281	0	0
T50	16362	184	0	0
T51	4699	39	0	0
T138	13964	1	0	0
T153	3918	2	0	0
T197	4202	5	0	0
T198	2628	4	0	0
T199	4210	10	0	0
T200	2463	56	0	0
T201	16570	233	0	0
T202	7563	24	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217646856	2143	0	0
T50	16362	361	0	0
T51	4699	51	0	0
T53	2276	31	0	0
T55	1274	17	0	0
T57	1287	6	0	0
T142	14285	1	0	0
T197	4202	85	0	0
T203	1366	23	0	0
T204	1192	11	0	0
T205	1268	5	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217646856	1755	0	0
T50	16362	384	0	0
T51	4699	2	0	0
T53	2276	25	0	0
T153	3918	42	0	0
T197	4202	11	0	0
T198	2628	44	0	0
T199	4210	17	0	0
T200	2463	38	0	0
T201	16570	338	0	0
T202	7563	19	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217646856	844	0	0
T50	16362	148	0	0
T51	4699	10	0	0
T53	2276	16	0	0
T153	3918	8	0	0
T197	4202	22	0	0
T198	2628	22	0	0
T200	2463	5	0	0
T201	16570	192	0	0
T202	7563	24	0	0
T206	3888	3	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217646856	1156	0	0
T50	16362	167	0	0
T51	4699	36	0	0
T53	2276	21	0	0
T141	6959	3	0	0
T142	14285	5	0	0
T197	4202	9	0	0
T198	2628	29	0	0
T200	2463	6	0	0
T201	16570	199	0	0
T202	7563	63	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217646856	1480	0	0
T50	16362	234	0	0
T51	4699	30	0	0
T53	2276	23	0	0
T153	3918	50	0	0
T197	4202	34	0	0
T198	2628	6	0	0
T199	4210	11	0	0
T200	2463	58	0	0
T201	16570	235	0	0
T202	7563	39	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217646856	1326	0	0
T50	16362	292	0	0
T51	4699	15	0	0
T53	2276	5	0	0
T138	13964	6	0	0
T197	4202	4	0	0
T198	2628	57	0	0
T199	4210	1	0	0
T200	2463	5	0	0
T201	16570	293	0	0
T202	7563	14	0	0