Unified Coverage Report :: Module :: usb_fs_nb_in_pe

Module : usb_fs_nb_in_pe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.90	85.71	82.19		50.00	76.60	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe	78.90	85.71	82.19		50.00	76.60	100.00

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.90	85.71	82.19		50.00	76.60	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.90	85.71	82.19		50.00	76.60	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	50.00				100.00	u_usb_fs_nb_pe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_nb_in_pe

	Line No.	Total	Covered	Percent
TOTAL		112	96	85.71
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
ALWAYS	185	49	34	69.39
ALWAYS	287	3	3	100.00
ALWAYS	295	3	3	100.00
ALWAYS	303	8	8	100.00
ALWAYS	316	6	6	100.00
ALWAYS	328	9	9	100.00
ALWAYS	345	7	6	85.71
CONT_ASSIGN	359	1	1	100.00
ALWAYS	362	5	5	100.00
ALWAYS	372	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
125	1	1
126	1	1
128	1	1
134	1	1
138	1	1
142	1	1
148	1	1
149	1	1
156	1	1
157	1	1
160	1	1
166	1	1
168	1	1
174	1	1
175	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
197	1	1
202	1	1
204	1	1
209	0	1
210	0	1
211	1	1
212	0	1
213	0	1
214	1	1
215	1	1
216	1	1
218	0	1
219	0	1
225	1	1
226	1	1
227	0	1
228	0	1
230	1	1
231	0	1
233	1	1
237	1	1
242	1	1
243	1	1
			MISSING_ELSE
251	1	1
253	1	1
254	1	1
255	1	1
256	0	1
257	0	1
259	1	1
264	1	1
265	1	1
266	1	1
267	1	1
268	0	1
269	0	1
270	1	1
271	0	1
272	0	1
274	1	1
287	1	1
288	1	1
290	1	1
295	1	1
296	1	1
298	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
310	1	1
311	1	1
316	1	1
317	1	1
319	1	1
320	1	1
321	1	1
322	1	1
			MISSING_ELSE
328	1	1
329	1	1
330	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
338	1	1
345	1	1
347	1	1
348	1	1
349	1	1
350	1	1
			MISSING_ELSE
353	1	1
354	0	1
			MISSING_ELSE
359	1	1
362	1	1
363	1	1
364	1	1
365	1	1
367	1	1
372	1	1
373	1	1
375	1	1
376	1	1
378	1	1

---

Cond Coverage for Module : usb_fs_nb_in_pe

	Total	Covered	Percent
Conditions	73	60	82.19
Logical	73	60	82.19
Non-Logical	0	0
Event	0	0

 LINE       128
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Not Covered
1	1	0	1	Covered	T1,T2,T3
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       128
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       134
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T12

 LINE       134
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T12

 LINE       138
 EXPRESSION (token_received && (rx_pid == UsbPidIn))
             -------1------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T10

 LINE       138
 SUB-EXPRESSION (rx_pid == UsbPidIn)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T10

 LINE       142
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidAck))
             ------1-----    -------2------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T7,T10
1	0	1	Not Covered
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T6,T7,T10

 LINE       142
 SUB-EXPRESSION (rx_pid == UsbPidAck)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T10

 LINE       149
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (in_ep_enabled_i[in_ep_index_d] & ep_in_hw)
             ---------------1--------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T10

 LINE       166
 EXPRESSION (has_data_q & ((~in_ep_data_done_i[in_ep_index])))
             -----1----   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T10,T20,T21
1	1	Covered	T6,T7,T10

 LINE       168
 EXPRESSION ((logic'((in_xact_state == StSendData))) & more_data_to_send)
             -------------------1-------------------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Covered	T10,T20,T21
1	1	Covered	T6,T7,T10

 LINE       174
 EXPRESSION (ep_active && in_token_received)
             ----1----    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       193
 EXPRESSION (ep_active && in_token_received)
             ----1----    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       225
 EXPRESSION (((!more_data_to_send)) || (((&in_ep_get_addr_o)) && tx_data_get_i))
             -----------1----------    --------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T10
0	1	Covered	T6,T7,T12
1	0	Covered	T10,T20,T21

 LINE       225
 SUB-EXPRESSION (((&in_ep_get_addr_o)) && tx_data_get_i)
                 ----------1----------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Covered	T6,T7,T12
1	1	Covered	T6,T7,T12

 LINE       255
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------

-1-	Status	Tests
0	Covered	T6,T7,T10
1	Not Covered

 LINE       306
 EXPRESSION (link_reset_i || ((!link_active_i)))
             ------1-----    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       319
 EXPRESSION (in_xact_state == StIdle)
            ------------1------------

-1-	Status	Tests
0	Covered	T6,T7,T10
1	Covered	T1,T2,T3

 LINE       321
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       321
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T6,T7,T10
1	Covered	T6,T7,T10

 LINE       347
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T10
1	0	Covered	T13,T14,T15
1	1	Covered	T6,T7,T12

 LINE       349
 EXPRESSION ((in_xact_state == StWaitAck) && ack_received)
             --------------1-------------    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       349
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T10

 LINE       375
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T10
1	1	Covered	T6,T7,T10

 LINE       375
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T10

---

FSM Coverage for Module : usb_fs_nb_in_pe

Summary for FSM :: in_xact_state

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	12	6	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: in_xact_state

---

states	Line No.	Covered	Tests
StIdle	307	Covered	T1,T2,T3
StRcvdIn	194	Covered	T6,T7,T10
StSendData	209	Covered	T6,T7,T10
StWaitAck	254	Covered	T6,T7,T10
StWaitAckStart	231	Covered	T6,T7,T10
StWaitTxEnd	233	Covered	T6,T7,T10

transitions	Line No.	Covered	Tests
StIdle->StRcvdIn	194	Covered	T6,T7,T10
StRcvdIn->StIdle	307	Not Covered
StRcvdIn->StSendData	209	Covered	T6,T7,T10
StSendData->StIdle	307	Not Covered
StSendData->StWaitAckStart	231	Not Covered
StSendData->StWaitTxEnd	233	Covered	T6,T7,T10
StWaitAck->StIdle	307	Covered	T6,T7,T10
StWaitAck->StRcvdIn	268	Not Covered
StWaitAckStart->StIdle	307	Not Covered
StWaitAckStart->StWaitAck	254	Covered	T6,T7,T10
StWaitTxEnd->StIdle	307	Not Covered
StWaitTxEnd->StWaitAckStart	243	Covered	T6,T7,T10

---

Branch Coverage for Module : usb_fs_nb_in_pe

	Line No.	Total	Covered	Percent
Branches		47	36	76.60
TERNARY	149	2	1	50.00
CASE	191	20	11	55.00
IF	287	2	2	100.00
IF	295	2	2	100.00
IF	303	3	3	100.00
IF	316	4	4	100.00
IF	328	3	3	100.00
IF	347	3	3	100.00
IF	353	2	1	50.00
IF	362	3	3	100.00
IF	372	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	149	(ep_in_hw) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	191	case (in_xact_state)
-2-:	193	if ((ep_active && in_token_received))
-3-:	204	if (in_ep_iso_i[in_ep_index])
-4-:	211	if (in_ep_stall_i[in_ep_index])
-5-:	214	if (has_data_q)
-6-:	225	if (((!more_data_to_send) || ((&in_ep_get_addr_o) && tx_data_get_i)))
-7-:	226	if (in_ep_iso_i[in_ep_index])
-8-:	230	if (tx_pkt_end_i)
-9-:	242	if (tx_pkt_end_i)
-10-:	253	if (rx_pkt_start_i)
-11-:	255	if ((timeout_cntdown_q == '0))
-12-:	264	if (ack_received)
-13-:	267	if (in_token_received)
-14-:	270	if (rx_pkt_end_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRcvdIn	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRcvdIn	-	0	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StRcvdIn	-	0	0	1	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
StRcvdIn	-	0	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StSendData	-	-	-	-	1	1	-	-	-	-	-	-	-	Not Covered
StSendData	-	-	-	-	1	0	1	-	-	-	-	-	-	Not Covered
StSendData	-	-	-	-	1	0	0	-	-	-	-	-	-	Covered	T6,T7,T10
StSendData	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T6,T7,T10
StWaitTxEnd	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T6,T7,T10
StWaitTxEnd	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T6,T7,T10
StWaitAckStart	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T7,T10
StWaitAckStart	-	-	-	-	-	-	-	-	0	1	-	-	-	Not Covered
StWaitAckStart	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T7,T10
StWaitAck	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T6,T7,T10
StWaitAck	-	-	-	-	-	-	-	-	-	-	0	1	-	Not Covered
StWaitAck	-	-	-	-	-	-	-	-	-	-	0	0	1	Not Covered
StWaitAck	-	-	-	-	-	-	-	-	-	-	0	0	0	Covered	T6,T7,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	287	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	295	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))
-2-:	306	if ((link_reset_i || (!link_active_i)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	316	if ((!rst_ni))
-2-:	319	if ((in_xact_state == StIdle))
-3-:	321	if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T6,T7,T10
0	0	0	Covered	T6,T7,T10

	LineNo.	Expression
-1-:	328	if ((!rst_ni))
-2-:	333	if (in_token_received)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T7,T10
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	347	if ((setup_token_received && ep_active))
-2-:	349	if (((in_xact_state == StWaitAck) && ack_received))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T12
0	1	Covered	T6,T7,T10
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	353	if (in_datatog_we_i)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	362	if ((!rst_ni))
-2-:	364	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	372	if ((!rst_ni))
-2-:	375	if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T7,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usb_fs_nb_in_pe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
InXactStateValid_A	216880923	216786888	0	0

InXactStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216880923	216786888	0	0
T1	401649	401462	0	0
T2	402059	401893	0	0
T3	403729	403567	0	0
T5	403429	403378	0	0
T6	406890	406725	0	0
T7	406744	406483	0	0
T8	8361	8275	0	0
T9	403118	403043	0	0
T10	403405	403285	0	0
T11	1103	967	0	0