Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.91 96.34 88.43 97.17 45.31 94.22 97.36 96.58


Total test records in report: 801
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T758 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.398566783 Mar 12 01:02:22 PM PDT 24 Mar 12 01:02:22 PM PDT 24 26354098 ps
T157 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3062779206 Mar 12 01:01:53 PM PDT 24 Mar 12 01:01:54 PM PDT 24 77362427 ps
T759 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2667781371 Mar 12 01:02:09 PM PDT 24 Mar 12 01:02:12 PM PDT 24 78271645 ps
T760 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2318441105 Mar 12 01:02:20 PM PDT 24 Mar 12 01:02:20 PM PDT 24 19405595 ps
T761 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1775842844 Mar 12 01:02:00 PM PDT 24 Mar 12 01:02:07 PM PDT 24 43140860 ps
T762 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2314255292 Mar 12 01:01:51 PM PDT 24 Mar 12 01:01:53 PM PDT 24 92277967 ps
T221 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1674754977 Mar 12 01:01:59 PM PDT 24 Mar 12 01:02:03 PM PDT 24 337458244 ps
T763 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2217485943 Mar 12 01:02:23 PM PDT 24 Mar 12 01:02:24 PM PDT 24 24540253 ps
T764 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1675106721 Mar 12 01:01:57 PM PDT 24 Mar 12 01:01:58 PM PDT 24 27875216 ps
T765 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.553832505 Mar 12 01:01:55 PM PDT 24 Mar 12 01:01:58 PM PDT 24 151406445 ps
T766 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1281592455 Mar 12 01:02:11 PM PDT 24 Mar 12 01:02:17 PM PDT 24 29143721 ps
T767 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3193582250 Mar 12 01:02:07 PM PDT 24 Mar 12 01:02:08 PM PDT 24 80107926 ps
T768 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.829638773 Mar 12 01:01:52 PM PDT 24 Mar 12 01:01:53 PM PDT 24 42534603 ps
T769 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3136303703 Mar 12 01:01:49 PM PDT 24 Mar 12 01:01:51 PM PDT 24 79301732 ps
T770 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3188939784 Mar 12 01:02:04 PM PDT 24 Mar 12 01:02:05 PM PDT 24 19881817 ps
T771 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3518519191 Mar 12 01:02:17 PM PDT 24 Mar 12 01:02:19 PM PDT 24 158716205 ps
T772 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3763303134 Mar 12 01:02:01 PM PDT 24 Mar 12 01:02:03 PM PDT 24 83656036 ps
T158 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.708918501 Mar 12 01:01:56 PM PDT 24 Mar 12 01:01:58 PM PDT 24 63191841 ps
T773 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.486297131 Mar 12 01:02:23 PM PDT 24 Mar 12 01:02:24 PM PDT 24 23893930 ps
T774 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3666614354 Mar 12 01:02:02 PM PDT 24 Mar 12 01:02:03 PM PDT 24 29751183 ps
T48 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3370699186 Mar 12 01:01:47 PM PDT 24 Mar 12 01:01:47 PM PDT 24 39104349 ps
T775 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4288146862 Mar 12 01:01:54 PM PDT 24 Mar 12 01:01:56 PM PDT 24 61083644 ps
T776 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2955573609 Mar 12 01:01:51 PM PDT 24 Mar 12 01:01:53 PM PDT 24 95837619 ps
T777 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2049047372 Mar 12 01:01:53 PM PDT 24 Mar 12 01:01:57 PM PDT 24 92345180 ps
T778 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.342782988 Mar 12 01:02:08 PM PDT 24 Mar 12 01:02:10 PM PDT 24 83448723 ps
T220 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.86281858 Mar 12 01:01:56 PM PDT 24 Mar 12 01:02:01 PM PDT 24 267975813 ps
T52 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3418801381 Mar 12 01:01:57 PM PDT 24 Mar 12 01:01:58 PM PDT 24 33962368 ps
T779 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.457223066 Mar 12 01:01:51 PM PDT 24 Mar 12 01:01:54 PM PDT 24 331959148 ps
T780 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1029805147 Mar 12 01:02:19 PM PDT 24 Mar 12 01:02:20 PM PDT 24 93114895 ps
T781 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.232568887 Mar 12 01:02:12 PM PDT 24 Mar 12 01:02:15 PM PDT 24 140632842 ps
T782 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3523631117 Mar 12 01:01:50 PM PDT 24 Mar 12 01:01:55 PM PDT 24 201593416 ps
T783 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2595137708 Mar 12 01:02:07 PM PDT 24 Mar 12 01:02:08 PM PDT 24 30333574 ps
T784 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3863229802 Mar 12 01:02:23 PM PDT 24 Mar 12 01:02:25 PM PDT 24 127783011 ps
T785 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2470405847 Mar 12 01:01:53 PM PDT 24 Mar 12 01:01:54 PM PDT 24 22916756 ps
T786 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3762050894 Mar 12 01:02:00 PM PDT 24 Mar 12 01:02:01 PM PDT 24 70211447 ps
T787 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1004421645 Mar 12 01:01:50 PM PDT 24 Mar 12 01:01:52 PM PDT 24 63096165 ps
T788 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2260177486 Mar 12 01:02:03 PM PDT 24 Mar 12 01:02:05 PM PDT 24 39423205 ps
T789 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1240197181 Mar 12 01:02:05 PM PDT 24 Mar 12 01:02:07 PM PDT 24 23416248 ps
T790 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2139229708 Mar 12 01:02:01 PM PDT 24 Mar 12 01:02:04 PM PDT 24 66684374 ps
T791 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3809802915 Mar 12 01:02:02 PM PDT 24 Mar 12 01:02:05 PM PDT 24 118998063 ps
T792 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.185997942 Mar 12 01:02:01 PM PDT 24 Mar 12 01:02:03 PM PDT 24 20156537 ps
T222 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4288652116 Mar 12 01:02:09 PM PDT 24 Mar 12 01:02:12 PM PDT 24 139369508 ps
T793 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4126600564 Mar 12 01:02:14 PM PDT 24 Mar 12 01:02:15 PM PDT 24 57652245 ps
T794 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1606249370 Mar 12 01:01:49 PM PDT 24 Mar 12 01:01:50 PM PDT 24 27648807 ps
T795 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2723354116 Mar 12 01:02:18 PM PDT 24 Mar 12 01:02:19 PM PDT 24 70480310 ps
T796 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2342379423 Mar 12 01:02:18 PM PDT 24 Mar 12 01:02:21 PM PDT 24 140780881 ps
T797 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3044314031 Mar 12 01:02:15 PM PDT 24 Mar 12 01:02:16 PM PDT 24 26931814 ps
T798 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4256310818 Mar 12 01:01:57 PM PDT 24 Mar 12 01:01:59 PM PDT 24 153130374 ps
T799 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1693901735 Mar 12 01:02:08 PM PDT 24 Mar 12 01:02:09 PM PDT 24 24070406 ps
T800 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3021054980 Mar 12 01:02:03 PM PDT 24 Mar 12 01:02:05 PM PDT 24 110677717 ps
T801 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2020381596 Mar 12 01:02:18 PM PDT 24 Mar 12 01:02:19 PM PDT 24 32150949 ps

Test location /workspace/coverage/default/35.usbdev_smoke.3250052316
Short name T6
Test name
Test status
Simulation time 8476755645 ps
CPU time 9.64 seconds
Started Mar 12 02:58:53 PM PDT 24
Finished Mar 12 02:59:03 PM PDT 24
Peak memory 203076 kb
Host smart-f03dae72-9779-4f86-9342-c42134f826b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32500
52316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3250052316
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2881889908
Short name T54
Test name
Test status
Simulation time 22667137 ps
CPU time 0.63 seconds
Started Mar 12 01:02:21 PM PDT 24
Finished Mar 12 01:02:22 PM PDT 24
Peak memory 201968 kb
Host smart-ddffd729-5075-4f10-ba8e-589b4f68206f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2881889908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2881889908
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2025821674
Short name T8
Test name
Test status
Simulation time 174212085 ps
CPU time 1.87 seconds
Started Mar 12 02:58:20 PM PDT 24
Finished Mar 12 02:58:22 PM PDT 24
Peak memory 203108 kb
Host smart-c480ad0c-ca7a-4fd2-8b7e-636c6bfa2f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20258
21674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2025821674
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.304813250
Short name T50
Test name
Test status
Simulation time 340882544 ps
CPU time 3.24 seconds
Started Mar 12 01:01:53 PM PDT 24
Finished Mar 12 01:01:57 PM PDT 24
Peak memory 202696 kb
Host smart-a04feea9-dbef-4c9a-9a00-d8e80aab10dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=304813250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.304813250
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.397999235
Short name T211
Test name
Test status
Simulation time 22345603 ps
CPU time 0.64 seconds
Started Mar 12 01:02:23 PM PDT 24
Finished Mar 12 01:02:23 PM PDT 24
Peak memory 201940 kb
Host smart-6269e19a-6a4a-4b08-8aca-1f5086900dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=397999235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.397999235
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.766305740
Short name T41
Test name
Test status
Simulation time 203105850 ps
CPU time 2.79 seconds
Started Mar 12 01:02:21 PM PDT 24
Finished Mar 12 01:02:24 PM PDT 24
Peak memory 202732 kb
Host smart-fc03a2d7-a60a-47a1-b881-2224c9ee3c25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=766305740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.766305740
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2079217266
Short name T43
Test name
Test status
Simulation time 265357041 ps
CPU time 1.17 seconds
Started Mar 12 02:56:56 PM PDT 24
Finished Mar 12 02:56:59 PM PDT 24
Peak memory 218584 kb
Host smart-04b9079f-8667-424a-ba13-9b373e877d99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2079217266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2079217266
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.817628815
Short name T16
Test name
Test status
Simulation time 8417127028 ps
CPU time 7.96 seconds
Started Mar 12 02:58:03 PM PDT 24
Finished Mar 12 02:58:11 PM PDT 24
Peak memory 202960 kb
Host smart-2e96a00d-15ee-4a8b-8a51-e1c357f6ebe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81762
8815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.817628815
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3828973512
Short name T162
Test name
Test status
Simulation time 63680481 ps
CPU time 1.83 seconds
Started Mar 12 02:57:31 PM PDT 24
Finished Mar 12 02:57:34 PM PDT 24
Peak memory 202996 kb
Host smart-d1285d32-77fe-446b-bbc7-4d5f2ddd1418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38289
73512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3828973512
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.77351965
Short name T280
Test name
Test status
Simulation time 27506422 ps
CPU time 0.66 seconds
Started Mar 12 02:56:58 PM PDT 24
Finished Mar 12 02:57:00 PM PDT 24
Peak memory 202944 kb
Host smart-bc71ef0f-bfea-42fc-a8b9-75b494d839ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77351
965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.77351965
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1689076143
Short name T51
Test name
Test status
Simulation time 97930023 ps
CPU time 1.14 seconds
Started Mar 12 01:02:19 PM PDT 24
Finished Mar 12 01:02:20 PM PDT 24
Peak memory 202708 kb
Host smart-dbc32a46-9b31-4da2-8ad5-22b1e38bf902
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689076143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_
csr_outstanding.1689076143
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.89881220
Short name T253
Test name
Test status
Simulation time 8401123387 ps
CPU time 7.68 seconds
Started Mar 12 02:56:47 PM PDT 24
Finished Mar 12 02:56:55 PM PDT 24
Peak memory 203020 kb
Host smart-22b77419-a0b7-428b-a62d-2ad2f25a86b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89881
220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.89881220
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3333870233
Short name T108
Test name
Test status
Simulation time 8460576462 ps
CPU time 8.69 seconds
Started Mar 12 02:58:20 PM PDT 24
Finished Mar 12 02:58:29 PM PDT 24
Peak memory 203028 kb
Host smart-7807c606-8ed6-477b-a92e-29d0003bcfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33338
70233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3333870233
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4283711428
Short name T55
Test name
Test status
Simulation time 26564422 ps
CPU time 0.63 seconds
Started Mar 12 01:02:15 PM PDT 24
Finished Mar 12 01:02:16 PM PDT 24
Peak memory 202000 kb
Host smart-a1fba5a0-203e-4b8b-ba52-07f756ca40f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4283711428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4283711428
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1284109002
Short name T49
Test name
Test status
Simulation time 33909101 ps
CPU time 0.99 seconds
Started Mar 12 01:02:14 PM PDT 24
Finished Mar 12 01:02:15 PM PDT 24
Peak memory 202640 kb
Host smart-2dc3fc79-cc12-4106-9edc-9dabb686f55f
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284109002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1284109002
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2936918004
Short name T103
Test name
Test status
Simulation time 8408383045 ps
CPU time 7.92 seconds
Started Mar 12 02:58:43 PM PDT 24
Finished Mar 12 02:58:52 PM PDT 24
Peak memory 202936 kb
Host smart-ba63e158-9db5-4086-a17a-d51ef8f36b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29369
18004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2936918004
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_smoke.893185219
Short name T132
Test name
Test status
Simulation time 8475685390 ps
CPU time 8.85 seconds
Started Mar 12 02:59:03 PM PDT 24
Finished Mar 12 02:59:12 PM PDT 24
Peak memory 203040 kb
Host smart-668a78d9-9d5e-4b8b-80a5-425fef423da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89318
5219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.893185219
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3244134305
Short name T135
Test name
Test status
Simulation time 8479429824 ps
CPU time 7.27 seconds
Started Mar 12 02:56:48 PM PDT 24
Finished Mar 12 02:56:56 PM PDT 24
Peak memory 202928 kb
Host smart-571cc5f4-38d4-42a3-a9df-26f28c9444f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32441
34305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3244134305
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_smoke.894656930
Short name T114
Test name
Test status
Simulation time 8473412913 ps
CPU time 7.65 seconds
Started Mar 12 02:57:32 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 202284 kb
Host smart-c3246476-6e10-41cb-a7e2-d6a8eb54b7d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89465
6930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.894656930
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_smoke.965161517
Short name T136
Test name
Test status
Simulation time 8477003602 ps
CPU time 9.23 seconds
Started Mar 12 02:58:26 PM PDT 24
Finished Mar 12 02:58:35 PM PDT 24
Peak memory 203048 kb
Host smart-5d82f57f-0ab4-4d5e-a7da-1f9ff4c8f47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96516
1517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.965161517
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_smoke.4030156697
Short name T486
Test name
Test status
Simulation time 8480283606 ps
CPU time 8.75 seconds
Started Mar 12 02:58:46 PM PDT 24
Finished Mar 12 02:58:55 PM PDT 24
Peak memory 203024 kb
Host smart-25d97508-ad19-4db6-8580-7dea66cb315e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40301
56697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.4030156697
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2284671032
Short name T27
Test name
Test status
Simulation time 8475429524 ps
CPU time 8.04 seconds
Started Mar 12 02:56:46 PM PDT 24
Finished Mar 12 02:56:55 PM PDT 24
Peak memory 203028 kb
Host smart-f15b0637-d1c1-45d7-b19f-9364a616c1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22846
71032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2284671032
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2311523826
Short name T111
Test name
Test status
Simulation time 8475455355 ps
CPU time 7.98 seconds
Started Mar 12 02:58:15 PM PDT 24
Finished Mar 12 02:58:23 PM PDT 24
Peak memory 203040 kb
Host smart-4b7966f2-7822-4a5c-a191-0980a629caad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23115
23826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2311523826
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1656528265
Short name T161
Test name
Test status
Simulation time 270470456 ps
CPU time 4.51 seconds
Started Mar 12 01:02:20 PM PDT 24
Finished Mar 12 01:02:30 PM PDT 24
Peak memory 202624 kb
Host smart-faead259-07ab-4e8f-959a-4fd960b1697b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1656528265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1656528265
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2255145934
Short name T215
Test name
Test status
Simulation time 22736757 ps
CPU time 0.6 seconds
Started Mar 12 01:02:06 PM PDT 24
Finished Mar 12 01:02:07 PM PDT 24
Peak memory 201908 kb
Host smart-a61852d6-020d-4f95-8926-303bf4b17fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2255145934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2255145934
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1110530732
Short name T102
Test name
Test status
Simulation time 8471681165 ps
CPU time 7.3 seconds
Started Mar 12 02:58:59 PM PDT 24
Finished Mar 12 02:59:06 PM PDT 24
Peak memory 203024 kb
Host smart-c97c732b-3c33-491f-8756-b14f2124a342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11105
30732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1110530732
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1425014043
Short name T219
Test name
Test status
Simulation time 239524962 ps
CPU time 4.27 seconds
Started Mar 12 01:01:48 PM PDT 24
Finished Mar 12 01:01:53 PM PDT 24
Peak memory 202736 kb
Host smart-03af25bb-9054-4b01-9399-350738ae429c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1425014043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1425014043
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2901896704
Short name T46
Test name
Test status
Simulation time 52655665 ps
CPU time 0.9 seconds
Started Mar 12 01:02:12 PM PDT 24
Finished Mar 12 01:02:14 PM PDT 24
Peak memory 202440 kb
Host smart-69ea7292-a426-48fc-9d07-6f3c4d928879
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901896704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2901896704
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.997340974
Short name T30
Test name
Test status
Simulation time 26356351 ps
CPU time 0.66 seconds
Started Mar 12 02:57:42 PM PDT 24
Finished Mar 12 02:57:43 PM PDT 24
Peak memory 202912 kb
Host smart-f19f7b7a-f740-40bd-b961-d53c2c957129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99734
0974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.997340974
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3637165317
Short name T123
Test name
Test status
Simulation time 8471194336 ps
CPU time 7.37 seconds
Started Mar 12 02:57:49 PM PDT 24
Finished Mar 12 02:57:56 PM PDT 24
Peak memory 203004 kb
Host smart-2d1d99ae-feec-44a5-9a06-bf3fcbf6109e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36371
65317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3637165317
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.666536476
Short name T171
Test name
Test status
Simulation time 206009932 ps
CPU time 2.23 seconds
Started Mar 12 02:58:53 PM PDT 24
Finished Mar 12 02:58:55 PM PDT 24
Peak memory 203072 kb
Host smart-9d2b819c-6cc0-4a4c-90dc-38370abf3d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66653
6476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.666536476
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2088209922
Short name T727
Test name
Test status
Simulation time 29774671 ps
CPU time 0.66 seconds
Started Mar 12 01:02:18 PM PDT 24
Finished Mar 12 01:02:18 PM PDT 24
Peak memory 201912 kb
Host smart-05ecb691-0729-444d-ac4f-7c79b7f8de0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2088209922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2088209922
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1838959469
Short name T201
Test name
Test status
Simulation time 345227122 ps
CPU time 3.18 seconds
Started Mar 12 01:02:03 PM PDT 24
Finished Mar 12 01:02:07 PM PDT 24
Peak memory 202668 kb
Host smart-e5e6e9b3-8475-402c-86ad-5f0d3a2a673a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1838959469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1838959469
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.378754192
Short name T723
Test name
Test status
Simulation time 148633467 ps
CPU time 1.78 seconds
Started Mar 12 01:02:29 PM PDT 24
Finished Mar 12 01:02:31 PM PDT 24
Peak memory 202640 kb
Host smart-1d0c5e81-738d-417f-9277-36b2160b7d0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=378754192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.378754192
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2907825939
Short name T167
Test name
Test status
Simulation time 169750969 ps
CPU time 2.05 seconds
Started Mar 12 02:58:41 PM PDT 24
Finished Mar 12 02:58:44 PM PDT 24
Peak memory 203028 kb
Host smart-35dbac2c-5fd5-4ff7-b9c2-4d4178bac67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29078
25939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2907825939
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2773045573
Short name T242
Test name
Test status
Simulation time 8359662874 ps
CPU time 7.4 seconds
Started Mar 12 02:56:49 PM PDT 24
Finished Mar 12 02:56:57 PM PDT 24
Peak memory 203008 kb
Host smart-5ae37f6b-23cc-4f5b-85b2-e0e8dadd187b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27730
45573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2773045573
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.428730494
Short name T509
Test name
Test status
Simulation time 8476490290 ps
CPU time 7.42 seconds
Started Mar 12 02:57:30 PM PDT 24
Finished Mar 12 02:57:39 PM PDT 24
Peak memory 203056 kb
Host smart-a622901c-e65f-42ec-81be-d6950118724b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42873
0494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.428730494
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3810736813
Short name T126
Test name
Test status
Simulation time 8474076044 ps
CPU time 9.09 seconds
Started Mar 12 02:57:39 PM PDT 24
Finished Mar 12 02:57:48 PM PDT 24
Peak memory 203052 kb
Host smart-a18af6c6-92fd-499c-b1c3-672592acc82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38107
36813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3810736813
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3282656151
Short name T145
Test name
Test status
Simulation time 192322077 ps
CPU time 4.77 seconds
Started Mar 12 01:02:04 PM PDT 24
Finished Mar 12 01:02:09 PM PDT 24
Peak memory 202692 kb
Host smart-a9189fe7-4e74-4d19-bd15-a5aa75a5ba31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282656151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3282656151
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3673186090
Short name T95
Test name
Test status
Simulation time 8424799330 ps
CPU time 7.98 seconds
Started Mar 12 02:56:44 PM PDT 24
Finished Mar 12 02:56:52 PM PDT 24
Peak memory 202972 kb
Host smart-76b17a27-9b5e-48ef-a924-b3709c709a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36731
86090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3673186090
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3253975153
Short name T70
Test name
Test status
Simulation time 8378214911 ps
CPU time 7.25 seconds
Started Mar 12 02:56:46 PM PDT 24
Finished Mar 12 02:56:54 PM PDT 24
Peak memory 202992 kb
Host smart-9e9a11df-8d30-4bce-8602-f4d9f41e97c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32539
75153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3253975153
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2904599276
Short name T524
Test name
Test status
Simulation time 8427037421 ps
CPU time 7.29 seconds
Started Mar 12 02:57:16 PM PDT 24
Finished Mar 12 02:57:23 PM PDT 24
Peak memory 202948 kb
Host smart-12bfbe5c-f0d4-408d-9a7e-e7b0b76aed14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29045
99276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2904599276
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.692776795
Short name T87
Test name
Test status
Simulation time 8411246206 ps
CPU time 7.78 seconds
Started Mar 12 02:57:26 PM PDT 24
Finished Mar 12 02:57:35 PM PDT 24
Peak memory 202992 kb
Host smart-295aa1f2-ce59-4f70-a031-0de02afcac78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69277
6795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.692776795
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3747799107
Short name T69
Test name
Test status
Simulation time 8429162386 ps
CPU time 8.65 seconds
Started Mar 12 02:57:29 PM PDT 24
Finished Mar 12 02:57:39 PM PDT 24
Peak memory 202964 kb
Host smart-36503312-3daa-4408-9543-ff73e68bcaf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37477
99107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3747799107
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3629257497
Short name T4
Test name
Test status
Simulation time 8394584236 ps
CPU time 7.58 seconds
Started Mar 12 02:57:32 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 202972 kb
Host smart-03d2d390-02a8-4cbc-9d66-1f30fd8dadeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36292
57497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3629257497
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.821924650
Short name T96
Test name
Test status
Simulation time 8429972608 ps
CPU time 9.4 seconds
Started Mar 12 02:57:36 PM PDT 24
Finished Mar 12 02:57:46 PM PDT 24
Peak memory 202928 kb
Host smart-02b9fd7a-7623-4d5c-9b21-dff57192b8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82192
4650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.821924650
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.303097929
Short name T83
Test name
Test status
Simulation time 8395771870 ps
CPU time 7.71 seconds
Started Mar 12 02:57:35 PM PDT 24
Finished Mar 12 02:57:44 PM PDT 24
Peak memory 202996 kb
Host smart-2a2c745e-33cf-4521-be70-da438c174fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30309
7929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.303097929
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.244377580
Short name T703
Test name
Test status
Simulation time 8396145245 ps
CPU time 10.05 seconds
Started Mar 12 02:56:45 PM PDT 24
Finished Mar 12 02:56:55 PM PDT 24
Peak memory 202956 kb
Host smart-85e58ad9-d430-440f-b419-ecc56b34c58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24437
7580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.244377580
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2361749078
Short name T73
Test name
Test status
Simulation time 8416847907 ps
CPU time 7.34 seconds
Started Mar 12 02:57:55 PM PDT 24
Finished Mar 12 02:58:02 PM PDT 24
Peak memory 202872 kb
Host smart-8d3544ea-d5b0-4ad4-9969-ba69593f3576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23617
49078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2361749078
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.875634878
Short name T84
Test name
Test status
Simulation time 8412302374 ps
CPU time 7.78 seconds
Started Mar 12 02:58:29 PM PDT 24
Finished Mar 12 02:58:37 PM PDT 24
Peak memory 202992 kb
Host smart-04a70233-647f-4f37-b1ac-ae399abf5c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87563
4878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.875634878
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3214506194
Short name T89
Test name
Test status
Simulation time 8421746326 ps
CPU time 7.31 seconds
Started Mar 12 02:59:08 PM PDT 24
Finished Mar 12 02:59:16 PM PDT 24
Peak memory 203008 kb
Host smart-dcc084d0-b481-40f9-ad1a-57413f5ffd73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32145
06194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3214506194
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1702735087
Short name T154
Test name
Test status
Simulation time 334999512 ps
CPU time 3.47 seconds
Started Mar 12 01:01:55 PM PDT 24
Finished Mar 12 01:01:59 PM PDT 24
Peak memory 202616 kb
Host smart-ac75ef79-296a-4fcc-ab94-a41f3343220d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702735087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1702735087
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3580995668
Short name T148
Test name
Test status
Simulation time 363073117 ps
CPU time 8.13 seconds
Started Mar 12 01:01:52 PM PDT 24
Finished Mar 12 01:02:00 PM PDT 24
Peak memory 202612 kb
Host smart-a2eae927-e144-4cc4-940e-da2637f8008b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580995668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3580995668
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3136303703
Short name T769
Test name
Test status
Simulation time 79301732 ps
CPU time 1.15 seconds
Started Mar 12 01:01:49 PM PDT 24
Finished Mar 12 01:01:51 PM PDT 24
Peak memory 202780 kb
Host smart-4a0cd016-19d3-478b-aead-eda39b80455c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136303703 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.usbdev_csr_mem_rw_with_rand_reset.3136303703
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.421820196
Short name T200
Test name
Test status
Simulation time 51322868 ps
CPU time 0.85 seconds
Started Mar 12 01:02:11 PM PDT 24
Finished Mar 12 01:02:12 PM PDT 24
Peak memory 202372 kb
Host smart-69d69145-d67d-4467-814d-9e90d9accb4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421820196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.421820196
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.341079843
Short name T156
Test name
Test status
Simulation time 40557758 ps
CPU time 1.26 seconds
Started Mar 12 01:01:48 PM PDT 24
Finished Mar 12 01:01:50 PM PDT 24
Peak memory 202716 kb
Host smart-204f6e4c-e26c-4b6b-b788-18a3829b1823
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=341079843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.341079843
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3135831322
Short name T748
Test name
Test status
Simulation time 314666790 ps
CPU time 2.31 seconds
Started Mar 12 01:02:10 PM PDT 24
Finished Mar 12 01:02:13 PM PDT 24
Peak memory 202416 kb
Host smart-2856fcea-79d8-4e8c-aa76-cd29a0a9c14d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3135831322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3135831322
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.130281398
Short name T66
Test name
Test status
Simulation time 38865261 ps
CPU time 1.06 seconds
Started Mar 12 01:01:51 PM PDT 24
Finished Mar 12 01:01:55 PM PDT 24
Peak memory 202724 kb
Host smart-7d96bf84-61fc-48e9-8e36-a9439f4643c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130281398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_cs
r_outstanding.130281398
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2886125942
Short name T42
Test name
Test status
Simulation time 239971766 ps
CPU time 3.08 seconds
Started Mar 12 01:02:01 PM PDT 24
Finished Mar 12 01:02:05 PM PDT 24
Peak memory 202732 kb
Host smart-079a7897-85fc-438f-83df-02ffabf74ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2886125942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2886125942
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2204364976
Short name T739
Test name
Test status
Simulation time 126945837 ps
CPU time 3.41 seconds
Started Mar 12 01:01:51 PM PDT 24
Finished Mar 12 01:01:54 PM PDT 24
Peak memory 202652 kb
Host smart-d0ba37ed-783f-442d-b2ea-f05898dab3b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204364976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2204364976
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3370699186
Short name T48
Test name
Test status
Simulation time 39104349 ps
CPU time 0.74 seconds
Started Mar 12 01:01:47 PM PDT 24
Finished Mar 12 01:01:47 PM PDT 24
Peak memory 202452 kb
Host smart-14a77e61-cdcb-4faa-a4f1-6451312ea847
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370699186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3370699186
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2465185764
Short name T744
Test name
Test status
Simulation time 73514270 ps
CPU time 1.15 seconds
Started Mar 12 01:02:06 PM PDT 24
Finished Mar 12 01:02:08 PM PDT 24
Peak memory 212032 kb
Host smart-cee8f2c3-05ce-4a56-917d-69962d3c9a9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465185764 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.usbdev_csr_mem_rw_with_rand_reset.2465185764
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3044314031
Short name T797
Test name
Test status
Simulation time 26931814 ps
CPU time 0.79 seconds
Started Mar 12 01:02:15 PM PDT 24
Finished Mar 12 01:02:16 PM PDT 24
Peak memory 202436 kb
Host smart-dd9d4d36-625b-49b0-b480-3ca2104ae0f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044314031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3044314031
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2470405847
Short name T785
Test name
Test status
Simulation time 22916756 ps
CPU time 0.64 seconds
Started Mar 12 01:01:53 PM PDT 24
Finished Mar 12 01:01:54 PM PDT 24
Peak memory 201904 kb
Host smart-c08677b2-e8bb-49ec-879f-f093255d018c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2470405847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2470405847
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1029805147
Short name T780
Test name
Test status
Simulation time 93114895 ps
CPU time 1.34 seconds
Started Mar 12 01:02:19 PM PDT 24
Finished Mar 12 01:02:20 PM PDT 24
Peak memory 202556 kb
Host smart-07aba9e1-34dc-4173-aa60-dd4b646207c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1029805147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1029805147
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1548604938
Short name T743
Test name
Test status
Simulation time 477949372 ps
CPU time 4.24 seconds
Started Mar 12 01:01:48 PM PDT 24
Finished Mar 12 01:01:53 PM PDT 24
Peak memory 202568 kb
Host smart-28c93581-7cca-4ab0-b5c1-13460b302dde
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1548604938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1548604938
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.204243904
Short name T202
Test name
Test status
Simulation time 157573498 ps
CPU time 1.65 seconds
Started Mar 12 01:02:29 PM PDT 24
Finished Mar 12 01:02:31 PM PDT 24
Peak memory 202720 kb
Host smart-507c06d0-1875-4a91-8131-73ad3126cd4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204243904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_cs
r_outstanding.204243904
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1769067592
Short name T718
Test name
Test status
Simulation time 48277663 ps
CPU time 1.48 seconds
Started Mar 12 01:01:51 PM PDT 24
Finished Mar 12 01:01:53 PM PDT 24
Peak memory 202832 kb
Host smart-3dc97537-cec0-40da-9881-3451dc6e7f01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1769067592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1769067592
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2435437543
Short name T719
Test name
Test status
Simulation time 49438315 ps
CPU time 1.55 seconds
Started Mar 12 01:02:12 PM PDT 24
Finished Mar 12 01:02:14 PM PDT 24
Peak memory 211052 kb
Host smart-2ec79cfb-db7e-4a6b-9e8e-da0cf6ffb24b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435437543 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.usbdev_csr_mem_rw_with_rand_reset.2435437543
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1281592455
Short name T766
Test name
Test status
Simulation time 29143721 ps
CPU time 0.64 seconds
Started Mar 12 01:02:11 PM PDT 24
Finished Mar 12 01:02:17 PM PDT 24
Peak memory 201956 kb
Host smart-7ad140ba-e0a7-4a68-9beb-fd78518d26ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1281592455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1281592455
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3743114292
Short name T752
Test name
Test status
Simulation time 60535977 ps
CPU time 1.37 seconds
Started Mar 12 01:01:51 PM PDT 24
Finished Mar 12 01:01:53 PM PDT 24
Peak memory 202748 kb
Host smart-6f65c7e8-fa1c-4e2b-8006-e616581c5747
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743114292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_
csr_outstanding.3743114292
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3509799326
Short name T140
Test name
Test status
Simulation time 238975551 ps
CPU time 2.82 seconds
Started Mar 12 01:01:50 PM PDT 24
Finished Mar 12 01:01:53 PM PDT 24
Peak memory 202800 kb
Host smart-68345157-59f3-4d2f-a0ad-ff3b2a2dc333
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3509799326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3509799326
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3193582250
Short name T767
Test name
Test status
Simulation time 80107926 ps
CPU time 1.18 seconds
Started Mar 12 01:02:07 PM PDT 24
Finished Mar 12 01:02:08 PM PDT 24
Peak memory 210996 kb
Host smart-fa9f63ee-f2c4-4327-8eed-e8eb003869c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193582250 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.usbdev_csr_mem_rw_with_rand_reset.3193582250
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.602370584
Short name T728
Test name
Test status
Simulation time 29765619 ps
CPU time 0.77 seconds
Started Mar 12 01:01:49 PM PDT 24
Finished Mar 12 01:01:50 PM PDT 24
Peak memory 202452 kb
Host smart-d1828a80-0484-4fbd-a31d-0385e363d43e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602370584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.602370584
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1606249370
Short name T794
Test name
Test status
Simulation time 27648807 ps
CPU time 0.65 seconds
Started Mar 12 01:01:49 PM PDT 24
Finished Mar 12 01:01:50 PM PDT 24
Peak memory 201904 kb
Host smart-0bbb4861-5088-4929-a7b1-f0e99d7b800e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1606249370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1606249370
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1775842844
Short name T761
Test name
Test status
Simulation time 43140860 ps
CPU time 1.03 seconds
Started Mar 12 01:02:00 PM PDT 24
Finished Mar 12 01:02:07 PM PDT 24
Peak memory 202784 kb
Host smart-b274c0af-dfbb-4cc9-9cd3-44ee188b04a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775842844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_
csr_outstanding.1775842844
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3339455995
Short name T206
Test name
Test status
Simulation time 81012883 ps
CPU time 1.14 seconds
Started Mar 12 01:02:02 PM PDT 24
Finished Mar 12 01:02:05 PM PDT 24
Peak memory 210968 kb
Host smart-9ed4e54b-f9a2-4ac3-af97-11f77a716c57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339455995 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.usbdev_csr_mem_rw_with_rand_reset.3339455995
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3762050894
Short name T786
Test name
Test status
Simulation time 70211447 ps
CPU time 1 seconds
Started Mar 12 01:02:00 PM PDT 24
Finished Mar 12 01:02:01 PM PDT 24
Peak memory 202644 kb
Host smart-a9e3304b-2f7c-4dc4-a39f-63c9f0fee62e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762050894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3762050894
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3666614354
Short name T774
Test name
Test status
Simulation time 29751183 ps
CPU time 0.65 seconds
Started Mar 12 01:02:02 PM PDT 24
Finished Mar 12 01:02:03 PM PDT 24
Peak memory 201972 kb
Host smart-12cf00e1-bc48-4606-94f6-362a07cd3cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3666614354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3666614354
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2684732385
Short name T733
Test name
Test status
Simulation time 74488836 ps
CPU time 0.99 seconds
Started Mar 12 01:02:19 PM PDT 24
Finished Mar 12 01:02:20 PM PDT 24
Peak memory 202668 kb
Host smart-3887754b-ff6a-49d9-aab0-44a791a66df7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684732385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_
csr_outstanding.2684732385
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.342782988
Short name T778
Test name
Test status
Simulation time 83448723 ps
CPU time 1.33 seconds
Started Mar 12 01:02:08 PM PDT 24
Finished Mar 12 01:02:10 PM PDT 24
Peak memory 211004 kb
Host smart-432b0052-c6fb-4730-8cd6-6e971f58316f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342782988 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.usbdev_csr_mem_rw_with_rand_reset.342782988
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3646733738
Short name T65
Test name
Test status
Simulation time 41281490 ps
CPU time 0.87 seconds
Started Mar 12 01:01:50 PM PDT 24
Finished Mar 12 01:01:51 PM PDT 24
Peak memory 202456 kb
Host smart-86546c83-637c-4d0c-ad52-f2a01a4ad68a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646733738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3646733738
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.185997942
Short name T792
Test name
Test status
Simulation time 20156537 ps
CPU time 0.64 seconds
Started Mar 12 01:02:01 PM PDT 24
Finished Mar 12 01:02:03 PM PDT 24
Peak memory 202028 kb
Host smart-4f978e2f-a34d-43ae-b652-41c94e1ecb17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=185997942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.185997942
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2551959826
Short name T736
Test name
Test status
Simulation time 62194544 ps
CPU time 1.43 seconds
Started Mar 12 01:01:49 PM PDT 24
Finished Mar 12 01:01:51 PM PDT 24
Peak memory 202732 kb
Host smart-f64bcd25-99e5-43a5-b434-d8aa537994f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551959826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_
csr_outstanding.2551959826
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2181014660
Short name T740
Test name
Test status
Simulation time 206245983 ps
CPU time 2.39 seconds
Started Mar 12 01:01:56 PM PDT 24
Finished Mar 12 01:01:58 PM PDT 24
Peak memory 202724 kb
Host smart-70949c37-2fb8-4c4d-a8fc-8b3c543c6b35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2181014660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2181014660
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.86281858
Short name T220
Test name
Test status
Simulation time 267975813 ps
CPU time 4.38 seconds
Started Mar 12 01:01:56 PM PDT 24
Finished Mar 12 01:02:01 PM PDT 24
Peak memory 202760 kb
Host smart-57b6d4b1-2210-42d3-8947-04506b9d6747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=86281858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.86281858
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.232568887
Short name T781
Test name
Test status
Simulation time 140632842 ps
CPU time 1.98 seconds
Started Mar 12 01:02:12 PM PDT 24
Finished Mar 12 01:02:15 PM PDT 24
Peak memory 210932 kb
Host smart-b32966b9-897b-4484-953c-2a5323bd44db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232568887 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.usbdev_csr_mem_rw_with_rand_reset.232568887
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2336766943
Short name T63
Test name
Test status
Simulation time 25462512 ps
CPU time 0.8 seconds
Started Mar 12 01:01:49 PM PDT 24
Finished Mar 12 01:01:51 PM PDT 24
Peak memory 202364 kb
Host smart-b7a1b436-0754-4e58-953d-ee913b716953
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336766943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2336766943
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3688601065
Short name T745
Test name
Test status
Simulation time 62002816 ps
CPU time 1.4 seconds
Started Mar 12 01:01:47 PM PDT 24
Finished Mar 12 01:01:48 PM PDT 24
Peak memory 202612 kb
Host smart-170d935c-3214-497d-9041-cb5ca1035f45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688601065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_
csr_outstanding.3688601065
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.716185421
Short name T720
Test name
Test status
Simulation time 236970521 ps
CPU time 2.88 seconds
Started Mar 12 01:01:49 PM PDT 24
Finished Mar 12 01:01:53 PM PDT 24
Peak memory 202852 kb
Host smart-a2384ad5-3743-4edf-a427-997f0989b536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=716185421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.716185421
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3809802915
Short name T791
Test name
Test status
Simulation time 118998063 ps
CPU time 2.48 seconds
Started Mar 12 01:02:02 PM PDT 24
Finished Mar 12 01:02:05 PM PDT 24
Peak memory 202716 kb
Host smart-eb62155d-26e2-4dda-9263-2c897a151dcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3809802915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3809802915
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2952185645
Short name T725
Test name
Test status
Simulation time 113489121 ps
CPU time 1.53 seconds
Started Mar 12 01:02:01 PM PDT 24
Finished Mar 12 01:02:04 PM PDT 24
Peak memory 211008 kb
Host smart-c754b6fb-47e7-47a9-8d50-62dc5235adbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952185645 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.usbdev_csr_mem_rw_with_rand_reset.2952185645
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4063644638
Short name T757
Test name
Test status
Simulation time 25727996 ps
CPU time 0.78 seconds
Started Mar 12 01:02:11 PM PDT 24
Finished Mar 12 01:02:13 PM PDT 24
Peak memory 202352 kb
Host smart-7ee64b85-da0f-45e7-8ff9-1d28adeca569
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063644638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.4063644638
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2318441105
Short name T760
Test name
Test status
Simulation time 19405595 ps
CPU time 0.66 seconds
Started Mar 12 01:02:20 PM PDT 24
Finished Mar 12 01:02:20 PM PDT 24
Peak memory 201952 kb
Host smart-9ce746a0-72d0-4153-b1e1-063c337f6b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2318441105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2318441105
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3644600366
Short name T147
Test name
Test status
Simulation time 38681689 ps
CPU time 0.97 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:02:23 PM PDT 24
Peak memory 202672 kb
Host smart-1b34c26f-318e-4ff7-9a8a-2ee70a4048f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644600366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_
csr_outstanding.3644600366
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1598625238
Short name T749
Test name
Test status
Simulation time 59699774 ps
CPU time 1.87 seconds
Started Mar 12 01:02:04 PM PDT 24
Finished Mar 12 01:02:06 PM PDT 24
Peak memory 202756 kb
Host smart-bb517a2a-dddf-4c38-8624-22dc5e9d6549
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1598625238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1598625238
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3863229802
Short name T784
Test name
Test status
Simulation time 127783011 ps
CPU time 2.51 seconds
Started Mar 12 01:02:23 PM PDT 24
Finished Mar 12 01:02:25 PM PDT 24
Peak memory 202668 kb
Host smart-8072c023-287e-402b-a11b-2608a2054385
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3863229802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3863229802
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2723354116
Short name T795
Test name
Test status
Simulation time 70480310 ps
CPU time 1.26 seconds
Started Mar 12 01:02:18 PM PDT 24
Finished Mar 12 01:02:19 PM PDT 24
Peak memory 212032 kb
Host smart-b9d6e8e6-b78a-495f-8e8d-cc20abc16439
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723354116 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.usbdev_csr_mem_rw_with_rand_reset.2723354116
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3446539990
Short name T64
Test name
Test status
Simulation time 64884652 ps
CPU time 1.03 seconds
Started Mar 12 01:02:09 PM PDT 24
Finished Mar 12 01:02:11 PM PDT 24
Peak memory 202656 kb
Host smart-02154383-07e5-430f-8bfb-629c41ac550e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446539990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3446539990
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2430305299
Short name T753
Test name
Test status
Simulation time 133594299 ps
CPU time 1.47 seconds
Started Mar 12 01:02:14 PM PDT 24
Finished Mar 12 01:02:16 PM PDT 24
Peak memory 202732 kb
Host smart-fc1c21a1-929e-4c81-99b3-300ba1e74a5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430305299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_
csr_outstanding.2430305299
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4003429284
Short name T141
Test name
Test status
Simulation time 144998292 ps
CPU time 1.9 seconds
Started Mar 12 01:02:17 PM PDT 24
Finished Mar 12 01:02:19 PM PDT 24
Peak memory 202712 kb
Host smart-2255af1d-33a2-4eb3-9ac3-e7c352527922
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4003429284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.4003429284
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1305430492
Short name T144
Test name
Test status
Simulation time 261152088 ps
CPU time 4.45 seconds
Started Mar 12 01:02:02 PM PDT 24
Finished Mar 12 01:02:08 PM PDT 24
Peak memory 202728 kb
Host smart-5c69595e-8da3-4d85-99dc-f59e64790ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1305430492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1305430492
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.115606496
Short name T747
Test name
Test status
Simulation time 67918716 ps
CPU time 2.21 seconds
Started Mar 12 01:02:18 PM PDT 24
Finished Mar 12 01:02:20 PM PDT 24
Peak memory 210772 kb
Host smart-98cef44e-0a67-4824-b9c9-d78cc30f0dfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115606496 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.usbdev_csr_mem_rw_with_rand_reset.115606496
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3062779206
Short name T157
Test name
Test status
Simulation time 77362427 ps
CPU time 1.02 seconds
Started Mar 12 01:01:53 PM PDT 24
Finished Mar 12 01:01:54 PM PDT 24
Peak memory 202652 kb
Host smart-e2295d19-e43e-410d-8424-5123c9009c4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062779206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3062779206
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3278506751
Short name T210
Test name
Test status
Simulation time 29360225 ps
CPU time 0.65 seconds
Started Mar 12 01:01:49 PM PDT 24
Finished Mar 12 01:01:51 PM PDT 24
Peak memory 201920 kb
Host smart-10ae4691-0dac-418a-b28b-a16b5d1ba31b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3278506751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3278506751
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3763303134
Short name T772
Test name
Test status
Simulation time 83656036 ps
CPU time 1.09 seconds
Started Mar 12 01:02:01 PM PDT 24
Finished Mar 12 01:02:03 PM PDT 24
Peak memory 202768 kb
Host smart-91672207-5bba-404a-9c9f-8945eef9f869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763303134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_
csr_outstanding.3763303134
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1850944484
Short name T142
Test name
Test status
Simulation time 297627796 ps
CPU time 3.03 seconds
Started Mar 12 01:01:56 PM PDT 24
Finished Mar 12 01:01:59 PM PDT 24
Peak memory 202648 kb
Host smart-8016ffc8-0e8a-436e-b7a6-da4315ecda78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1850944484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1850944484
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.553832505
Short name T765
Test name
Test status
Simulation time 151406445 ps
CPU time 2.49 seconds
Started Mar 12 01:01:55 PM PDT 24
Finished Mar 12 01:01:58 PM PDT 24
Peak memory 202764 kb
Host smart-c9713ba4-0bef-4f56-a7a2-0ec89ffcbf10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=553832505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.553832505
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.424354570
Short name T197
Test name
Test status
Simulation time 87554108 ps
CPU time 1.33 seconds
Started Mar 12 01:02:31 PM PDT 24
Finished Mar 12 01:02:33 PM PDT 24
Peak memory 212040 kb
Host smart-b3488f54-0121-46aa-beb1-0f06bdda6acb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424354570 -assert nopostproc +UVM_TESTNAME=usbd
ev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.usbdev_csr_mem_rw_with_rand_reset.424354570
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.548908377
Short name T155
Test name
Test status
Simulation time 45076608 ps
CPU time 0.84 seconds
Started Mar 12 01:01:56 PM PDT 24
Finished Mar 12 01:01:57 PM PDT 24
Peak memory 202480 kb
Host smart-1bb82762-0f47-44f8-81a4-b19c277e9084
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548908377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.548908377
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1559510733
Short name T207
Test name
Test status
Simulation time 26969613 ps
CPU time 0.61 seconds
Started Mar 12 01:02:00 PM PDT 24
Finished Mar 12 01:02:01 PM PDT 24
Peak memory 201900 kb
Host smart-592276fa-0c8d-4c15-9aac-d9be4656bddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1559510733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1559510733
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3252525397
Short name T717
Test name
Test status
Simulation time 73675912 ps
CPU time 2.18 seconds
Started Mar 12 01:02:18 PM PDT 24
Finished Mar 12 01:02:20 PM PDT 24
Peak memory 202584 kb
Host smart-07b1ff35-58f0-4243-977a-78336eb3e8c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3252525397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3252525397
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3518519191
Short name T771
Test name
Test status
Simulation time 158716205 ps
CPU time 1.81 seconds
Started Mar 12 01:02:17 PM PDT 24
Finished Mar 12 01:02:19 PM PDT 24
Peak memory 211028 kb
Host smart-6e9c7829-be49-41a1-8427-50284f0349f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518519191 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.usbdev_csr_mem_rw_with_rand_reset.3518519191
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2260177486
Short name T788
Test name
Test status
Simulation time 39423205 ps
CPU time 0.78 seconds
Started Mar 12 01:02:03 PM PDT 24
Finished Mar 12 01:02:05 PM PDT 24
Peak memory 202468 kb
Host smart-7805def1-2041-4122-964a-430d24a37b0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260177486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2260177486
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3638078092
Short name T214
Test name
Test status
Simulation time 28714077 ps
CPU time 0.63 seconds
Started Mar 12 01:02:18 PM PDT 24
Finished Mar 12 01:02:19 PM PDT 24
Peak memory 201840 kb
Host smart-13847ca8-7fd4-40be-92ff-49dbce5a29ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3638078092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3638078092
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4126600564
Short name T793
Test name
Test status
Simulation time 57652245 ps
CPU time 1.28 seconds
Started Mar 12 01:02:14 PM PDT 24
Finished Mar 12 01:02:15 PM PDT 24
Peak memory 202596 kb
Host smart-d2d656f3-81ba-47ad-9ef9-a4868d82badc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126600564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_
csr_outstanding.4126600564
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3129346720
Short name T715
Test name
Test status
Simulation time 118444429 ps
CPU time 1.55 seconds
Started Mar 12 01:02:20 PM PDT 24
Finished Mar 12 01:02:22 PM PDT 24
Peak memory 202812 kb
Host smart-3c18e1c1-6543-4bb4-ac74-6ba1d17712bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3129346720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3129346720
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2342379423
Short name T796
Test name
Test status
Simulation time 140780881 ps
CPU time 2.63 seconds
Started Mar 12 01:02:18 PM PDT 24
Finished Mar 12 01:02:21 PM PDT 24
Peak memory 202696 kb
Host smart-091242be-4291-4cab-a944-ef12652e5809
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2342379423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2342379423
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2667781371
Short name T759
Test name
Test status
Simulation time 78271645 ps
CPU time 2.18 seconds
Started Mar 12 01:02:09 PM PDT 24
Finished Mar 12 01:02:12 PM PDT 24
Peak memory 202608 kb
Host smart-b47c69a4-b982-4b78-a87f-37d23deb119d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667781371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2667781371
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2020381596
Short name T801
Test name
Test status
Simulation time 32150949 ps
CPU time 0.71 seconds
Started Mar 12 01:02:18 PM PDT 24
Finished Mar 12 01:02:19 PM PDT 24
Peak memory 202444 kb
Host smart-6d730fd0-719d-43e5-a703-8f382c46d408
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020381596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2020381596
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3021054980
Short name T800
Test name
Test status
Simulation time 110677717 ps
CPU time 1.67 seconds
Started Mar 12 01:02:03 PM PDT 24
Finished Mar 12 01:02:05 PM PDT 24
Peak memory 211068 kb
Host smart-684637e1-c6e5-4260-b6d2-846753cb9d82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021054980 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.usbdev_csr_mem_rw_with_rand_reset.3021054980
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1240197181
Short name T789
Test name
Test status
Simulation time 23416248 ps
CPU time 0.81 seconds
Started Mar 12 01:02:05 PM PDT 24
Finished Mar 12 01:02:07 PM PDT 24
Peak memory 202460 kb
Host smart-899d4ec4-fcb2-4435-b5aa-fbe3a4373806
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240197181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1240197181
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.708918501
Short name T158
Test name
Test status
Simulation time 63191841 ps
CPU time 2.13 seconds
Started Mar 12 01:01:56 PM PDT 24
Finished Mar 12 01:01:58 PM PDT 24
Peak memory 202668 kb
Host smart-a539e65e-cc45-4cda-9ce8-0b33684a9155
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=708918501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.708918501
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3015990865
Short name T196
Test name
Test status
Simulation time 353876583 ps
CPU time 2.65 seconds
Started Mar 12 01:01:48 PM PDT 24
Finished Mar 12 01:01:51 PM PDT 24
Peak memory 202540 kb
Host smart-2ec61e1d-26fc-463d-8910-552855b09d33
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3015990865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3015990865
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.4273535582
Short name T67
Test name
Test status
Simulation time 39682236 ps
CPU time 0.95 seconds
Started Mar 12 01:02:14 PM PDT 24
Finished Mar 12 01:02:15 PM PDT 24
Peak memory 202732 kb
Host smart-487cb0a1-fbc6-435a-958a-968518a7e35a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273535582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_c
sr_outstanding.4273535582
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3508366191
Short name T721
Test name
Test status
Simulation time 190767455 ps
CPU time 2.59 seconds
Started Mar 12 01:01:58 PM PDT 24
Finished Mar 12 01:02:01 PM PDT 24
Peak memory 202784 kb
Host smart-92df14e5-7126-4504-a5e7-4696d7ae503f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3508366191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3508366191
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1674754977
Short name T221
Test name
Test status
Simulation time 337458244 ps
CPU time 4.21 seconds
Started Mar 12 01:01:59 PM PDT 24
Finished Mar 12 01:02:03 PM PDT 24
Peak memory 202704 kb
Host smart-93fc6252-3cb1-48b8-baa9-5795569afff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1674754977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1674754977
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.518711089
Short name T756
Test name
Test status
Simulation time 22869027 ps
CPU time 0.65 seconds
Started Mar 12 01:02:18 PM PDT 24
Finished Mar 12 01:02:19 PM PDT 24
Peak memory 201936 kb
Host smart-f40ea662-1f92-43da-88da-9ba19de982b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=518711089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.518711089
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3235398369
Short name T57
Test name
Test status
Simulation time 26858187 ps
CPU time 0.68 seconds
Started Mar 12 01:02:34 PM PDT 24
Finished Mar 12 01:02:34 PM PDT 24
Peak memory 201908 kb
Host smart-57a4bf46-82d0-45d2-b714-3b50c6cf0182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3235398369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3235398369
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2217485943
Short name T763
Test name
Test status
Simulation time 24540253 ps
CPU time 0.64 seconds
Started Mar 12 01:02:23 PM PDT 24
Finished Mar 12 01:02:24 PM PDT 24
Peak memory 201896 kb
Host smart-d2e51b0a-d346-4406-b88f-38ac52800afd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2217485943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2217485943
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3965868050
Short name T729
Test name
Test status
Simulation time 33815327 ps
CPU time 0.65 seconds
Started Mar 12 01:02:11 PM PDT 24
Finished Mar 12 01:02:12 PM PDT 24
Peak memory 201940 kb
Host smart-f6492343-fb0a-4a6e-a3da-9f02c7a8f0fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3965868050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3965868050
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.547335909
Short name T754
Test name
Test status
Simulation time 23471086 ps
CPU time 0.67 seconds
Started Mar 12 01:02:20 PM PDT 24
Finished Mar 12 01:02:21 PM PDT 24
Peak memory 201884 kb
Host smart-20588454-aa4a-4d29-b0d6-9723c749d2f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=547335909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.547335909
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1996620232
Short name T151
Test name
Test status
Simulation time 335352439 ps
CPU time 3.91 seconds
Started Mar 12 01:01:57 PM PDT 24
Finished Mar 12 01:02:07 PM PDT 24
Peak memory 202680 kb
Host smart-b579b23c-3662-4320-af4b-49a65a120de9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996620232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1996620232
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3418801381
Short name T52
Test name
Test status
Simulation time 33962368 ps
CPU time 0.71 seconds
Started Mar 12 01:01:57 PM PDT 24
Finished Mar 12 01:01:58 PM PDT 24
Peak memory 202444 kb
Host smart-d3bf60e9-fff0-4e35-9730-fa67e32f6152
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418801381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3418801381
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.1004421645
Short name T787
Test name
Test status
Simulation time 63096165 ps
CPU time 1.84 seconds
Started Mar 12 01:01:50 PM PDT 24
Finished Mar 12 01:01:52 PM PDT 24
Peak memory 211028 kb
Host smart-a6470c37-8d48-488f-9e77-3b3d43da2720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004421645 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.usbdev_csr_mem_rw_with_rand_reset.1004421645
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2125041500
Short name T53
Test name
Test status
Simulation time 47432771 ps
CPU time 0.83 seconds
Started Mar 12 01:02:17 PM PDT 24
Finished Mar 12 01:02:18 PM PDT 24
Peak memory 202440 kb
Host smart-8acd3aa0-7308-4613-9bd8-1ec966ee09ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125041500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2125041500
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3044374141
Short name T722
Test name
Test status
Simulation time 28181371 ps
CPU time 0.62 seconds
Started Mar 12 01:02:01 PM PDT 24
Finished Mar 12 01:02:03 PM PDT 24
Peak memory 201932 kb
Host smart-9a2f0937-c1fa-4f1c-b107-1c322bf9bf5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3044374141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3044374141
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.673288801
Short name T150
Test name
Test status
Simulation time 154288413 ps
CPU time 2.27 seconds
Started Mar 12 01:01:52 PM PDT 24
Finished Mar 12 01:01:54 PM PDT 24
Peak memory 202728 kb
Host smart-1ebc5d8f-8789-4b3c-942b-4fe677bb6bdf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=673288801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.673288801
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2955573609
Short name T776
Test name
Test status
Simulation time 95837619 ps
CPU time 1.21 seconds
Started Mar 12 01:01:51 PM PDT 24
Finished Mar 12 01:01:53 PM PDT 24
Peak memory 202668 kb
Host smart-ad0d4574-f1bc-4ab5-b5f8-02db7adca935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955573609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_c
sr_outstanding.2955573609
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1926214005
Short name T732
Test name
Test status
Simulation time 152721739 ps
CPU time 1.72 seconds
Started Mar 12 01:02:00 PM PDT 24
Finished Mar 12 01:02:04 PM PDT 24
Peak memory 202808 kb
Host smart-029d514f-a95f-4bee-8316-4f9db09c7715
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1926214005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1926214005
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.457223066
Short name T779
Test name
Test status
Simulation time 331959148 ps
CPU time 3.05 seconds
Started Mar 12 01:01:51 PM PDT 24
Finished Mar 12 01:01:54 PM PDT 24
Peak memory 202744 kb
Host smart-5544e5b3-6504-479b-8f4f-af0a34b22c59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=457223066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.457223066
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2111799644
Short name T209
Test name
Test status
Simulation time 24704418 ps
CPU time 0.63 seconds
Started Mar 12 01:02:19 PM PDT 24
Finished Mar 12 01:02:20 PM PDT 24
Peak memory 201904 kb
Host smart-249aee39-8fee-4cd3-bd0e-3f16bad23e6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2111799644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2111799644
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1675106721
Short name T764
Test name
Test status
Simulation time 27875216 ps
CPU time 0.61 seconds
Started Mar 12 01:01:57 PM PDT 24
Finished Mar 12 01:01:58 PM PDT 24
Peak memory 201920 kb
Host smart-e4a57826-137d-4246-be4a-5f9aec894df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1675106721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1675106721
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3616172669
Short name T208
Test name
Test status
Simulation time 24965892 ps
CPU time 0.65 seconds
Started Mar 12 01:02:20 PM PDT 24
Finished Mar 12 01:02:21 PM PDT 24
Peak memory 201968 kb
Host smart-4a02e203-22e6-4036-b073-27cc93d6c706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3616172669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3616172669
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1450906359
Short name T212
Test name
Test status
Simulation time 26788338 ps
CPU time 0.64 seconds
Started Mar 12 01:02:20 PM PDT 24
Finished Mar 12 01:02:21 PM PDT 24
Peak memory 201824 kb
Host smart-053376f3-a78c-4b0a-b966-9fe60f3aaeba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1450906359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1450906359
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.504864728
Short name T204
Test name
Test status
Simulation time 24844181 ps
CPU time 0.65 seconds
Started Mar 12 01:02:23 PM PDT 24
Finished Mar 12 01:02:24 PM PDT 24
Peak memory 201876 kb
Host smart-ca435cbc-9439-4c36-8349-3415d5358cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=504864728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.504864728
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3618197289
Short name T735
Test name
Test status
Simulation time 22307221 ps
CPU time 0.64 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:02:23 PM PDT 24
Peak memory 201908 kb
Host smart-79b6c740-8a4f-49eb-9282-c9435f74112e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3618197289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3618197289
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2010358833
Short name T741
Test name
Test status
Simulation time 22765959 ps
CPU time 0.64 seconds
Started Mar 12 01:02:27 PM PDT 24
Finished Mar 12 01:02:28 PM PDT 24
Peak memory 201876 kb
Host smart-01007414-2163-415b-85d6-f28c4ef9542c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2010358833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2010358833
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3308408517
Short name T159
Test name
Test status
Simulation time 176259185 ps
CPU time 2.15 seconds
Started Mar 12 01:02:01 PM PDT 24
Finished Mar 12 01:02:04 PM PDT 24
Peak memory 202664 kb
Host smart-60ce1993-04ca-4c8c-a5e3-54a0f2205366
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308408517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3308408517
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3523631117
Short name T782
Test name
Test status
Simulation time 201593416 ps
CPU time 4.73 seconds
Started Mar 12 01:01:50 PM PDT 24
Finished Mar 12 01:01:55 PM PDT 24
Peak memory 202636 kb
Host smart-19ed7cdb-c4a1-4f0f-9f96-113e5d2685fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523631117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3523631117
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2523769252
Short name T47
Test name
Test status
Simulation time 35488672 ps
CPU time 0.71 seconds
Started Mar 12 01:02:04 PM PDT 24
Finished Mar 12 01:02:06 PM PDT 24
Peak memory 202416 kb
Host smart-212b5798-33b1-4370-8a73-2fda7a37551f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523769252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2523769252
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2314255292
Short name T762
Test name
Test status
Simulation time 92277967 ps
CPU time 1.31 seconds
Started Mar 12 01:01:51 PM PDT 24
Finished Mar 12 01:01:53 PM PDT 24
Peak memory 210968 kb
Host smart-76d6140e-5567-4d28-af0b-a2cd32fa92a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314255292 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.usbdev_csr_mem_rw_with_rand_reset.2314255292
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2732439698
Short name T737
Test name
Test status
Simulation time 72630109 ps
CPU time 1.03 seconds
Started Mar 12 01:02:07 PM PDT 24
Finished Mar 12 01:02:08 PM PDT 24
Peak memory 202704 kb
Host smart-0f806dcf-c8ce-4d4a-8073-79b7c14a7141
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732439698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2732439698
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4202970855
Short name T734
Test name
Test status
Simulation time 20614627 ps
CPU time 0.61 seconds
Started Mar 12 01:02:10 PM PDT 24
Finished Mar 12 01:02:11 PM PDT 24
Peak memory 201912 kb
Host smart-3fe42372-4050-41a9-970f-98bcb9e940c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4202970855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.4202970855
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4205543224
Short name T146
Test name
Test status
Simulation time 182944031 ps
CPU time 2.2 seconds
Started Mar 12 01:02:01 PM PDT 24
Finished Mar 12 01:02:05 PM PDT 24
Peak memory 202748 kb
Host smart-bbb73dfa-271e-4053-839f-22015f9e088b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4205543224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.4205543224
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3519282807
Short name T726
Test name
Test status
Simulation time 149175245 ps
CPU time 3.7 seconds
Started Mar 12 01:01:49 PM PDT 24
Finished Mar 12 01:01:54 PM PDT 24
Peak memory 202640 kb
Host smart-4bd43d24-2248-4946-930f-8f67eca13fc7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3519282807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3519282807
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1478128798
Short name T746
Test name
Test status
Simulation time 81198633 ps
CPU time 1.12 seconds
Started Mar 12 01:01:52 PM PDT 24
Finished Mar 12 01:01:54 PM PDT 24
Peak memory 202616 kb
Host smart-0ff4dafd-5b94-4f05-acba-fa2edcebf029
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478128798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_c
sr_outstanding.1478128798
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.16679812
Short name T730
Test name
Test status
Simulation time 114546513 ps
CPU time 1.43 seconds
Started Mar 12 01:01:51 PM PDT 24
Finished Mar 12 01:01:58 PM PDT 24
Peak memory 202816 kb
Host smart-268c8fab-16b3-4a98-a401-df5cfb1e1d13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=16679812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.16679812
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1780036153
Short name T218
Test name
Test status
Simulation time 286366769 ps
CPU time 2.76 seconds
Started Mar 12 01:02:01 PM PDT 24
Finished Mar 12 01:02:05 PM PDT 24
Peak memory 202736 kb
Host smart-5691b811-91c3-44d8-b563-0c11f77926e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1780036153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1780036153
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2595137708
Short name T783
Test name
Test status
Simulation time 30333574 ps
CPU time 0.63 seconds
Started Mar 12 01:02:07 PM PDT 24
Finished Mar 12 01:02:08 PM PDT 24
Peak memory 201912 kb
Host smart-1d5ab80c-ce3b-45c3-947f-ad26a8bc5c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2595137708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2595137708
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4145489046
Short name T751
Test name
Test status
Simulation time 28776948 ps
CPU time 0.65 seconds
Started Mar 12 01:02:25 PM PDT 24
Finished Mar 12 01:02:26 PM PDT 24
Peak memory 201916 kb
Host smart-75afe82d-01f6-448b-8d71-4f44c1b2419e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4145489046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.4145489046
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3337114404
Short name T738
Test name
Test status
Simulation time 20655520 ps
CPU time 0.64 seconds
Started Mar 12 01:02:18 PM PDT 24
Finished Mar 12 01:02:19 PM PDT 24
Peak memory 201736 kb
Host smart-368b161a-51ac-4bed-9c2d-15fc8659d46b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3337114404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3337114404
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2678224866
Short name T205
Test name
Test status
Simulation time 26426442 ps
CPU time 0.63 seconds
Started Mar 12 01:02:23 PM PDT 24
Finished Mar 12 01:02:24 PM PDT 24
Peak memory 201936 kb
Host smart-d0ed74c0-4ba1-45aa-9ba2-d8c637a142f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2678224866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2678224866
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3325487268
Short name T213
Test name
Test status
Simulation time 18672392 ps
CPU time 0.63 seconds
Started Mar 12 01:02:17 PM PDT 24
Finished Mar 12 01:02:18 PM PDT 24
Peak memory 201912 kb
Host smart-a458fdf9-5096-4b27-a9af-583b85e3d7fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3325487268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3325487268
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.398566783
Short name T758
Test name
Test status
Simulation time 26354098 ps
CPU time 0.66 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:02:22 PM PDT 24
Peak memory 201884 kb
Host smart-28902dca-d681-4fe6-ba20-7eb5b2b24c2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=398566783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.398566783
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.486297131
Short name T773
Test name
Test status
Simulation time 23893930 ps
CPU time 0.64 seconds
Started Mar 12 01:02:23 PM PDT 24
Finished Mar 12 01:02:24 PM PDT 24
Peak memory 201976 kb
Host smart-8cfc2743-f80a-4b5c-ae52-f6b203fa0b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=486297131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.486297131
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1693901735
Short name T799
Test name
Test status
Simulation time 24070406 ps
CPU time 0.65 seconds
Started Mar 12 01:02:08 PM PDT 24
Finished Mar 12 01:02:09 PM PDT 24
Peak memory 201908 kb
Host smart-7e587e2a-9b5d-4514-b55f-c061ad657fe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1693901735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1693901735
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3318898152
Short name T56
Test name
Test status
Simulation time 23324366 ps
CPU time 0.61 seconds
Started Mar 12 01:02:13 PM PDT 24
Finished Mar 12 01:02:14 PM PDT 24
Peak memory 201912 kb
Host smart-51f1a117-53ca-4b72-a8e5-06c5ede26348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3318898152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3318898152
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2139229708
Short name T790
Test name
Test status
Simulation time 66684374 ps
CPU time 2.01 seconds
Started Mar 12 01:02:01 PM PDT 24
Finished Mar 12 01:02:04 PM PDT 24
Peak memory 210940 kb
Host smart-92a3930b-b6a0-42dc-b209-47866a2cce02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139229708 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.usbdev_csr_mem_rw_with_rand_reset.2139229708
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.625223122
Short name T152
Test name
Test status
Simulation time 29411705 ps
CPU time 0.81 seconds
Started Mar 12 01:01:53 PM PDT 24
Finished Mar 12 01:01:54 PM PDT 24
Peak memory 202456 kb
Host smart-51b591c2-70d1-4f37-8dc8-35b0c411f52a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625223122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.625223122
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2211169201
Short name T742
Test name
Test status
Simulation time 23884896 ps
CPU time 0.61 seconds
Started Mar 12 01:02:00 PM PDT 24
Finished Mar 12 01:02:01 PM PDT 24
Peak memory 201964 kb
Host smart-beefa4f1-159d-443b-95a2-578ad3fdbf8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2211169201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2211169201
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4288146862
Short name T775
Test name
Test status
Simulation time 61083644 ps
CPU time 1.51 seconds
Started Mar 12 01:01:54 PM PDT 24
Finished Mar 12 01:01:56 PM PDT 24
Peak memory 202684 kb
Host smart-104ee642-fbba-43b4-858b-e99146df0b2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288146862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_c
sr_outstanding.4288146862
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.293392443
Short name T40
Test name
Test status
Simulation time 60798535 ps
CPU time 1.78 seconds
Started Mar 12 01:01:56 PM PDT 24
Finished Mar 12 01:01:58 PM PDT 24
Peak memory 202740 kb
Host smart-faee7ec3-452a-45a3-9761-213a7213a4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=293392443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.293392443
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.4129348903
Short name T216
Test name
Test status
Simulation time 142410452 ps
CPU time 2.68 seconds
Started Mar 12 01:02:12 PM PDT 24
Finished Mar 12 01:02:15 PM PDT 24
Peak memory 202700 kb
Host smart-6acfb358-68d2-461b-8fce-edb1c083d781
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4129348903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.4129348903
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1893310827
Short name T143
Test name
Test status
Simulation time 68326212 ps
CPU time 2.01 seconds
Started Mar 12 01:01:53 PM PDT 24
Finished Mar 12 01:01:56 PM PDT 24
Peak memory 210872 kb
Host smart-5f390d47-ccd4-42aa-a0c7-67ea5d4ce99e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893310827 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.usbdev_csr_mem_rw_with_rand_reset.1893310827
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.829638773
Short name T768
Test name
Test status
Simulation time 42534603 ps
CPU time 0.83 seconds
Started Mar 12 01:01:52 PM PDT 24
Finished Mar 12 01:01:53 PM PDT 24
Peak memory 202424 kb
Host smart-f1fa1820-c567-4364-a19a-e1575a249ec7
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829638773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.829638773
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3188939784
Short name T770
Test name
Test status
Simulation time 19881817 ps
CPU time 0.66 seconds
Started Mar 12 01:02:04 PM PDT 24
Finished Mar 12 01:02:05 PM PDT 24
Peak memory 201876 kb
Host smart-9ebbb0b3-7a9c-40b3-a202-0932bb914cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3188939784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3188939784
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3906969502
Short name T750
Test name
Test status
Simulation time 47964557 ps
CPU time 1.34 seconds
Started Mar 12 01:02:05 PM PDT 24
Finished Mar 12 01:02:07 PM PDT 24
Peak memory 202724 kb
Host smart-8442f5af-e469-4fd6-bd46-99b52fea0ee2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906969502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_c
sr_outstanding.3906969502
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2931509446
Short name T139
Test name
Test status
Simulation time 85816034 ps
CPU time 1.32 seconds
Started Mar 12 01:02:02 PM PDT 24
Finished Mar 12 01:02:04 PM PDT 24
Peak memory 202776 kb
Host smart-082f6baf-7674-4328-9088-16a0802b8d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2931509446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2931509446
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3886751932
Short name T217
Test name
Test status
Simulation time 302237819 ps
CPU time 2.76 seconds
Started Mar 12 01:02:07 PM PDT 24
Finished Mar 12 01:02:10 PM PDT 24
Peak memory 202776 kb
Host smart-91f6d4a6-45a6-4b33-88fe-53e2dcea35fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3886751932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3886751932
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2049047372
Short name T777
Test name
Test status
Simulation time 92345180 ps
CPU time 2.65 seconds
Started Mar 12 01:01:53 PM PDT 24
Finished Mar 12 01:01:57 PM PDT 24
Peak memory 210980 kb
Host smart-53e52a78-a2ef-4204-9d63-589e6ae2fad0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049047372 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.usbdev_csr_mem_rw_with_rand_reset.2049047372
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1363089192
Short name T153
Test name
Test status
Simulation time 81649817 ps
CPU time 1.11 seconds
Started Mar 12 01:02:05 PM PDT 24
Finished Mar 12 01:02:07 PM PDT 24
Peak memory 202676 kb
Host smart-44329059-79a2-4fc9-88ef-20a66d5aa8e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363089192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1363089192
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3746846145
Short name T731
Test name
Test status
Simulation time 29111721 ps
CPU time 0.62 seconds
Started Mar 12 01:01:54 PM PDT 24
Finished Mar 12 01:01:54 PM PDT 24
Peak memory 201924 kb
Host smart-0cff460c-5553-41ad-b802-87fbad0cccb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3746846145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3746846145
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2582068744
Short name T149
Test name
Test status
Simulation time 109432345 ps
CPU time 1.32 seconds
Started Mar 12 01:02:16 PM PDT 24
Finished Mar 12 01:02:17 PM PDT 24
Peak memory 202660 kb
Host smart-1e58560f-6e6b-44cf-a8ab-7409042983b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582068744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_c
sr_outstanding.2582068744
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2302725435
Short name T138
Test name
Test status
Simulation time 290922844 ps
CPU time 3 seconds
Started Mar 12 01:02:16 PM PDT 24
Finished Mar 12 01:02:19 PM PDT 24
Peak memory 202704 kb
Host smart-05215ef8-81f8-4be4-a018-644b7f5b56ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2302725435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2302725435
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4256310818
Short name T798
Test name
Test status
Simulation time 153130374 ps
CPU time 1.81 seconds
Started Mar 12 01:01:57 PM PDT 24
Finished Mar 12 01:01:59 PM PDT 24
Peak memory 211040 kb
Host smart-e42ada6f-70b8-4a45-b87b-b537b17792ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256310818 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.usbdev_csr_mem_rw_with_rand_reset.4256310818
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.9084781
Short name T198
Test name
Test status
Simulation time 54771072 ps
CPU time 0.91 seconds
Started Mar 12 01:02:17 PM PDT 24
Finished Mar 12 01:02:18 PM PDT 24
Peak memory 202384 kb
Host smart-f776e8a7-caf0-4b24-90ff-731b1e54b34a
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9084781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.9084781
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1854345102
Short name T714
Test name
Test status
Simulation time 38018800 ps
CPU time 1.01 seconds
Started Mar 12 01:02:22 PM PDT 24
Finished Mar 12 01:02:23 PM PDT 24
Peak memory 202712 kb
Host smart-4de93c22-8e20-4e7b-8dfd-2baa85905c8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854345102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_c
sr_outstanding.1854345102
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2563481233
Short name T137
Test name
Test status
Simulation time 45612101 ps
CPU time 1.31 seconds
Started Mar 12 01:01:50 PM PDT 24
Finished Mar 12 01:01:52 PM PDT 24
Peak memory 202724 kb
Host smart-1cb94a5e-33a4-431d-b59e-0f04e69997a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2563481233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2563481233
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4288652116
Short name T222
Test name
Test status
Simulation time 139369508 ps
CPU time 2.47 seconds
Started Mar 12 01:02:09 PM PDT 24
Finished Mar 12 01:02:12 PM PDT 24
Peak memory 202728 kb
Host smart-1780bd01-6da6-43e8-a0f7-d84bcb9bf463
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4288652116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.4288652116
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.4046955213
Short name T716
Test name
Test status
Simulation time 67321906 ps
CPU time 2.07 seconds
Started Mar 12 01:02:02 PM PDT 24
Finished Mar 12 01:02:05 PM PDT 24
Peak memory 211000 kb
Host smart-7840d24a-0b79-4acd-9a23-4e57f1eb0a43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046955213 -assert nopostproc +UVM_TESTNAME=usb
dev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.usbdev_csr_mem_rw_with_rand_reset.4046955213
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4047761097
Short name T755
Test name
Test status
Simulation time 37526015 ps
CPU time 0.97 seconds
Started Mar 12 01:01:57 PM PDT 24
Finished Mar 12 01:01:58 PM PDT 24
Peak memory 202644 kb
Host smart-77ae6060-bc56-4eef-967e-7d1ac0a29709
User root
Command /workspace/cover_reg_top/simv +csr_rw +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047761097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4047761097
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2961933130
Short name T203
Test name
Test status
Simulation time 28501368 ps
CPU time 0.66 seconds
Started Mar 12 01:01:56 PM PDT 24
Finished Mar 12 01:01:56 PM PDT 24
Peak memory 201892 kb
Host smart-e77f37b1-76ff-4ece-a98e-bc089a51d51c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2961933130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2961933130
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.735000725
Short name T199
Test name
Test status
Simulation time 87727897 ps
CPU time 1.09 seconds
Started Mar 12 01:01:58 PM PDT 24
Finished Mar 12 01:02:00 PM PDT 24
Peak memory 202676 kb
Host smart-25d52dfe-1377-4a0d-b01f-9f62c6cfe821
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +do_clear_all_interrupts=0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735000725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_cs
r_outstanding.735000725
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2573200235
Short name T724
Test name
Test status
Simulation time 137968050 ps
CPU time 1.73 seconds
Started Mar 12 01:02:19 PM PDT 24
Finished Mar 12 01:02:21 PM PDT 24
Peak memory 202764 kb
Host smart-211e157c-1da8-42a5-8be0-a61b58355881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2573200235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2573200235
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3719853311
Short name T28
Test name
Test status
Simulation time 8370494915 ps
CPU time 7.77 seconds
Started Mar 12 02:56:51 PM PDT 24
Finished Mar 12 02:56:59 PM PDT 24
Peak memory 203020 kb
Host smart-e8f0ff43-e96e-49cc-9c24-441e2a2d68b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37198
53311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3719853311
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1583094984
Short name T275
Test name
Test status
Simulation time 218499642 ps
CPU time 1.8 seconds
Started Mar 12 02:56:49 PM PDT 24
Finished Mar 12 02:56:51 PM PDT 24
Peak memory 203028 kb
Host smart-60d0eea0-4106-4868-9b22-4503d3fc8733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15830
94984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1583094984
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.4253303233
Short name T100
Test name
Test status
Simulation time 8381844364 ps
CPU time 8.03 seconds
Started Mar 12 02:56:47 PM PDT 24
Finished Mar 12 02:56:55 PM PDT 24
Peak memory 203020 kb
Host smart-1fa7dc1f-49c9-404f-9755-2a0274da2431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42533
03233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.4253303233
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3401672372
Short name T469
Test name
Test status
Simulation time 8411715950 ps
CPU time 8.47 seconds
Started Mar 12 02:56:47 PM PDT 24
Finished Mar 12 02:56:56 PM PDT 24
Peak memory 203048 kb
Host smart-a52d5fa4-08b6-4d83-b5f5-b97c86954f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34016
72372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3401672372
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.558927039
Short name T713
Test name
Test status
Simulation time 8365524822 ps
CPU time 7.48 seconds
Started Mar 12 02:56:46 PM PDT 24
Finished Mar 12 02:56:54 PM PDT 24
Peak memory 203032 kb
Host smart-caaf06e7-769f-42a8-a225-b75fbd31d698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55892
7039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.558927039
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1239798764
Short name T290
Test name
Test status
Simulation time 8363228944 ps
CPU time 8.14 seconds
Started Mar 12 02:56:49 PM PDT 24
Finished Mar 12 02:56:57 PM PDT 24
Peak memory 203004 kb
Host smart-58867454-1a7e-4fb9-8d14-d524a3ba8e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12397
98764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1239798764
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.533321379
Short name T589
Test name
Test status
Simulation time 27962570 ps
CPU time 0.63 seconds
Started Mar 12 02:56:47 PM PDT 24
Finished Mar 12 02:56:48 PM PDT 24
Peak memory 202936 kb
Host smart-4a9e796f-3540-453d-9661-1ef5e1de7fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53332
1379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.533321379
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.1405380500
Short name T538
Test name
Test status
Simulation time 8403807655 ps
CPU time 7.84 seconds
Started Mar 12 02:56:44 PM PDT 24
Finished Mar 12 02:56:52 PM PDT 24
Peak memory 202988 kb
Host smart-a2254aea-2440-4fca-a46f-5f1605601250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14053
80500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.1405380500
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3992721140
Short name T44
Test name
Test status
Simulation time 80633516 ps
CPU time 0.95 seconds
Started Mar 12 02:56:49 PM PDT 24
Finished Mar 12 02:56:50 PM PDT 24
Peak memory 217404 kb
Host smart-74b40236-6c30-410a-815a-4433497017f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3992721140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3992721140
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_smoke.4036128621
Short name T131
Test name
Test status
Simulation time 8479031663 ps
CPU time 8 seconds
Started Mar 12 02:56:46 PM PDT 24
Finished Mar 12 02:56:55 PM PDT 24
Peak memory 203060 kb
Host smart-49d2d8b9-9f32-4e9d-9edd-58072a8f60bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40361
28621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.4036128621
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1464030773
Short name T160
Test name
Test status
Simulation time 8372777172 ps
CPU time 8.74 seconds
Started Mar 12 02:56:46 PM PDT 24
Finished Mar 12 02:56:55 PM PDT 24
Peak memory 203024 kb
Host smart-8084db87-5a6e-411f-bf60-3e229b341bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14640
30773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1464030773
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3011386601
Short name T382
Test name
Test status
Simulation time 42283112 ps
CPU time 1.18 seconds
Started Mar 12 02:56:47 PM PDT 24
Finished Mar 12 02:56:49 PM PDT 24
Peak memory 202892 kb
Host smart-4056eec6-4620-48bf-8e71-3970f8eeccc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30113
86601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3011386601
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.314653215
Short name T117
Test name
Test status
Simulation time 8408866723 ps
CPU time 9.8 seconds
Started Mar 12 02:56:45 PM PDT 24
Finished Mar 12 02:56:55 PM PDT 24
Peak memory 203028 kb
Host smart-83138148-6783-470e-bd98-cfefcd9e2133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31465
3215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.314653215
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.3489354325
Short name T554
Test name
Test status
Simulation time 8406032399 ps
CPU time 9.82 seconds
Started Mar 12 02:56:47 PM PDT 24
Finished Mar 12 02:56:57 PM PDT 24
Peak memory 202980 kb
Host smart-fb3ed961-1dbc-431a-ad9a-229fdea1ca65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34893
54325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3489354325
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.4241336989
Short name T335
Test name
Test status
Simulation time 8362325129 ps
CPU time 7.11 seconds
Started Mar 12 02:56:48 PM PDT 24
Finished Mar 12 02:56:55 PM PDT 24
Peak memory 203020 kb
Host smart-b8c336ad-fb2f-4297-b271-323e2bf725ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42413
36989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.4241336989
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.304423008
Short name T558
Test name
Test status
Simulation time 8384439472 ps
CPU time 7.39 seconds
Started Mar 12 02:56:44 PM PDT 24
Finished Mar 12 02:56:52 PM PDT 24
Peak memory 203012 kb
Host smart-442db19c-8348-4d4e-8d86-5e379483dc63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30442
3008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.304423008
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3126596609
Short name T542
Test name
Test status
Simulation time 8401166213 ps
CPU time 7.36 seconds
Started Mar 12 02:56:49 PM PDT 24
Finished Mar 12 02:56:57 PM PDT 24
Peak memory 202896 kb
Host smart-76805280-df5c-4222-801f-57ea742c7f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31265
96609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3126596609
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.806197298
Short name T346
Test name
Test status
Simulation time 24658745 ps
CPU time 0.63 seconds
Started Mar 12 02:56:46 PM PDT 24
Finished Mar 12 02:56:47 PM PDT 24
Peak memory 202956 kb
Host smart-f7189892-a01c-4375-ba0a-0aef25011e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80619
7298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.806197298
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3428023500
Short name T641
Test name
Test status
Simulation time 8396396699 ps
CPU time 7.59 seconds
Started Mar 12 02:56:51 PM PDT 24
Finished Mar 12 02:56:59 PM PDT 24
Peak memory 203036 kb
Host smart-f348eb59-834a-4f08-9a90-da754025df16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34280
23500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3428023500
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.346116557
Short name T574
Test name
Test status
Simulation time 8394601477 ps
CPU time 8.22 seconds
Started Mar 12 02:56:47 PM PDT 24
Finished Mar 12 02:56:56 PM PDT 24
Peak memory 203004 kb
Host smart-b8fee956-73e0-4c44-bd31-74e5d1b1e2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34611
6557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.346116557
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.1771279980
Short name T45
Test name
Test status
Simulation time 141556362 ps
CPU time 0.92 seconds
Started Mar 12 02:56:47 PM PDT 24
Finished Mar 12 02:56:48 PM PDT 24
Peak memory 217568 kb
Host smart-1df48dd9-36fe-494f-b376-7f50f3bb8a65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1771279980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.1771279980
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1037242579
Short name T297
Test name
Test status
Simulation time 8358852081 ps
CPU time 7.52 seconds
Started Mar 12 02:56:48 PM PDT 24
Finished Mar 12 02:56:56 PM PDT 24
Peak memory 202980 kb
Host smart-66715f82-0963-4b18-8228-a40732efb244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10372
42579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1037242579
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2570448150
Short name T618
Test name
Test status
Simulation time 8375795265 ps
CPU time 7.59 seconds
Started Mar 12 02:57:26 PM PDT 24
Finished Mar 12 02:57:35 PM PDT 24
Peak memory 203008 kb
Host smart-044164d9-c7d6-4ac8-af07-b0ccb87d43e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25704
48150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2570448150
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.316531856
Short name T611
Test name
Test status
Simulation time 210277145 ps
CPU time 1.91 seconds
Started Mar 12 02:57:20 PM PDT 24
Finished Mar 12 02:57:22 PM PDT 24
Peak memory 202980 kb
Host smart-104cf2d7-aacf-4507-8b4b-6c13443dbd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31653
1856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.316531856
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.623736256
Short name T363
Test name
Test status
Simulation time 8378566758 ps
CPU time 7.93 seconds
Started Mar 12 02:57:14 PM PDT 24
Finished Mar 12 02:57:23 PM PDT 24
Peak memory 202984 kb
Host smart-68f3c19e-0509-4441-8f0d-0c29ec2c2e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62373
6256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.623736256
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3246952326
Short name T349
Test name
Test status
Simulation time 8408307983 ps
CPU time 7.79 seconds
Started Mar 12 02:57:21 PM PDT 24
Finished Mar 12 02:57:29 PM PDT 24
Peak memory 202940 kb
Host smart-c1695dc0-b9eb-43a1-8eca-e1fd0a91ef69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32469
52326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3246952326
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1733029625
Short name T644
Test name
Test status
Simulation time 8361288039 ps
CPU time 9.79 seconds
Started Mar 12 02:57:15 PM PDT 24
Finished Mar 12 02:57:25 PM PDT 24
Peak memory 202992 kb
Host smart-f5277d01-b618-41d1-ae8a-410a8f645bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17330
29625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1733029625
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1946073248
Short name T418
Test name
Test status
Simulation time 8393280628 ps
CPU time 7.59 seconds
Started Mar 12 02:57:15 PM PDT 24
Finished Mar 12 02:57:23 PM PDT 24
Peak memory 203000 kb
Host smart-8e286455-6622-4071-ab24-db360e74e98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19460
73248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1946073248
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.459040043
Short name T599
Test name
Test status
Simulation time 8400102804 ps
CPU time 7.95 seconds
Started Mar 12 02:57:13 PM PDT 24
Finished Mar 12 02:57:22 PM PDT 24
Peak memory 203028 kb
Host smart-481698b9-65fc-4a25-a383-54a9f89e84b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45904
0043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.459040043
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3988569611
Short name T347
Test name
Test status
Simulation time 27558894 ps
CPU time 0.7 seconds
Started Mar 12 02:57:21 PM PDT 24
Finished Mar 12 02:57:22 PM PDT 24
Peak memory 202932 kb
Host smart-dd1aea49-9098-436f-890a-309350ab9df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39885
69611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3988569611
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.3989382220
Short name T555
Test name
Test status
Simulation time 8413497452 ps
CPU time 7.59 seconds
Started Mar 12 02:57:13 PM PDT 24
Finished Mar 12 02:57:21 PM PDT 24
Peak memory 203024 kb
Host smart-73ad1cad-23ca-4812-ab88-ad777077061b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39893
82220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3989382220
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.2785658794
Short name T306
Test name
Test status
Simulation time 8375517782 ps
CPU time 7.03 seconds
Started Mar 12 02:57:17 PM PDT 24
Finished Mar 12 02:57:24 PM PDT 24
Peak memory 202860 kb
Host smart-3cf7ae69-9c57-42a1-8a4b-5806414f40a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27856
58794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.2785658794
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3698229016
Short name T670
Test name
Test status
Simulation time 8361166797 ps
CPU time 7.47 seconds
Started Mar 12 02:57:16 PM PDT 24
Finished Mar 12 02:57:24 PM PDT 24
Peak memory 203020 kb
Host smart-0824ad33-bb18-4f33-93d9-7c20f320bb5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36982
29016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3698229016
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1401641384
Short name T544
Test name
Test status
Simulation time 8477998508 ps
CPU time 8.29 seconds
Started Mar 12 02:57:14 PM PDT 24
Finished Mar 12 02:57:23 PM PDT 24
Peak memory 203056 kb
Host smart-e433374b-fce0-4798-b576-b046c9d65d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14016
41384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1401641384
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.841568150
Short name T336
Test name
Test status
Simulation time 8369632836 ps
CPU time 7.54 seconds
Started Mar 12 02:57:13 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 203004 kb
Host smart-d044e731-3b8c-44fe-9f2e-d428601faf8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84156
8150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.841568150
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2485128419
Short name T38
Test name
Test status
Simulation time 137819744 ps
CPU time 1.6 seconds
Started Mar 12 02:57:19 PM PDT 24
Finished Mar 12 02:57:21 PM PDT 24
Peak memory 202992 kb
Host smart-ade5c464-6ee5-40f3-a4a3-47015c509f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24851
28419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2485128419
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.2269546032
Short name T375
Test name
Test status
Simulation time 8439226854 ps
CPU time 8.81 seconds
Started Mar 12 02:57:26 PM PDT 24
Finished Mar 12 02:57:36 PM PDT 24
Peak memory 203004 kb
Host smart-c952411b-4e6e-4670-bdde-fb9e6647c3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22695
46032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.2269546032
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3124194179
Short name T621
Test name
Test status
Simulation time 8406132379 ps
CPU time 7 seconds
Started Mar 12 02:57:16 PM PDT 24
Finished Mar 12 02:57:23 PM PDT 24
Peak memory 203020 kb
Host smart-de618c21-27d0-4ea0-bc02-42303e0c45ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31241
94179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3124194179
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.117286089
Short name T571
Test name
Test status
Simulation time 8367024868 ps
CPU time 7.13 seconds
Started Mar 12 02:57:16 PM PDT 24
Finished Mar 12 02:57:23 PM PDT 24
Peak memory 203028 kb
Host smart-b6aca4a5-8e00-4b8b-a217-dc9df039921b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11728
6089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.117286089
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.327972243
Short name T562
Test name
Test status
Simulation time 8376878642 ps
CPU time 8.31 seconds
Started Mar 12 02:57:17 PM PDT 24
Finished Mar 12 02:57:25 PM PDT 24
Peak memory 203032 kb
Host smart-7fc8d1b3-9c62-4a4f-8a5c-e7a83bdaf945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32797
2243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.327972243
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.4095384202
Short name T597
Test name
Test status
Simulation time 8400123397 ps
CPU time 9.03 seconds
Started Mar 12 02:57:20 PM PDT 24
Finished Mar 12 02:57:29 PM PDT 24
Peak memory 202932 kb
Host smart-1c9ded4e-865f-46b7-9c2f-a54bd00e232a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40953
84202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.4095384202
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1433953594
Short name T248
Test name
Test status
Simulation time 22324498 ps
CPU time 0.65 seconds
Started Mar 12 02:57:17 PM PDT 24
Finished Mar 12 02:57:17 PM PDT 24
Peak memory 202960 kb
Host smart-009f7d05-8299-4cc8-8b97-128031b3d351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14339
53594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1433953594
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.538214850
Short name T519
Test name
Test status
Simulation time 8432777559 ps
CPU time 7.93 seconds
Started Mar 12 02:57:37 PM PDT 24
Finished Mar 12 02:57:45 PM PDT 24
Peak memory 202848 kb
Host smart-9726df3d-ca2e-4a52-80c5-6646549f6076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53821
4850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.538214850
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.3042286357
Short name T443
Test name
Test status
Simulation time 8404779043 ps
CPU time 7.41 seconds
Started Mar 12 02:57:20 PM PDT 24
Finished Mar 12 02:57:27 PM PDT 24
Peak memory 202932 kb
Host smart-cf8f0ea5-194c-4137-8105-c98ac3d6c587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30422
86357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.3042286357
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3324804159
Short name T503
Test name
Test status
Simulation time 8359561205 ps
CPU time 7.15 seconds
Started Mar 12 02:57:16 PM PDT 24
Finished Mar 12 02:57:23 PM PDT 24
Peak memory 202856 kb
Host smart-bbfe7a2b-bbb2-4d93-b1b1-ce4a42486e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33248
04159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3324804159
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.4160768187
Short name T672
Test name
Test status
Simulation time 8471588633 ps
CPU time 7.9 seconds
Started Mar 12 02:57:14 PM PDT 24
Finished Mar 12 02:57:22 PM PDT 24
Peak memory 203028 kb
Host smart-e6f76d4d-d846-4f5c-82c3-78927683a9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41607
68187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.4160768187
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1898331499
Short name T467
Test name
Test status
Simulation time 8368669427 ps
CPU time 7.68 seconds
Started Mar 12 02:57:25 PM PDT 24
Finished Mar 12 02:57:34 PM PDT 24
Peak memory 202932 kb
Host smart-6fd7540e-4a3f-4dec-9e51-0c1298a57ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18983
31499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1898331499
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3691174343
Short name T701
Test name
Test status
Simulation time 98851655 ps
CPU time 1.36 seconds
Started Mar 12 02:57:25 PM PDT 24
Finished Mar 12 02:57:28 PM PDT 24
Peak memory 202976 kb
Host smart-8f99c705-da1e-48b3-8698-708506e4f938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36911
74343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3691174343
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3828516022
Short name T371
Test name
Test status
Simulation time 8450602464 ps
CPU time 7.71 seconds
Started Mar 12 02:57:25 PM PDT 24
Finished Mar 12 02:57:34 PM PDT 24
Peak memory 203008 kb
Host smart-5c6e8446-d8a1-4ebb-acd4-9c4c55bbd13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38285
16022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3828516022
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3436707889
Short name T241
Test name
Test status
Simulation time 8409372339 ps
CPU time 8.64 seconds
Started Mar 12 02:57:26 PM PDT 24
Finished Mar 12 02:57:36 PM PDT 24
Peak memory 203016 kb
Host smart-3289d81b-82fc-47ca-8515-cf686b5621e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34367
07889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3436707889
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1241705242
Short name T684
Test name
Test status
Simulation time 8364176866 ps
CPU time 7.13 seconds
Started Mar 12 02:57:30 PM PDT 24
Finished Mar 12 02:57:38 PM PDT 24
Peak memory 202996 kb
Host smart-eeaa11af-499b-4a9f-aae4-b60e934d7826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12417
05242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1241705242
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2339153028
Short name T304
Test name
Test status
Simulation time 8371292684 ps
CPU time 7.24 seconds
Started Mar 12 02:57:23 PM PDT 24
Finished Mar 12 02:57:31 PM PDT 24
Peak memory 203012 kb
Host smart-f8eaffc3-85b5-4cb7-9301-796392a5afae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23391
53028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2339153028
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3491334114
Short name T403
Test name
Test status
Simulation time 8384120909 ps
CPU time 10.02 seconds
Started Mar 12 02:57:29 PM PDT 24
Finished Mar 12 02:57:40 PM PDT 24
Peak memory 202948 kb
Host smart-40041c8e-9d51-41ee-8045-8d313fa0d686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34913
34114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3491334114
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1298115488
Short name T358
Test name
Test status
Simulation time 31295308 ps
CPU time 0.64 seconds
Started Mar 12 02:57:25 PM PDT 24
Finished Mar 12 02:57:27 PM PDT 24
Peak memory 202956 kb
Host smart-613e663f-83d3-45b7-89c9-dddff6b5af6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12981
15488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1298115488
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3103467750
Short name T425
Test name
Test status
Simulation time 8404442982 ps
CPU time 8.06 seconds
Started Mar 12 02:57:29 PM PDT 24
Finished Mar 12 02:57:38 PM PDT 24
Peak memory 203008 kb
Host smart-b0fb02ac-b1d6-4aff-969f-cc34cf4b5cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31034
67750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3103467750
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.626995621
Short name T629
Test name
Test status
Simulation time 8397202000 ps
CPU time 8.3 seconds
Started Mar 12 02:57:26 PM PDT 24
Finished Mar 12 02:57:36 PM PDT 24
Peak memory 203008 kb
Host smart-ce48b7b2-d3ac-416d-9018-4f39440610b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62699
5621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.626995621
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3747722846
Short name T697
Test name
Test status
Simulation time 8361537359 ps
CPU time 7.63 seconds
Started Mar 12 02:57:28 PM PDT 24
Finished Mar 12 02:57:37 PM PDT 24
Peak memory 202992 kb
Host smart-fbe2daef-96e5-400e-9558-77ce66239925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37477
22846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3747722846
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2191490321
Short name T1
Test name
Test status
Simulation time 8367571772 ps
CPU time 7.94 seconds
Started Mar 12 02:57:33 PM PDT 24
Finished Mar 12 02:57:42 PM PDT 24
Peak memory 202972 kb
Host smart-23edb304-0b60-4b8b-8381-9db3b01cc7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21914
90321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2191490321
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3918469280
Short name T573
Test name
Test status
Simulation time 8404214334 ps
CPU time 7.34 seconds
Started Mar 12 02:57:32 PM PDT 24
Finished Mar 12 02:57:40 PM PDT 24
Peak memory 203048 kb
Host smart-2db490f2-9e3f-4d29-8fdb-16eb30276c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39184
69280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3918469280
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.216278261
Short name T399
Test name
Test status
Simulation time 8359273944 ps
CPU time 7.6 seconds
Started Mar 12 02:57:32 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 202988 kb
Host smart-5264eaca-799b-4699-aba8-62c986692dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21627
8261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.216278261
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.666968850
Short name T383
Test name
Test status
Simulation time 8401764441 ps
CPU time 7.76 seconds
Started Mar 12 02:57:29 PM PDT 24
Finished Mar 12 02:57:38 PM PDT 24
Peak memory 203000 kb
Host smart-d82ef525-fa90-4fb1-aa9b-a88ca2a9161c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66696
8850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.666968850
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.31758386
Short name T272
Test name
Test status
Simulation time 8360458230 ps
CPU time 9.27 seconds
Started Mar 12 02:57:29 PM PDT 24
Finished Mar 12 02:57:40 PM PDT 24
Peak memory 202988 kb
Host smart-15c131c2-c416-4187-b73b-22c5f5c14a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31758
386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.31758386
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2006636045
Short name T395
Test name
Test status
Simulation time 8368769240 ps
CPU time 7.58 seconds
Started Mar 12 02:57:32 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 203032 kb
Host smart-f3344cd8-bdcf-4e83-9700-6c6fcc073d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20066
36045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2006636045
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2608189803
Short name T671
Test name
Test status
Simulation time 28722072 ps
CPU time 0.61 seconds
Started Mar 12 02:57:31 PM PDT 24
Finished Mar 12 02:57:32 PM PDT 24
Peak memory 202924 kb
Host smart-91eaaa79-1515-495c-b3f3-f1443e461947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26081
89803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2608189803
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2842742631
Short name T634
Test name
Test status
Simulation time 8441770570 ps
CPU time 7.38 seconds
Started Mar 12 02:57:34 PM PDT 24
Finished Mar 12 02:57:42 PM PDT 24
Peak memory 202936 kb
Host smart-52c4240f-6d9b-4e63-93ee-450655793513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28427
42631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2842742631
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.3923373598
Short name T656
Test name
Test status
Simulation time 8371530543 ps
CPU time 7.73 seconds
Started Mar 12 02:57:33 PM PDT 24
Finished Mar 12 02:57:42 PM PDT 24
Peak memory 202996 kb
Host smart-f8fa58b9-01fb-47ab-adcc-4ea562ba76e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39233
73598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.3923373598
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.684639061
Short name T279
Test name
Test status
Simulation time 8360173317 ps
CPU time 7.78 seconds
Started Mar 12 02:57:35 PM PDT 24
Finished Mar 12 02:57:44 PM PDT 24
Peak memory 202932 kb
Host smart-ee2bfb6a-7a2b-429f-8153-912c85183b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68463
9061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.684639061
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.2721083018
Short name T267
Test name
Test status
Simulation time 8474561117 ps
CPU time 7.27 seconds
Started Mar 12 02:57:30 PM PDT 24
Finished Mar 12 02:57:38 PM PDT 24
Peak memory 203048 kb
Host smart-0afd36c8-e033-4149-b2b4-a0eb9cac0fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27210
83018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2721083018
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3318205127
Short name T559
Test name
Test status
Simulation time 8370741377 ps
CPU time 8.19 seconds
Started Mar 12 02:57:31 PM PDT 24
Finished Mar 12 02:57:40 PM PDT 24
Peak memory 202980 kb
Host smart-8f253370-635c-4994-b116-006bd89123d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33182
05127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3318205127
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.4192688966
Short name T660
Test name
Test status
Simulation time 55565367 ps
CPU time 1.58 seconds
Started Mar 12 02:57:34 PM PDT 24
Finished Mar 12 02:57:36 PM PDT 24
Peak memory 203008 kb
Host smart-65c25896-1fdd-4f49-a6c1-a43beae78546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41926
88966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.4192688966
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.100524109
Short name T444
Test name
Test status
Simulation time 8453542021 ps
CPU time 7.73 seconds
Started Mar 12 02:57:31 PM PDT 24
Finished Mar 12 02:57:39 PM PDT 24
Peak memory 203040 kb
Host smart-d3dfb20c-316a-4132-826e-5aa183d560e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10052
4109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.100524109
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1264556419
Short name T270
Test name
Test status
Simulation time 8407740447 ps
CPU time 8.06 seconds
Started Mar 12 02:57:32 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 203016 kb
Host smart-52b047e3-5755-47cb-8cab-aa42ecf7bc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12645
56419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1264556419
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1273119628
Short name T350
Test name
Test status
Simulation time 8362587328 ps
CPU time 7.58 seconds
Started Mar 12 02:57:32 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 203024 kb
Host smart-22172f34-3ecf-4799-afb2-4e3e0697c689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12731
19628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1273119628
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.2016758777
Short name T504
Test name
Test status
Simulation time 8368016814 ps
CPU time 7.52 seconds
Started Mar 12 02:57:34 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 202992 kb
Host smart-498ce60f-6b43-454f-8da9-7548edbdc0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20167
58777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.2016758777
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1639709624
Short name T575
Test name
Test status
Simulation time 8380013702 ps
CPU time 7.1 seconds
Started Mar 12 02:57:30 PM PDT 24
Finished Mar 12 02:57:38 PM PDT 24
Peak memory 202992 kb
Host smart-d56bcf9a-7d9e-48c2-b860-13186bd9968a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16397
09624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1639709624
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2293751124
Short name T22
Test name
Test status
Simulation time 30639093 ps
CPU time 0.63 seconds
Started Mar 12 02:57:27 PM PDT 24
Finished Mar 12 02:57:29 PM PDT 24
Peak memory 202936 kb
Host smart-049d8db8-aacd-44c3-9723-2a499798b085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22937
51124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2293751124
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.1985625373
Short name T471
Test name
Test status
Simulation time 8455240172 ps
CPU time 7.97 seconds
Started Mar 12 02:57:36 PM PDT 24
Finished Mar 12 02:57:45 PM PDT 24
Peak memory 202988 kb
Host smart-9f843967-3304-4179-8164-fac51508d839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19856
25373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1985625373
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.1212511714
Short name T317
Test name
Test status
Simulation time 8382905203 ps
CPU time 7.29 seconds
Started Mar 12 02:57:32 PM PDT 24
Finished Mar 12 02:57:40 PM PDT 24
Peak memory 202236 kb
Host smart-d0422770-00c7-4e3f-94f0-bf3e0076bf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12125
11714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.1212511714
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1058670720
Short name T260
Test name
Test status
Simulation time 8362183737 ps
CPU time 7.48 seconds
Started Mar 12 02:57:31 PM PDT 24
Finished Mar 12 02:57:39 PM PDT 24
Peak memory 203020 kb
Host smart-a62bf5ce-1321-4751-880c-8b6505ff722a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10586
70720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1058670720
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1991231422
Short name T68
Test name
Test status
Simulation time 8474800096 ps
CPU time 7.44 seconds
Started Mar 12 02:57:32 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 203044 kb
Host smart-827d086d-3e91-47df-a0e2-39ed1c874902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19912
31422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1991231422
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.4184141506
Short name T609
Test name
Test status
Simulation time 8370734873 ps
CPU time 7.3 seconds
Started Mar 12 02:57:31 PM PDT 24
Finished Mar 12 02:57:39 PM PDT 24
Peak memory 202936 kb
Host smart-33fd30dc-1870-4f00-919d-cf4e362e96f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41841
41506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.4184141506
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1098229182
Short name T166
Test name
Test status
Simulation time 149646442 ps
CPU time 1.46 seconds
Started Mar 12 02:57:36 PM PDT 24
Finished Mar 12 02:57:38 PM PDT 24
Peak memory 203016 kb
Host smart-2c02a526-aeed-4c4b-93b9-93c2f8f33026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10982
29182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1098229182
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2461090356
Short name T101
Test name
Test status
Simulation time 8376484515 ps
CPU time 10.14 seconds
Started Mar 12 02:57:31 PM PDT 24
Finished Mar 12 02:57:42 PM PDT 24
Peak memory 202984 kb
Host smart-3617913d-19fc-4f61-a7dc-4d15134628b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24610
90356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2461090356
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.24503906
Short name T675
Test name
Test status
Simulation time 8406929451 ps
CPU time 9.24 seconds
Started Mar 12 02:57:31 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 202940 kb
Host smart-6eab4816-9044-4d91-8712-3478eeee160f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24503
906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.24503906
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1066721819
Short name T460
Test name
Test status
Simulation time 8365336993 ps
CPU time 7.59 seconds
Started Mar 12 02:57:30 PM PDT 24
Finished Mar 12 02:57:39 PM PDT 24
Peak memory 202908 kb
Host smart-625f1412-1e03-47ed-a6d8-2aa2e6b22710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10667
21819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1066721819
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.856365971
Short name T71
Test name
Test status
Simulation time 8435375297 ps
CPU time 9.81 seconds
Started Mar 12 02:57:31 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 202988 kb
Host smart-6a2e6c5a-e802-46df-87c2-99485393499a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85636
5971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.856365971
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2625322282
Short name T195
Test name
Test status
Simulation time 8376646866 ps
CPU time 7.73 seconds
Started Mar 12 02:57:36 PM PDT 24
Finished Mar 12 02:57:44 PM PDT 24
Peak memory 202988 kb
Host smart-04ff9467-c68b-4b65-80ff-361404a50d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26253
22282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2625322282
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3057351733
Short name T539
Test name
Test status
Simulation time 8409406910 ps
CPU time 8.55 seconds
Started Mar 12 02:57:36 PM PDT 24
Finished Mar 12 02:57:45 PM PDT 24
Peak memory 203016 kb
Host smart-3a95f109-471e-4691-b022-eaaebf96f730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30573
51733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3057351733
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3256721078
Short name T602
Test name
Test status
Simulation time 26620870 ps
CPU time 0.61 seconds
Started Mar 12 02:57:34 PM PDT 24
Finished Mar 12 02:57:35 PM PDT 24
Peak memory 202852 kb
Host smart-a726aa49-f8a7-42b6-863c-1e7c94578589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32567
21078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3256721078
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3035280369
Short name T636
Test name
Test status
Simulation time 8377550147 ps
CPU time 9.59 seconds
Started Mar 12 02:57:30 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 203020 kb
Host smart-1791685e-7332-45c7-9948-f21d86414de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30352
80369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3035280369
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.716873571
Short name T263
Test name
Test status
Simulation time 8400885383 ps
CPU time 7.4 seconds
Started Mar 12 02:57:37 PM PDT 24
Finished Mar 12 02:57:45 PM PDT 24
Peak memory 202988 kb
Host smart-4b9f5865-4293-4805-9477-71c58b8df05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71687
3571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.716873571
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.4049764708
Short name T13
Test name
Test status
Simulation time 8354964660 ps
CPU time 7.06 seconds
Started Mar 12 02:57:31 PM PDT 24
Finished Mar 12 02:57:39 PM PDT 24
Peak memory 202968 kb
Host smart-693a3ce6-b1d5-4c97-b15e-d0169b7fab3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40497
64708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.4049764708
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2796188531
Short name T127
Test name
Test status
Simulation time 8469308515 ps
CPU time 7.96 seconds
Started Mar 12 02:57:32 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 203012 kb
Host smart-8029f1aa-fe18-43ee-8281-7f3a1b274ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27961
88531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2796188531
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2008605688
Short name T238
Test name
Test status
Simulation time 8370327394 ps
CPU time 7.66 seconds
Started Mar 12 02:57:30 PM PDT 24
Finished Mar 12 02:57:39 PM PDT 24
Peak memory 202980 kb
Host smart-ed79e0a5-4b68-468f-ba44-75bf0dd817c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20086
05688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2008605688
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.66184374
Short name T547
Test name
Test status
Simulation time 51777356 ps
CPU time 1.33 seconds
Started Mar 12 02:57:34 PM PDT 24
Finished Mar 12 02:57:35 PM PDT 24
Peak memory 202684 kb
Host smart-7dc77793-6833-47ed-9300-2f418139f93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66184
374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.66184374
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1017911405
Short name T591
Test name
Test status
Simulation time 8412603433 ps
CPU time 7.5 seconds
Started Mar 12 02:57:32 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 202996 kb
Host smart-d32b1b61-32ed-4727-80fe-be73e14ca233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10179
11405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1017911405
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.196715988
Short name T676
Test name
Test status
Simulation time 8408186938 ps
CPU time 7.47 seconds
Started Mar 12 02:57:34 PM PDT 24
Finished Mar 12 02:57:42 PM PDT 24
Peak memory 202940 kb
Host smart-fc5b28d2-fbb3-4f3f-bb38-457b5c4e745e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19671
5988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.196715988
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3233515496
Short name T324
Test name
Test status
Simulation time 8367142880 ps
CPU time 9.37 seconds
Started Mar 12 02:57:46 PM PDT 24
Finished Mar 12 02:57:55 PM PDT 24
Peak memory 203028 kb
Host smart-171f37c3-0f0a-4186-a451-4507f6a3fe4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32335
15496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3233515496
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1012223757
Short name T294
Test name
Test status
Simulation time 8396144602 ps
CPU time 9.02 seconds
Started Mar 12 02:57:37 PM PDT 24
Finished Mar 12 02:57:47 PM PDT 24
Peak memory 203024 kb
Host smart-a1d220ad-5d2b-45e1-ae8f-f35e6476fa3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10122
23757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1012223757
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2616882141
Short name T312
Test name
Test status
Simulation time 8380682334 ps
CPU time 7.87 seconds
Started Mar 12 02:57:39 PM PDT 24
Finished Mar 12 02:57:47 PM PDT 24
Peak memory 203008 kb
Host smart-08e859d6-8402-4b09-8ad9-46701aa9edae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26168
82141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2616882141
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3325016839
Short name T441
Test name
Test status
Simulation time 8389210753 ps
CPU time 7.35 seconds
Started Mar 12 02:57:37 PM PDT 24
Finished Mar 12 02:57:45 PM PDT 24
Peak memory 203036 kb
Host smart-e37c2d2e-80e1-4e16-95df-f1b3dfdd0ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33250
16839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3325016839
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.3602175450
Short name T296
Test name
Test status
Simulation time 8400755567 ps
CPU time 7.33 seconds
Started Mar 12 02:57:40 PM PDT 24
Finished Mar 12 02:57:47 PM PDT 24
Peak memory 202972 kb
Host smart-c72e1ada-af12-4ae3-94fc-e59430d711f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36021
75450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.3602175450
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.3511517133
Short name T405
Test name
Test status
Simulation time 8356374266 ps
CPU time 9.4 seconds
Started Mar 12 02:57:39 PM PDT 24
Finished Mar 12 02:57:49 PM PDT 24
Peak memory 203024 kb
Host smart-57c3671e-5778-4c22-9180-9889499bb7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35115
17133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3511517133
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3799062488
Short name T24
Test name
Test status
Simulation time 8371119744 ps
CPU time 9.14 seconds
Started Mar 12 02:57:39 PM PDT 24
Finished Mar 12 02:57:48 PM PDT 24
Peak memory 202904 kb
Host smart-0bfa9655-c939-4db4-9e96-61333b00e118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37990
62488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3799062488
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2100639752
Short name T615
Test name
Test status
Simulation time 57131321 ps
CPU time 1.68 seconds
Started Mar 12 02:57:39 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 203016 kb
Host smart-93d88400-df8f-47a6-8d4e-3d723896640b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21006
39752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2100639752
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2723479687
Short name T365
Test name
Test status
Simulation time 8404008879 ps
CPU time 8.54 seconds
Started Mar 12 02:57:41 PM PDT 24
Finished Mar 12 02:57:49 PM PDT 24
Peak memory 202980 kb
Host smart-1ddd385f-931c-4d87-95ea-f714e0b69a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27234
79687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2723479687
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1188815789
Short name T577
Test name
Test status
Simulation time 8408868867 ps
CPU time 7.81 seconds
Started Mar 12 02:57:39 PM PDT 24
Finished Mar 12 02:57:47 PM PDT 24
Peak memory 202988 kb
Host smart-3a696a25-220c-4a7c-9202-020377d4cd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11888
15789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1188815789
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1959522412
Short name T61
Test name
Test status
Simulation time 8364254777 ps
CPU time 7.32 seconds
Started Mar 12 02:57:37 PM PDT 24
Finished Mar 12 02:57:44 PM PDT 24
Peak memory 202992 kb
Host smart-98c7f899-8c3d-4bcc-ae5d-bc196042109a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19595
22412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1959522412
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2988158775
Short name T711
Test name
Test status
Simulation time 8368441623 ps
CPU time 7.89 seconds
Started Mar 12 02:57:40 PM PDT 24
Finished Mar 12 02:57:48 PM PDT 24
Peak memory 202952 kb
Host smart-0b59e7f6-ec69-441d-ac88-7eebd6a9cab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29881
58775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2988158775
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2411031178
Short name T237
Test name
Test status
Simulation time 8387506480 ps
CPU time 7.41 seconds
Started Mar 12 02:57:37 PM PDT 24
Finished Mar 12 02:57:45 PM PDT 24
Peak memory 202964 kb
Host smart-b8b91c33-3a0b-4cdd-b7d6-32325578079c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24110
31178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2411031178
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2540330040
Short name T709
Test name
Test status
Simulation time 29610906 ps
CPU time 0.67 seconds
Started Mar 12 02:57:38 PM PDT 24
Finished Mar 12 02:57:40 PM PDT 24
Peak memory 202924 kb
Host smart-01ce9d9d-07a7-443f-80b9-11b514d9f58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25403
30040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2540330040
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1775521099
Short name T388
Test name
Test status
Simulation time 8447762910 ps
CPU time 7.61 seconds
Started Mar 12 02:57:43 PM PDT 24
Finished Mar 12 02:57:51 PM PDT 24
Peak memory 203012 kb
Host smart-828857a3-8471-405b-aa6f-6a7edff4c965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17755
21099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1775521099
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.105568863
Short name T301
Test name
Test status
Simulation time 8369217419 ps
CPU time 7.09 seconds
Started Mar 12 02:57:36 PM PDT 24
Finished Mar 12 02:57:43 PM PDT 24
Peak memory 203028 kb
Host smart-15233e74-2b3f-4539-b5a6-7a5d862ac91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10556
8863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.105568863
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2915290594
Short name T620
Test name
Test status
Simulation time 8357275569 ps
CPU time 7.05 seconds
Started Mar 12 02:57:40 PM PDT 24
Finished Mar 12 02:57:47 PM PDT 24
Peak memory 202992 kb
Host smart-083b3e1c-96c8-461a-8b2e-4a420bd6afbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29152
90594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2915290594
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2820781110
Short name T685
Test name
Test status
Simulation time 8476490134 ps
CPU time 9.85 seconds
Started Mar 12 02:57:40 PM PDT 24
Finished Mar 12 02:57:50 PM PDT 24
Peak memory 203012 kb
Host smart-1ec77f2e-d17b-4b65-b5ae-b1c355ff2c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28207
81110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2820781110
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.734140699
Short name T466
Test name
Test status
Simulation time 8373100160 ps
CPU time 10.01 seconds
Started Mar 12 02:57:40 PM PDT 24
Finished Mar 12 02:57:50 PM PDT 24
Peak memory 202980 kb
Host smart-d37d6b43-ea54-4637-8a13-9009f7c56803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73414
0699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.734140699
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1503855056
Short name T494
Test name
Test status
Simulation time 51575167 ps
CPU time 1.35 seconds
Started Mar 12 02:57:38 PM PDT 24
Finished Mar 12 02:57:40 PM PDT 24
Peak memory 202952 kb
Host smart-b00ff655-8091-4394-89cd-f6ad4e9722ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15038
55056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1503855056
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1376761050
Short name T487
Test name
Test status
Simulation time 8446755164 ps
CPU time 7.8 seconds
Started Mar 12 02:57:39 PM PDT 24
Finished Mar 12 02:57:47 PM PDT 24
Peak memory 202960 kb
Host smart-86ce2e65-c31c-47d5-88e0-38a24d27ba0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13767
61050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1376761050
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1809928486
Short name T372
Test name
Test status
Simulation time 8406444538 ps
CPU time 7.19 seconds
Started Mar 12 02:57:40 PM PDT 24
Finished Mar 12 02:57:48 PM PDT 24
Peak memory 203024 kb
Host smart-edaf7e6c-326c-4b83-8ba1-7f0142aec527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18099
28486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1809928486
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3235580646
Short name T461
Test name
Test status
Simulation time 8361111035 ps
CPU time 9.76 seconds
Started Mar 12 02:57:40 PM PDT 24
Finished Mar 12 02:57:50 PM PDT 24
Peak memory 202972 kb
Host smart-019c6181-f41b-49b9-b2c8-355aeb9a6de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32355
80646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3235580646
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.3325479746
Short name T90
Test name
Test status
Simulation time 8434693409 ps
CPU time 9.8 seconds
Started Mar 12 02:57:45 PM PDT 24
Finished Mar 12 02:57:55 PM PDT 24
Peak memory 203040 kb
Host smart-8eea34b7-5216-438e-957e-58db31a0fd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33254
79746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.3325479746
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1316379154
Short name T172
Test name
Test status
Simulation time 8388533166 ps
CPU time 9.38 seconds
Started Mar 12 02:57:39 PM PDT 24
Finished Mar 12 02:57:48 PM PDT 24
Peak memory 202988 kb
Host smart-efb3de1b-1361-4f3e-9fc1-124de8c011d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13163
79154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1316379154
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.318157449
Short name T345
Test name
Test status
Simulation time 8404175267 ps
CPU time 9.3 seconds
Started Mar 12 02:57:38 PM PDT 24
Finished Mar 12 02:57:48 PM PDT 24
Peak memory 203016 kb
Host smart-bf83e797-34b1-4445-90e7-372019221082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31815
7449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.318157449
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2290565428
Short name T552
Test name
Test status
Simulation time 26331139 ps
CPU time 0.67 seconds
Started Mar 12 02:57:41 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 202952 kb
Host smart-26baee12-a938-4478-ae2c-d4e911ec220d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22905
65428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2290565428
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1321646883
Short name T637
Test name
Test status
Simulation time 8435615704 ps
CPU time 7.2 seconds
Started Mar 12 02:57:38 PM PDT 24
Finished Mar 12 02:57:45 PM PDT 24
Peak memory 202944 kb
Host smart-69d1a796-003f-46cf-83fe-256c6926cb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13216
46883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1321646883
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.747170257
Short name T490
Test name
Test status
Simulation time 8375764219 ps
CPU time 9.37 seconds
Started Mar 12 02:57:38 PM PDT 24
Finished Mar 12 02:57:48 PM PDT 24
Peak memory 203032 kb
Host smart-2b3b13f7-1c9d-46a3-9518-022369a9a678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74717
0257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.747170257
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.128760453
Short name T698
Test name
Test status
Simulation time 8357469889 ps
CPU time 7.28 seconds
Started Mar 12 02:57:42 PM PDT 24
Finished Mar 12 02:57:49 PM PDT 24
Peak memory 202980 kb
Host smart-765f6674-17be-497f-8988-fdae1d09022c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12876
0453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.128760453
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.3143562271
Short name T37
Test name
Test status
Simulation time 8370601159 ps
CPU time 7.51 seconds
Started Mar 12 02:57:40 PM PDT 24
Finished Mar 12 02:57:48 PM PDT 24
Peak memory 203008 kb
Host smart-47a2532f-423f-4f94-9a83-9fd69b09b119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31435
62271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3143562271
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.802971711
Short name T690
Test name
Test status
Simulation time 38142428 ps
CPU time 0.96 seconds
Started Mar 12 02:57:40 PM PDT 24
Finished Mar 12 02:57:41 PM PDT 24
Peak memory 202960 kb
Host smart-794f7a26-6164-4674-b85e-14655108d1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80297
1711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.802971711
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3959997437
Short name T695
Test name
Test status
Simulation time 8423710031 ps
CPU time 7.23 seconds
Started Mar 12 02:57:40 PM PDT 24
Finished Mar 12 02:57:48 PM PDT 24
Peak memory 203044 kb
Host smart-30862eed-8080-402f-839f-413ee434abe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39599
97437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3959997437
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1831788031
Short name T437
Test name
Test status
Simulation time 8411332102 ps
CPU time 8.4 seconds
Started Mar 12 02:57:43 PM PDT 24
Finished Mar 12 02:57:51 PM PDT 24
Peak memory 202984 kb
Host smart-382668d8-fc96-4707-b6e1-92f894e52101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18317
88031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1831788031
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.681991819
Short name T223
Test name
Test status
Simulation time 8362570521 ps
CPU time 7.52 seconds
Started Mar 12 02:57:38 PM PDT 24
Finished Mar 12 02:57:46 PM PDT 24
Peak memory 202948 kb
Host smart-bd71ec18-5994-4066-96fb-15ce48568f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68199
1819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.681991819
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3376099438
Short name T256
Test name
Test status
Simulation time 8401432383 ps
CPU time 7.62 seconds
Started Mar 12 02:57:41 PM PDT 24
Finished Mar 12 02:57:49 PM PDT 24
Peak memory 203024 kb
Host smart-8921b097-ea5b-429d-9279-83f3f6e437fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33760
99438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3376099438
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1378317155
Short name T302
Test name
Test status
Simulation time 8398184396 ps
CPU time 8.97 seconds
Started Mar 12 02:57:42 PM PDT 24
Finished Mar 12 02:57:51 PM PDT 24
Peak memory 203024 kb
Host smart-0bc0a677-088e-4559-b0d4-34d2911c19c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13783
17155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1378317155
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2146547251
Short name T265
Test name
Test status
Simulation time 24314781 ps
CPU time 0.65 seconds
Started Mar 12 02:57:51 PM PDT 24
Finished Mar 12 02:57:51 PM PDT 24
Peak memory 202948 kb
Host smart-3e86584b-5ec4-4ac5-a9bd-0c552659d29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21465
47251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2146547251
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3331080339
Short name T115
Test name
Test status
Simulation time 8439070122 ps
CPU time 7.39 seconds
Started Mar 12 02:57:46 PM PDT 24
Finished Mar 12 02:57:54 PM PDT 24
Peak memory 203036 kb
Host smart-068acb2c-f136-46f0-8663-df05ce1ef321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33310
80339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3331080339
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.1292685417
Short name T681
Test name
Test status
Simulation time 8401778579 ps
CPU time 9.48 seconds
Started Mar 12 02:57:39 PM PDT 24
Finished Mar 12 02:57:49 PM PDT 24
Peak memory 202960 kb
Host smart-beb2c350-0ff3-4ba6-9a81-3e8d9409d657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12926
85417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.1292685417
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2330698477
Short name T374
Test name
Test status
Simulation time 8355747771 ps
CPU time 8.3 seconds
Started Mar 12 02:57:43 PM PDT 24
Finished Mar 12 02:57:51 PM PDT 24
Peak memory 202996 kb
Host smart-ae05d348-5d38-4af2-aa01-b4858bc74b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23306
98477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2330698477
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.1640188536
Short name T278
Test name
Test status
Simulation time 8475852799 ps
CPU time 8.61 seconds
Started Mar 12 02:57:40 PM PDT 24
Finished Mar 12 02:57:49 PM PDT 24
Peak memory 203024 kb
Host smart-aeec6095-8405-4f70-a070-3be254e9bdad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16401
88536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.1640188536
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1531202833
Short name T353
Test name
Test status
Simulation time 8366995506 ps
CPU time 7.33 seconds
Started Mar 12 02:56:49 PM PDT 24
Finished Mar 12 02:56:56 PM PDT 24
Peak memory 202952 kb
Host smart-d8b3df91-a27f-46fa-a2ec-a897509b9d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15312
02833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1531202833
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.609071304
Short name T331
Test name
Test status
Simulation time 45431190 ps
CPU time 1.25 seconds
Started Mar 12 02:56:48 PM PDT 24
Finished Mar 12 02:56:49 PM PDT 24
Peak memory 203056 kb
Host smart-24ce9e04-b4f2-4c8d-afe4-396da321d0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60907
1304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.609071304
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.125531760
Short name T426
Test name
Test status
Simulation time 8385303601 ps
CPU time 7.31 seconds
Started Mar 12 02:56:44 PM PDT 24
Finished Mar 12 02:56:52 PM PDT 24
Peak memory 203024 kb
Host smart-0f00b6b3-15cb-4e03-a63c-749d584a5b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12553
1760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.125531760
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.827814313
Short name T522
Test name
Test status
Simulation time 8410957526 ps
CPU time 9.39 seconds
Started Mar 12 02:56:46 PM PDT 24
Finished Mar 12 02:56:56 PM PDT 24
Peak memory 203040 kb
Host smart-3ed0914b-dca6-41d3-9b1f-6c2625dcbd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82781
4313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.827814313
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.4135202309
Short name T659
Test name
Test status
Simulation time 8362136767 ps
CPU time 7.36 seconds
Started Mar 12 02:56:45 PM PDT 24
Finished Mar 12 02:56:52 PM PDT 24
Peak memory 202936 kb
Host smart-7bdf118f-df7b-45fb-8a08-5e6ea3ff96d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41352
02309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.4135202309
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.2226830756
Short name T680
Test name
Test status
Simulation time 8384251872 ps
CPU time 7.59 seconds
Started Mar 12 02:56:51 PM PDT 24
Finished Mar 12 02:57:00 PM PDT 24
Peak memory 202952 kb
Host smart-37f53a2c-9e9a-47de-b466-35979abe1e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22268
30756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.2226830756
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2343376295
Short name T239
Test name
Test status
Simulation time 8361959619 ps
CPU time 7.35 seconds
Started Mar 12 02:56:45 PM PDT 24
Finished Mar 12 02:56:53 PM PDT 24
Peak memory 203032 kb
Host smart-b3ab2f2e-8607-4cbb-809b-d779f683c046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23433
76295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2343376295
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3668569777
Short name T288
Test name
Test status
Simulation time 28857600 ps
CPU time 0.63 seconds
Started Mar 12 02:56:53 PM PDT 24
Finished Mar 12 02:56:54 PM PDT 24
Peak memory 202816 kb
Host smart-f9f80199-c51e-4c25-812d-ea67ed86bb8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36685
69777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3668569777
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3786962298
Short name T649
Test name
Test status
Simulation time 8452306897 ps
CPU time 8.48 seconds
Started Mar 12 02:56:53 PM PDT 24
Finished Mar 12 02:57:02 PM PDT 24
Peak memory 202936 kb
Host smart-1fb0796b-8a30-46e3-afb0-6a35269c66a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37869
62298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3786962298
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.288807410
Short name T643
Test name
Test status
Simulation time 8377704205 ps
CPU time 8.27 seconds
Started Mar 12 02:56:51 PM PDT 24
Finished Mar 12 02:56:59 PM PDT 24
Peak memory 203032 kb
Host smart-eb4985ea-ef29-4bc9-a126-07acad4161c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28880
7410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.288807410
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2134329906
Short name T58
Test name
Test status
Simulation time 85019386 ps
CPU time 0.95 seconds
Started Mar 12 02:56:53 PM PDT 24
Finished Mar 12 02:56:55 PM PDT 24
Peak memory 217412 kb
Host smart-a7b7bfd8-0547-488e-a6c7-94d249d2676e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2134329906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2134329906
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2636186136
Short name T376
Test name
Test status
Simulation time 8358430200 ps
CPU time 8.79 seconds
Started Mar 12 02:56:46 PM PDT 24
Finished Mar 12 02:56:55 PM PDT 24
Peak memory 203000 kb
Host smart-d3875606-cb44-4ab8-a77c-9076cf8421ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26361
86136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2636186136
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2000497303
Short name T448
Test name
Test status
Simulation time 8368957621 ps
CPU time 8.83 seconds
Started Mar 12 02:57:54 PM PDT 24
Finished Mar 12 02:58:03 PM PDT 24
Peak memory 202996 kb
Host smart-18c2aecc-2be1-4239-9339-e68c582cb6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20004
97303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2000497303
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1380819646
Short name T500
Test name
Test status
Simulation time 283162107 ps
CPU time 2.27 seconds
Started Mar 12 02:57:49 PM PDT 24
Finished Mar 12 02:57:51 PM PDT 24
Peak memory 203020 kb
Host smart-d503debe-e934-4569-a084-141d166f13a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13808
19646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1380819646
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3944327788
Short name T499
Test name
Test status
Simulation time 8392077223 ps
CPU time 7.52 seconds
Started Mar 12 02:57:49 PM PDT 24
Finished Mar 12 02:57:57 PM PDT 24
Peak memory 203032 kb
Host smart-decaa5c8-e7bd-4b8a-8109-bcd671e8de3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39443
27788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3944327788
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3715528588
Short name T658
Test name
Test status
Simulation time 8407942346 ps
CPU time 7.31 seconds
Started Mar 12 02:57:54 PM PDT 24
Finished Mar 12 02:58:02 PM PDT 24
Peak memory 203000 kb
Host smart-c691a325-5edc-492a-baca-3ec85bec061c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37155
28588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3715528588
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1979417980
Short name T227
Test name
Test status
Simulation time 8364103953 ps
CPU time 7.25 seconds
Started Mar 12 02:57:55 PM PDT 24
Finished Mar 12 02:58:02 PM PDT 24
Peak memory 203008 kb
Host smart-3c64bf65-1c53-4a82-8dec-9653a4e1d393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794
17980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1979417980
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2265156456
Short name T598
Test name
Test status
Simulation time 8378526740 ps
CPU time 8.3 seconds
Started Mar 12 02:57:49 PM PDT 24
Finished Mar 12 02:57:57 PM PDT 24
Peak memory 202992 kb
Host smart-3b3d21f3-5d8e-4912-99ec-685f210e19e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22651
56456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2265156456
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.1855910884
Short name T692
Test name
Test status
Simulation time 8397719244 ps
CPU time 8.1 seconds
Started Mar 12 02:57:50 PM PDT 24
Finished Mar 12 02:57:58 PM PDT 24
Peak memory 203024 kb
Host smart-9102ae30-a369-4c82-9159-01f0c8ff85e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18559
10884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.1855910884
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3802949648
Short name T367
Test name
Test status
Simulation time 26953483 ps
CPU time 0.65 seconds
Started Mar 12 02:57:55 PM PDT 24
Finished Mar 12 02:57:55 PM PDT 24
Peak memory 202932 kb
Host smart-b1d30b4e-008a-43ef-b6e7-57cfff48488b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38029
49648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3802949648
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3327791808
Short name T484
Test name
Test status
Simulation time 8399956028 ps
CPU time 7.4 seconds
Started Mar 12 02:57:48 PM PDT 24
Finished Mar 12 02:57:56 PM PDT 24
Peak memory 202944 kb
Host smart-ee72988a-0f2e-482b-9be8-d72b6adefda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33277
91808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3327791808
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3984671410
Short name T470
Test name
Test status
Simulation time 8392011380 ps
CPU time 7.89 seconds
Started Mar 12 02:57:53 PM PDT 24
Finished Mar 12 02:58:01 PM PDT 24
Peak memory 202928 kb
Host smart-5b9404e3-1af2-4f91-839a-53bdbf9d1c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39846
71410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3984671410
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1917815306
Short name T333
Test name
Test status
Simulation time 8357083201 ps
CPU time 9.91 seconds
Started Mar 12 02:57:48 PM PDT 24
Finished Mar 12 02:57:58 PM PDT 24
Peak memory 202984 kb
Host smart-3cd1d2e0-35f5-4caa-aab0-15723909db2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19178
15306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1917815306
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1298673925
Short name T678
Test name
Test status
Simulation time 8369970556 ps
CPU time 9.12 seconds
Started Mar 12 02:57:51 PM PDT 24
Finished Mar 12 02:58:01 PM PDT 24
Peak memory 202988 kb
Host smart-272144b0-4d45-4042-9bb6-7569b9d84cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12986
73925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1298673925
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3391929140
Short name T187
Test name
Test status
Simulation time 158612232 ps
CPU time 1.48 seconds
Started Mar 12 02:57:46 PM PDT 24
Finished Mar 12 02:57:48 PM PDT 24
Peak memory 203056 kb
Host smart-100aac8c-accf-4869-837a-287df2d49d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33919
29140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3391929140
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1370895608
Short name T551
Test name
Test status
Simulation time 8454042506 ps
CPU time 9.37 seconds
Started Mar 12 02:57:45 PM PDT 24
Finished Mar 12 02:57:54 PM PDT 24
Peak memory 202952 kb
Host smart-75e16e4e-a49a-4a63-b802-9f8f5a8d7845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13708
95608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1370895608
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1281886249
Short name T563
Test name
Test status
Simulation time 8404954946 ps
CPU time 8.44 seconds
Started Mar 12 02:57:49 PM PDT 24
Finished Mar 12 02:57:57 PM PDT 24
Peak memory 202964 kb
Host smart-db697926-b3a1-4e65-835c-00e7ec0f4e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12818
86249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1281886249
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3664432938
Short name T635
Test name
Test status
Simulation time 8367876670 ps
CPU time 7.9 seconds
Started Mar 12 02:57:49 PM PDT 24
Finished Mar 12 02:57:57 PM PDT 24
Peak memory 203032 kb
Host smart-2587af7f-1e93-4f1a-9acf-58663f826111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36644
32938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3664432938
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2346261809
Short name T587
Test name
Test status
Simulation time 8417834521 ps
CPU time 7.76 seconds
Started Mar 12 02:57:51 PM PDT 24
Finished Mar 12 02:57:59 PM PDT 24
Peak memory 203036 kb
Host smart-3e69d801-f16f-41cb-b68b-13b02e3cb04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23462
61809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2346261809
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3122224876
Short name T246
Test name
Test status
Simulation time 8391463372 ps
CPU time 7.79 seconds
Started Mar 12 02:57:47 PM PDT 24
Finished Mar 12 02:57:55 PM PDT 24
Peak memory 203024 kb
Host smart-9bf73914-06d5-4d9a-842a-050f579dc8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31222
24876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3122224876
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3357322478
Short name T230
Test name
Test status
Simulation time 8400290947 ps
CPU time 7.69 seconds
Started Mar 12 02:57:51 PM PDT 24
Finished Mar 12 02:57:59 PM PDT 24
Peak memory 203020 kb
Host smart-40cf6024-f441-447d-867a-30ac98b891d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33573
22478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3357322478
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2708125985
Short name T505
Test name
Test status
Simulation time 26829445 ps
CPU time 0.67 seconds
Started Mar 12 02:57:57 PM PDT 24
Finished Mar 12 02:57:58 PM PDT 24
Peak memory 202944 kb
Host smart-b71b19ae-d22e-4be8-b224-152f481b5202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27081
25985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2708125985
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3372199113
Short name T710
Test name
Test status
Simulation time 8421764337 ps
CPU time 7.33 seconds
Started Mar 12 02:57:48 PM PDT 24
Finished Mar 12 02:57:55 PM PDT 24
Peak memory 202896 kb
Host smart-29867a05-561c-4c6e-9e22-b42a17505235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33721
99113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3372199113
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1333734540
Short name T352
Test name
Test status
Simulation time 8390151797 ps
CPU time 7.14 seconds
Started Mar 12 02:57:47 PM PDT 24
Finished Mar 12 02:57:54 PM PDT 24
Peak memory 203004 kb
Host smart-32b5bdbf-7912-419b-acf1-18cbe2b7bc19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13337
34540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1333734540
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2857800674
Short name T243
Test name
Test status
Simulation time 8359451648 ps
CPU time 9.32 seconds
Started Mar 12 02:57:47 PM PDT 24
Finished Mar 12 02:57:57 PM PDT 24
Peak memory 202952 kb
Host smart-76e30a6e-103a-4674-a835-26a512629330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28578
00674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2857800674
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3333873409
Short name T535
Test name
Test status
Simulation time 8481022090 ps
CPU time 7.81 seconds
Started Mar 12 02:57:48 PM PDT 24
Finished Mar 12 02:57:55 PM PDT 24
Peak memory 202968 kb
Host smart-57d398a3-7650-494d-8b84-18d24340303e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33338
73409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3333873409
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.28432738
Short name T450
Test name
Test status
Simulation time 8372587758 ps
CPU time 9.24 seconds
Started Mar 12 02:57:58 PM PDT 24
Finished Mar 12 02:58:07 PM PDT 24
Peak memory 203000 kb
Host smart-92784406-9504-4153-914b-f4fa032d4813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28432
738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.28432738
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.531050527
Short name T225
Test name
Test status
Simulation time 157247451 ps
CPU time 1.41 seconds
Started Mar 12 02:57:56 PM PDT 24
Finished Mar 12 02:57:57 PM PDT 24
Peak memory 203044 kb
Host smart-e0f7c8ae-8969-480d-ba7d-1eaf9e42c19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53105
0527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.531050527
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.501475675
Short name T440
Test name
Test status
Simulation time 8381385351 ps
CPU time 9.42 seconds
Started Mar 12 02:57:54 PM PDT 24
Finished Mar 12 02:58:03 PM PDT 24
Peak memory 202976 kb
Host smart-41b60009-2b07-4151-a3b9-05d2899fa3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50147
5675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.501475675
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2148587296
Short name T366
Test name
Test status
Simulation time 8406294099 ps
CPU time 7.26 seconds
Started Mar 12 02:57:55 PM PDT 24
Finished Mar 12 02:58:02 PM PDT 24
Peak memory 202944 kb
Host smart-a3a933cd-45e6-4973-bd98-930d6d7eebf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21485
87296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2148587296
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.1938349363
Short name T561
Test name
Test status
Simulation time 8367369017 ps
CPU time 7.39 seconds
Started Mar 12 02:57:53 PM PDT 24
Finished Mar 12 02:58:00 PM PDT 24
Peak memory 203028 kb
Host smart-5926f3ba-7204-44a6-aeec-087e5d38e79e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19383
49363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.1938349363
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2682200226
Short name T86
Test name
Test status
Simulation time 8402730120 ps
CPU time 7.28 seconds
Started Mar 12 02:57:56 PM PDT 24
Finished Mar 12 02:58:03 PM PDT 24
Peak memory 202952 kb
Host smart-9952ff53-ba8f-4f23-ae07-b3d91a35febf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26822
00226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2682200226
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1328041062
Short name T584
Test name
Test status
Simulation time 8374292324 ps
CPU time 7.19 seconds
Started Mar 12 02:57:56 PM PDT 24
Finished Mar 12 02:58:03 PM PDT 24
Peak memory 203000 kb
Host smart-7a815cff-6773-42a4-99c0-e8eb0ce69976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13280
41062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1328041062
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2538870452
Short name T628
Test name
Test status
Simulation time 8399434528 ps
CPU time 7.87 seconds
Started Mar 12 02:57:56 PM PDT 24
Finished Mar 12 02:58:04 PM PDT 24
Peak memory 203040 kb
Host smart-940349f6-cdda-4bd0-9d57-edbb967cd741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25388
70452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2538870452
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3747188932
Short name T594
Test name
Test status
Simulation time 29227217 ps
CPU time 0.62 seconds
Started Mar 12 02:57:59 PM PDT 24
Finished Mar 12 02:58:00 PM PDT 24
Peak memory 202928 kb
Host smart-48572a97-fc00-4c4b-a3c8-4896c0bb76e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37471
88932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3747188932
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.230259563
Short name T313
Test name
Test status
Simulation time 8452765744 ps
CPU time 9.43 seconds
Started Mar 12 02:57:57 PM PDT 24
Finished Mar 12 02:58:06 PM PDT 24
Peak memory 203000 kb
Host smart-1d09c48d-b9d4-43cb-9771-55d74f24f14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23025
9563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.230259563
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.3927864086
Short name T623
Test name
Test status
Simulation time 8377413043 ps
CPU time 9.46 seconds
Started Mar 12 02:57:53 PM PDT 24
Finished Mar 12 02:58:02 PM PDT 24
Peak memory 203028 kb
Host smart-2a191031-0999-4a53-ba33-0283b0c50103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39278
64086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.3927864086
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3966488373
Short name T332
Test name
Test status
Simulation time 8361859120 ps
CPU time 9.65 seconds
Started Mar 12 02:57:55 PM PDT 24
Finished Mar 12 02:58:05 PM PDT 24
Peak memory 203000 kb
Host smart-3c1a7c44-54ec-4fd3-b848-4985ff23d817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39664
88373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3966488373
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1252506976
Short name T124
Test name
Test status
Simulation time 8481784469 ps
CPU time 7.71 seconds
Started Mar 12 02:57:55 PM PDT 24
Finished Mar 12 02:58:03 PM PDT 24
Peak memory 203056 kb
Host smart-c3161113-9513-498b-912e-4bd5a57f92b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12525
06976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1252506976
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2794077720
Short name T415
Test name
Test status
Simulation time 8371071018 ps
CPU time 9.13 seconds
Started Mar 12 02:57:56 PM PDT 24
Finished Mar 12 02:58:05 PM PDT 24
Peak memory 202984 kb
Host smart-d889e62a-bcfe-4d9f-9ce5-032a4fbac3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27940
77720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2794077720
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1385670701
Short name T173
Test name
Test status
Simulation time 104780358 ps
CPU time 1.65 seconds
Started Mar 12 02:57:58 PM PDT 24
Finished Mar 12 02:58:00 PM PDT 24
Peak memory 203000 kb
Host smart-8d63d784-9407-4391-873e-ada5941aaf2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13856
70701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1385670701
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3632322492
Short name T473
Test name
Test status
Simulation time 8410262277 ps
CPU time 9.38 seconds
Started Mar 12 02:57:55 PM PDT 24
Finished Mar 12 02:58:05 PM PDT 24
Peak memory 202936 kb
Host smart-12381fff-9605-4e6b-94bd-a3279689d320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36323
22492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3632322492
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2575950519
Short name T385
Test name
Test status
Simulation time 8366185064 ps
CPU time 7.91 seconds
Started Mar 12 02:58:00 PM PDT 24
Finished Mar 12 02:58:08 PM PDT 24
Peak memory 203016 kb
Host smart-f96d21a1-31b3-457e-99f4-dcbdc1b2b8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25759
50519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2575950519
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1732968476
Short name T359
Test name
Test status
Simulation time 8399861299 ps
CPU time 8.38 seconds
Started Mar 12 02:57:55 PM PDT 24
Finished Mar 12 02:58:03 PM PDT 24
Peak memory 203004 kb
Host smart-0b422dac-064f-4f5a-a81d-8b46b97effef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17329
68476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1732968476
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2221885678
Short name T245
Test name
Test status
Simulation time 8407514148 ps
CPU time 7.58 seconds
Started Mar 12 02:57:57 PM PDT 24
Finished Mar 12 02:58:05 PM PDT 24
Peak memory 202996 kb
Host smart-bda8aef2-d264-45a5-9272-c108942f833d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22218
85678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2221885678
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1417649892
Short name T325
Test name
Test status
Simulation time 27649130 ps
CPU time 0.65 seconds
Started Mar 12 02:58:08 PM PDT 24
Finished Mar 12 02:58:08 PM PDT 24
Peak memory 202872 kb
Host smart-80724c1b-7da8-45fd-aa65-243dfab365f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14176
49892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1417649892
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3554132527
Short name T10
Test name
Test status
Simulation time 8404146164 ps
CPU time 9.14 seconds
Started Mar 12 02:57:53 PM PDT 24
Finished Mar 12 02:58:02 PM PDT 24
Peak memory 202992 kb
Host smart-1ffd1de6-b11e-4c47-a29f-ee091d0a1294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35541
32527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3554132527
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.453835555
Short name T557
Test name
Test status
Simulation time 8402829055 ps
CPU time 7.27 seconds
Started Mar 12 02:57:56 PM PDT 24
Finished Mar 12 02:58:03 PM PDT 24
Peak memory 203004 kb
Host smart-a7ff95b8-7cd0-4382-880d-73d2c231da5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45383
5555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.453835555
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.689060814
Short name T15
Test name
Test status
Simulation time 8363124785 ps
CPU time 7.76 seconds
Started Mar 12 02:58:08 PM PDT 24
Finished Mar 12 02:58:16 PM PDT 24
Peak memory 203016 kb
Host smart-311d7d48-c128-46db-830c-4d15590cd82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68906
0814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.689060814
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1215844107
Short name T666
Test name
Test status
Simulation time 8473528590 ps
CPU time 10.06 seconds
Started Mar 12 02:57:57 PM PDT 24
Finished Mar 12 02:58:07 PM PDT 24
Peak memory 203012 kb
Host smart-91aa44d9-804b-4473-bd2b-c3a45db865dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12158
44107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1215844107
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.24608794
Short name T610
Test name
Test status
Simulation time 8368851574 ps
CPU time 7.13 seconds
Started Mar 12 02:58:04 PM PDT 24
Finished Mar 12 02:58:11 PM PDT 24
Peak memory 202880 kb
Host smart-bd4a4bc3-603d-40c8-8c2a-a336a448f77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24608
794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.24608794
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3234871546
Short name T404
Test name
Test status
Simulation time 54938559 ps
CPU time 1.54 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:07 PM PDT 24
Peak memory 203096 kb
Host smart-81d6c4a4-6806-4394-9f4a-1c11f0ee23c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32348
71546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3234871546
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1960622717
Short name T120
Test name
Test status
Simulation time 8463642068 ps
CPU time 7.84 seconds
Started Mar 12 02:58:06 PM PDT 24
Finished Mar 12 02:58:14 PM PDT 24
Peak memory 202996 kb
Host smart-fc840f53-c137-498c-9ca6-1aa20b03cefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19606
22717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1960622717
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.340379334
Short name T453
Test name
Test status
Simulation time 8408475255 ps
CPU time 8.4 seconds
Started Mar 12 02:58:03 PM PDT 24
Finished Mar 12 02:58:11 PM PDT 24
Peak memory 202972 kb
Host smart-39ab6075-be88-4662-855b-64ac61716c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34037
9334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.340379334
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.349958009
Short name T387
Test name
Test status
Simulation time 8361474308 ps
CPU time 7.31 seconds
Started Mar 12 02:58:12 PM PDT 24
Finished Mar 12 02:58:19 PM PDT 24
Peak memory 202932 kb
Host smart-de30d5f0-0a98-4c57-9b28-a14d95a4d1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34995
8009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.349958009
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1733711046
Short name T74
Test name
Test status
Simulation time 8410171422 ps
CPU time 7.52 seconds
Started Mar 12 02:58:06 PM PDT 24
Finished Mar 12 02:58:14 PM PDT 24
Peak memory 202956 kb
Host smart-c75d2eaa-449a-4c49-990c-3c8ffcd885d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17337
11046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1733711046
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3576604800
Short name T457
Test name
Test status
Simulation time 8361092599 ps
CPU time 7.28 seconds
Started Mar 12 02:58:08 PM PDT 24
Finished Mar 12 02:58:16 PM PDT 24
Peak memory 202940 kb
Host smart-c2f745a2-0a38-46a1-81a1-f79ae48ffe83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35766
04800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3576604800
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.562375739
Short name T17
Test name
Test status
Simulation time 8385401087 ps
CPU time 9.99 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:15 PM PDT 24
Peak memory 202936 kb
Host smart-10da9009-94fd-4f04-beec-612bdd1aa09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56237
5739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.562375739
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.1172992217
Short name T462
Test name
Test status
Simulation time 26545657 ps
CPU time 0.63 seconds
Started Mar 12 02:58:12 PM PDT 24
Finished Mar 12 02:58:13 PM PDT 24
Peak memory 202856 kb
Host smart-bd07ed4e-6bcb-4581-8c3f-9a19f56f2e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11729
92217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.1172992217
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1917006091
Short name T342
Test name
Test status
Simulation time 8421042809 ps
CPU time 8.69 seconds
Started Mar 12 02:58:06 PM PDT 24
Finished Mar 12 02:58:15 PM PDT 24
Peak memory 202988 kb
Host smart-c364b90d-7b1b-4475-bb66-958c17696119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19170
06091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1917006091
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.1961345773
Short name T661
Test name
Test status
Simulation time 8386031890 ps
CPU time 7.11 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:12 PM PDT 24
Peak memory 203000 kb
Host smart-5b0a3ad8-2c44-4638-a11a-d8190c764a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19613
45773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.1961345773
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1121596410
Short name T601
Test name
Test status
Simulation time 8360915274 ps
CPU time 7.82 seconds
Started Mar 12 02:58:08 PM PDT 24
Finished Mar 12 02:58:15 PM PDT 24
Peak memory 202984 kb
Host smart-9591b2b2-8602-42c0-a672-297efeb2f087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215
96410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1121596410
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3602317757
Short name T26
Test name
Test status
Simulation time 8475022671 ps
CPU time 7.75 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:13 PM PDT 24
Peak memory 203052 kb
Host smart-5d5be109-aa78-44ff-bf79-d01f297d4485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36023
17757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3602317757
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1854176484
Short name T273
Test name
Test status
Simulation time 8365672437 ps
CPU time 7.86 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:13 PM PDT 24
Peak memory 202872 kb
Host smart-9cc39e8a-2d3c-4af1-ba60-fd231bc6624e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18541
76484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1854176484
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.696895905
Short name T226
Test name
Test status
Simulation time 71173306 ps
CPU time 1.97 seconds
Started Mar 12 02:58:12 PM PDT 24
Finished Mar 12 02:58:14 PM PDT 24
Peak memory 203000 kb
Host smart-11324c19-6afa-491e-b13c-427e295d700c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69689
5905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.696895905
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.810598823
Short name T186
Test name
Test status
Simulation time 8445917785 ps
CPU time 8.15 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:13 PM PDT 24
Peak memory 203036 kb
Host smart-1d7a87c0-a24b-4421-afe5-b7a58cc4f8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81059
8823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.810598823
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3481197320
Short name T488
Test name
Test status
Simulation time 8403741834 ps
CPU time 6.95 seconds
Started Mar 12 02:58:07 PM PDT 24
Finished Mar 12 02:58:14 PM PDT 24
Peak memory 203024 kb
Host smart-2fa6d02e-b517-4c7f-b983-4d655293b84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34811
97320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3481197320
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.320215752
Short name T689
Test name
Test status
Simulation time 8362258364 ps
CPU time 7.56 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:12 PM PDT 24
Peak memory 202864 kb
Host smart-f65bb9ff-c3f0-4776-96f7-219da5b35082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32021
5752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.320215752
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2007747484
Short name T264
Test name
Test status
Simulation time 8410408177 ps
CPU time 8.05 seconds
Started Mar 12 02:58:08 PM PDT 24
Finished Mar 12 02:58:16 PM PDT 24
Peak memory 202992 kb
Host smart-908c0724-7c3c-457b-9e72-81c735f39561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20077
47484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2007747484
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1976805653
Short name T175
Test name
Test status
Simulation time 8405073439 ps
CPU time 7.98 seconds
Started Mar 12 02:58:07 PM PDT 24
Finished Mar 12 02:58:15 PM PDT 24
Peak memory 203032 kb
Host smart-f4a842c3-5c5a-43dc-b7b5-6d59131943c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19768
05653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1976805653
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1360263274
Short name T592
Test name
Test status
Simulation time 27191839 ps
CPU time 0.65 seconds
Started Mar 12 02:58:12 PM PDT 24
Finished Mar 12 02:58:13 PM PDT 24
Peak memory 202856 kb
Host smart-b558dbb1-7e18-4786-90ad-8040901839ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13602
63274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1360263274
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.422920888
Short name T674
Test name
Test status
Simulation time 8409591732 ps
CPU time 8.47 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:14 PM PDT 24
Peak memory 202992 kb
Host smart-4978a7c0-db1c-4c36-bdd4-1abc54f312a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42292
0888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.422920888
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.1172645420
Short name T327
Test name
Test status
Simulation time 8408588180 ps
CPU time 8.64 seconds
Started Mar 12 02:58:03 PM PDT 24
Finished Mar 12 02:58:11 PM PDT 24
Peak memory 203008 kb
Host smart-d25b1f74-ccdc-4819-97d1-22e57cb2dc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11726
45420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.1172645420
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.215841827
Short name T384
Test name
Test status
Simulation time 8354813069 ps
CPU time 7.26 seconds
Started Mar 12 02:58:03 PM PDT 24
Finished Mar 12 02:58:10 PM PDT 24
Peak memory 203020 kb
Host smart-d51b33de-2aa0-485d-a32f-0a802aeedd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21584
1827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.215841827
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.239761148
Short name T109
Test name
Test status
Simulation time 8479496919 ps
CPU time 8.29 seconds
Started Mar 12 02:58:08 PM PDT 24
Finished Mar 12 02:58:16 PM PDT 24
Peak memory 203048 kb
Host smart-017775c9-22ab-42f2-9697-7e7738cc4695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23976
1148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.239761148
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3744179712
Short name T593
Test name
Test status
Simulation time 8368671369 ps
CPU time 9.71 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:15 PM PDT 24
Peak memory 203000 kb
Host smart-151b6ab0-9af3-4486-bdb0-ba70a1902b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37441
79712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3744179712
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.621935618
Short name T512
Test name
Test status
Simulation time 143372504 ps
CPU time 1.77 seconds
Started Mar 12 02:58:03 PM PDT 24
Finished Mar 12 02:58:05 PM PDT 24
Peak memory 203060 kb
Host smart-7c8e8329-9f6f-4629-b7f6-96469bf4f9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62193
5618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.621935618
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2078304166
Short name T447
Test name
Test status
Simulation time 8437489093 ps
CPU time 7.49 seconds
Started Mar 12 02:58:04 PM PDT 24
Finished Mar 12 02:58:12 PM PDT 24
Peak memory 203000 kb
Host smart-9b1beeaf-ee7e-4bb6-80b4-1957978bf158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20783
04166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2078304166
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1976427413
Short name T475
Test name
Test status
Simulation time 8406839461 ps
CPU time 9.93 seconds
Started Mar 12 02:58:10 PM PDT 24
Finished Mar 12 02:58:20 PM PDT 24
Peak memory 203048 kb
Host smart-c911da3c-776a-4c09-b724-b88322e6fd72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19764
27413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1976427413
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.631663818
Short name T174
Test name
Test status
Simulation time 8360012535 ps
CPU time 7.39 seconds
Started Mar 12 02:58:10 PM PDT 24
Finished Mar 12 02:58:18 PM PDT 24
Peak memory 203000 kb
Host smart-9864e7fa-ce4b-4be6-b0e7-ade96dcf2e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63166
3818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.631663818
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2291320443
Short name T646
Test name
Test status
Simulation time 8391328852 ps
CPU time 8.25 seconds
Started Mar 12 02:58:09 PM PDT 24
Finished Mar 12 02:58:18 PM PDT 24
Peak memory 203004 kb
Host smart-2327becf-9a1f-41bf-9603-9544a5c5adb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22913
20443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2291320443
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.575825621
Short name T506
Test name
Test status
Simulation time 8402526056 ps
CPU time 7.32 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:12 PM PDT 24
Peak memory 202948 kb
Host smart-a9cb0be1-8004-4bcf-96df-67dd056902c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57582
5621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.575825621
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2332049435
Short name T655
Test name
Test status
Simulation time 8393691280 ps
CPU time 7.51 seconds
Started Mar 12 02:58:04 PM PDT 24
Finished Mar 12 02:58:11 PM PDT 24
Peak memory 203008 kb
Host smart-34b189c2-c1f7-48cc-a1c9-32b6eb55bb33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23320
49435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2332049435
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3304349060
Short name T258
Test name
Test status
Simulation time 28474339 ps
CPU time 0.65 seconds
Started Mar 12 02:58:04 PM PDT 24
Finished Mar 12 02:58:05 PM PDT 24
Peak memory 202876 kb
Host smart-8032254d-e0ea-4f83-b649-690719f1e7e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33043
49060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3304349060
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.4048515441
Short name T533
Test name
Test status
Simulation time 8389295827 ps
CPU time 8.44 seconds
Started Mar 12 02:58:04 PM PDT 24
Finished Mar 12 02:58:13 PM PDT 24
Peak memory 202988 kb
Host smart-da638b54-28ad-442c-a30e-ed84f8a77aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40485
15441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.4048515441
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.351440854
Short name T581
Test name
Test status
Simulation time 8383959982 ps
CPU time 7.56 seconds
Started Mar 12 02:58:08 PM PDT 24
Finished Mar 12 02:58:16 PM PDT 24
Peak memory 202936 kb
Host smart-c6ebe8ac-59bd-4dcc-913b-810198b6d1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35144
0854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.351440854
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.826350493
Short name T326
Test name
Test status
Simulation time 8360027854 ps
CPU time 7.79 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:13 PM PDT 24
Peak memory 203028 kb
Host smart-77f1dfc3-a2c8-4b1e-b4f0-eda37c16581b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82635
0493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.826350493
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.370606358
Short name T377
Test name
Test status
Simulation time 8472504646 ps
CPU time 7.57 seconds
Started Mar 12 02:58:03 PM PDT 24
Finished Mar 12 02:58:10 PM PDT 24
Peak memory 203032 kb
Host smart-65d2a6ab-f08b-491c-ac21-6bf8c307374b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37060
6358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.370606358
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2205913701
Short name T427
Test name
Test status
Simulation time 8373881580 ps
CPU time 7.33 seconds
Started Mar 12 02:58:04 PM PDT 24
Finished Mar 12 02:58:12 PM PDT 24
Peak memory 203020 kb
Host smart-b23d2290-19cd-4b81-9452-1dc148996147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22059
13701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2205913701
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3325169244
Short name T619
Test name
Test status
Simulation time 41094018 ps
CPU time 1.03 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:06 PM PDT 24
Peak memory 203012 kb
Host smart-43ef5dab-2b0b-4eaa-8bb5-b80cca44de20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33251
69244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3325169244
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2307398110
Short name T396
Test name
Test status
Simulation time 8386249687 ps
CPU time 7.25 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:13 PM PDT 24
Peak memory 202944 kb
Host smart-0283365e-92d5-4e08-88fb-9aa7a48070b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23073
98110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2307398110
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3507261697
Short name T548
Test name
Test status
Simulation time 8404328150 ps
CPU time 7.34 seconds
Started Mar 12 02:58:05 PM PDT 24
Finished Mar 12 02:58:12 PM PDT 24
Peak memory 202976 kb
Host smart-7490c6ef-c590-480b-8205-d6c90db04d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35072
61697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3507261697
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.276761230
Short name T247
Test name
Test status
Simulation time 8360336145 ps
CPU time 7.34 seconds
Started Mar 12 02:58:06 PM PDT 24
Finished Mar 12 02:58:13 PM PDT 24
Peak memory 202964 kb
Host smart-865642cd-273e-4729-bf9c-be6b4db5c539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27676
1230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.276761230
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3584136519
Short name T76
Test name
Test status
Simulation time 8388121259 ps
CPU time 7.37 seconds
Started Mar 12 02:58:06 PM PDT 24
Finished Mar 12 02:58:14 PM PDT 24
Peak memory 203008 kb
Host smart-b894e8bc-97a6-431c-950b-4daa92479f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35841
36519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3584136519
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2836423628
Short name T286
Test name
Test status
Simulation time 8404121385 ps
CPU time 7.18 seconds
Started Mar 12 02:58:16 PM PDT 24
Finished Mar 12 02:58:24 PM PDT 24
Peak memory 203004 kb
Host smart-f9a22cbf-349a-4a12-ba7a-909528897c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28364
23628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2836423628
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.4160126573
Short name T624
Test name
Test status
Simulation time 8405257747 ps
CPU time 9.17 seconds
Started Mar 12 02:58:14 PM PDT 24
Finished Mar 12 02:58:23 PM PDT 24
Peak memory 202996 kb
Host smart-fb34b0ed-7bf9-4cd7-bd13-dac35abbf897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41601
26573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.4160126573
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2144958135
Short name T417
Test name
Test status
Simulation time 28990701 ps
CPU time 0.67 seconds
Started Mar 12 02:58:13 PM PDT 24
Finished Mar 12 02:58:13 PM PDT 24
Peak memory 202904 kb
Host smart-357b0e0f-fa98-4617-90b9-7124e23da90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21449
58135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2144958135
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3751037536
Short name T423
Test name
Test status
Simulation time 8410356898 ps
CPU time 8.03 seconds
Started Mar 12 02:58:11 PM PDT 24
Finished Mar 12 02:58:20 PM PDT 24
Peak memory 202976 kb
Host smart-c6ca0107-e4f9-4fa7-bb82-6c7ec141889f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37510
37536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3751037536
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.4088471275
Short name T411
Test name
Test status
Simulation time 8368273647 ps
CPU time 7.4 seconds
Started Mar 12 02:58:17 PM PDT 24
Finished Mar 12 02:58:24 PM PDT 24
Peak memory 202996 kb
Host smart-0d529258-7c5c-4276-bb7a-153c959e4ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40884
71275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.4088471275
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1643654753
Short name T414
Test name
Test status
Simulation time 8357968433 ps
CPU time 7.99 seconds
Started Mar 12 02:58:16 PM PDT 24
Finished Mar 12 02:58:24 PM PDT 24
Peak memory 202928 kb
Host smart-e076a60e-22b7-4826-aa7a-2c387ac1f692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16436
54753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1643654753
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2916837366
Short name T12
Test name
Test status
Simulation time 8475856776 ps
CPU time 8.08 seconds
Started Mar 12 02:58:03 PM PDT 24
Finished Mar 12 02:58:12 PM PDT 24
Peak memory 203016 kb
Host smart-a66078e5-48c2-4973-9ca8-0f4509e64174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29168
37366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2916837366
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1422274618
Short name T578
Test name
Test status
Simulation time 8372730614 ps
CPU time 7.21 seconds
Started Mar 12 02:58:13 PM PDT 24
Finished Mar 12 02:58:21 PM PDT 24
Peak memory 202964 kb
Host smart-eee41550-808a-4c88-8f5b-34bb563659dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14222
74618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1422274618
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1696221976
Short name T369
Test name
Test status
Simulation time 151384404 ps
CPU time 1.43 seconds
Started Mar 12 02:58:13 PM PDT 24
Finished Mar 12 02:58:15 PM PDT 24
Peak memory 202956 kb
Host smart-c593b5da-5e0c-45f0-9e16-94258d0b8031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16962
21976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1696221976
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2033397105
Short name T107
Test name
Test status
Simulation time 8372604904 ps
CPU time 7.14 seconds
Started Mar 12 02:58:14 PM PDT 24
Finished Mar 12 02:58:21 PM PDT 24
Peak memory 202964 kb
Host smart-9a3fda8c-b4ed-40cc-8066-7dee41616141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20333
97105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2033397105
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1768443498
Short name T5
Test name
Test status
Simulation time 8404658657 ps
CPU time 8.65 seconds
Started Mar 12 02:58:12 PM PDT 24
Finished Mar 12 02:58:21 PM PDT 24
Peak memory 202976 kb
Host smart-e70f710b-2bc5-4d16-b707-e2a9081bad7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17684
43498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1768443498
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1800240948
Short name T309
Test name
Test status
Simulation time 8367827836 ps
CPU time 7.5 seconds
Started Mar 12 02:58:11 PM PDT 24
Finished Mar 12 02:58:19 PM PDT 24
Peak memory 202992 kb
Host smart-8946ff50-fe76-4305-837f-fefa07c00621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18002
40948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1800240948
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.541118509
Short name T3
Test name
Test status
Simulation time 8410912947 ps
CPU time 8 seconds
Started Mar 12 02:58:13 PM PDT 24
Finished Mar 12 02:58:22 PM PDT 24
Peak memory 203008 kb
Host smart-6c85ed1a-65f3-47f0-a0fa-71c2e30f1721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54111
8509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.541118509
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1897270920
Short name T464
Test name
Test status
Simulation time 8365120458 ps
CPU time 7.32 seconds
Started Mar 12 02:58:16 PM PDT 24
Finished Mar 12 02:58:23 PM PDT 24
Peak memory 203004 kb
Host smart-f6864b12-dccd-4c4f-b9c1-378d0c113640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18972
70920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1897270920
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.289067222
Short name T392
Test name
Test status
Simulation time 8392029684 ps
CPU time 7 seconds
Started Mar 12 02:58:17 PM PDT 24
Finished Mar 12 02:58:24 PM PDT 24
Peak memory 203040 kb
Host smart-63cb19c0-bb28-4f29-8d63-848b0bc12a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28906
7222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.289067222
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1118008422
Short name T529
Test name
Test status
Simulation time 25806965 ps
CPU time 0.63 seconds
Started Mar 12 02:58:14 PM PDT 24
Finished Mar 12 02:58:15 PM PDT 24
Peak memory 202900 kb
Host smart-2a2b5cdd-0310-4054-85fb-31d94d65a2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11180
08422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1118008422
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.984348199
Short name T339
Test name
Test status
Simulation time 8421983722 ps
CPU time 7.72 seconds
Started Mar 12 02:58:13 PM PDT 24
Finished Mar 12 02:58:21 PM PDT 24
Peak memory 202916 kb
Host smart-7c9c93b8-a1c5-47fa-800c-7c94f17883c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98434
8199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.984348199
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.3391944288
Short name T33
Test name
Test status
Simulation time 8395903353 ps
CPU time 7.15 seconds
Started Mar 12 02:58:15 PM PDT 24
Finished Mar 12 02:58:23 PM PDT 24
Peak memory 203000 kb
Host smart-705dcdcf-afd1-49db-8c14-56abbb2ebc75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33919
44288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.3391944288
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2033466052
Short name T520
Test name
Test status
Simulation time 8355488751 ps
CPU time 8.95 seconds
Started Mar 12 02:58:11 PM PDT 24
Finished Mar 12 02:58:20 PM PDT 24
Peak memory 202996 kb
Host smart-70c1f2b3-1c3e-46cb-a6eb-6356794a62f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20334
66052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2033466052
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3394788875
Short name T285
Test name
Test status
Simulation time 8371335877 ps
CPU time 7.67 seconds
Started Mar 12 02:58:12 PM PDT 24
Finished Mar 12 02:58:20 PM PDT 24
Peak memory 202944 kb
Host smart-12df787b-a896-4407-91c2-c7fc16986460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33947
88875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3394788875
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1963985828
Short name T357
Test name
Test status
Simulation time 72044124 ps
CPU time 1.06 seconds
Started Mar 12 02:58:22 PM PDT 24
Finished Mar 12 02:58:23 PM PDT 24
Peak memory 202920 kb
Host smart-d8301c48-7e9e-47ee-940e-cabe2757a040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19639
85828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1963985828
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.772162515
Short name T421
Test name
Test status
Simulation time 8382873322 ps
CPU time 7.25 seconds
Started Mar 12 02:58:28 PM PDT 24
Finished Mar 12 02:58:35 PM PDT 24
Peak memory 203024 kb
Host smart-a5fb063e-8566-4978-94b8-878139c4faff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77216
2515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.772162515
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2748920528
Short name T596
Test name
Test status
Simulation time 8404686010 ps
CPU time 8.72 seconds
Started Mar 12 02:58:22 PM PDT 24
Finished Mar 12 02:58:31 PM PDT 24
Peak memory 203008 kb
Host smart-bc1e4b5d-279a-4c08-abe7-faef02a0a2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27489
20528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2748920528
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.750195851
Short name T568
Test name
Test status
Simulation time 8363086502 ps
CPU time 7.69 seconds
Started Mar 12 02:58:28 PM PDT 24
Finished Mar 12 02:58:36 PM PDT 24
Peak memory 203024 kb
Host smart-5981a051-b29b-47d6-acac-59f1b69da641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75019
5851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.750195851
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.4208015147
Short name T97
Test name
Test status
Simulation time 8456009164 ps
CPU time 7.11 seconds
Started Mar 12 02:58:21 PM PDT 24
Finished Mar 12 02:58:28 PM PDT 24
Peak memory 202980 kb
Host smart-da582b42-e668-47d8-b38d-1b63bd43cd14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42080
15147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.4208015147
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2440694730
Short name T192
Test name
Test status
Simulation time 8401946731 ps
CPU time 7.88 seconds
Started Mar 12 02:58:21 PM PDT 24
Finished Mar 12 02:58:29 PM PDT 24
Peak memory 203024 kb
Host smart-aa34ebae-9eb6-45c7-b4e8-07e0f9237b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24406
94730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2440694730
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.185059154
Short name T508
Test name
Test status
Simulation time 8405272750 ps
CPU time 10.02 seconds
Started Mar 12 02:58:23 PM PDT 24
Finished Mar 12 02:58:33 PM PDT 24
Peak memory 202976 kb
Host smart-b948c679-b4e4-4aee-be90-bbe6d8230cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
9154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.185059154
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.1308686902
Short name T329
Test name
Test status
Simulation time 33991072 ps
CPU time 0.61 seconds
Started Mar 12 02:58:19 PM PDT 24
Finished Mar 12 02:58:20 PM PDT 24
Peak memory 202908 kb
Host smart-4dbe1162-5cda-4193-ade5-ed1018f40200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13086
86902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.1308686902
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.1682427108
Short name T451
Test name
Test status
Simulation time 8399094300 ps
CPU time 7.57 seconds
Started Mar 12 02:58:21 PM PDT 24
Finished Mar 12 02:58:28 PM PDT 24
Peak memory 203020 kb
Host smart-7dcc8e99-ea01-481e-a175-d42b0666f229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16824
27108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.1682427108
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3818909096
Short name T669
Test name
Test status
Simulation time 8357668746 ps
CPU time 7.54 seconds
Started Mar 12 02:58:23 PM PDT 24
Finished Mar 12 02:58:31 PM PDT 24
Peak memory 203024 kb
Host smart-fb195b7c-3b62-4739-9b82-1e5778eaf23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38189
09096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3818909096
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1086184612
Short name T431
Test name
Test status
Simulation time 8476348121 ps
CPU time 7.95 seconds
Started Mar 12 02:58:13 PM PDT 24
Finished Mar 12 02:58:21 PM PDT 24
Peak memory 203032 kb
Host smart-99f436e1-fa16-4b29-adff-219557ca3fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
84612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1086184612
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3100343376
Short name T694
Test name
Test status
Simulation time 8366504239 ps
CPU time 9.32 seconds
Started Mar 12 02:56:46 PM PDT 24
Finished Mar 12 02:56:56 PM PDT 24
Peak memory 202976 kb
Host smart-94c6cbfe-701f-45dc-86a7-9c5ff01a6cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31003
43376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3100343376
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1242738986
Short name T165
Test name
Test status
Simulation time 101884938 ps
CPU time 1.39 seconds
Started Mar 12 02:56:48 PM PDT 24
Finished Mar 12 02:56:50 PM PDT 24
Peak memory 203096 kb
Host smart-04d8fd59-c39c-42dd-af67-8ef40ddb6fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12427
38986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1242738986
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2687347112
Short name T407
Test name
Test status
Simulation time 8429794066 ps
CPU time 8.39 seconds
Started Mar 12 02:56:48 PM PDT 24
Finished Mar 12 02:56:57 PM PDT 24
Peak memory 202968 kb
Host smart-de202e3d-f5ee-43f5-9b6f-0ff58fe93077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26873
47112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2687347112
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.871803522
Short name T531
Test name
Test status
Simulation time 8403107865 ps
CPU time 7.56 seconds
Started Mar 12 02:56:50 PM PDT 24
Finished Mar 12 02:56:58 PM PDT 24
Peak memory 203036 kb
Host smart-39469a0c-845c-427f-b671-324a9ef1879d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87180
3522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.871803522
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1196757376
Short name T305
Test name
Test status
Simulation time 8361799770 ps
CPU time 7.81 seconds
Started Mar 12 02:56:49 PM PDT 24
Finished Mar 12 02:56:57 PM PDT 24
Peak memory 202984 kb
Host smart-161afa51-2e9c-4d51-9fab-13d7833e867e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11967
57376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1196757376
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1598789589
Short name T92
Test name
Test status
Simulation time 8432004126 ps
CPU time 7.41 seconds
Started Mar 12 02:56:48 PM PDT 24
Finished Mar 12 02:56:55 PM PDT 24
Peak memory 203008 kb
Host smart-2f04fb37-a7ea-4ad3-8631-a3078e17cf56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15987
89589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1598789589
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.1899687701
Short name T607
Test name
Test status
Simulation time 8398391718 ps
CPU time 7.43 seconds
Started Mar 12 02:56:48 PM PDT 24
Finished Mar 12 02:56:56 PM PDT 24
Peak memory 202956 kb
Host smart-84ea0117-b233-472d-8dd1-d7f84254c661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18996
87701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1899687701
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3314637184
Short name T442
Test name
Test status
Simulation time 8365013679 ps
CPU time 9.13 seconds
Started Mar 12 02:56:51 PM PDT 24
Finished Mar 12 02:57:01 PM PDT 24
Peak memory 203024 kb
Host smart-1776debc-63ea-45d2-8431-0157d6cfa795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33146
37184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3314637184
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2843755502
Short name T495
Test name
Test status
Simulation time 27243171 ps
CPU time 0.65 seconds
Started Mar 12 02:56:57 PM PDT 24
Finished Mar 12 02:57:00 PM PDT 24
Peak memory 202868 kb
Host smart-e059ebf4-f309-4002-af99-ca0f6f696906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28437
55502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2843755502
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2621005452
Short name T322
Test name
Test status
Simulation time 8434719707 ps
CPU time 8.32 seconds
Started Mar 12 02:56:51 PM PDT 24
Finished Mar 12 02:57:00 PM PDT 24
Peak memory 203020 kb
Host smart-bc0b4047-5741-483e-b1c3-20021d1c5fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26210
05452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2621005452
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.19786364
Short name T236
Test name
Test status
Simulation time 8376033732 ps
CPU time 7.09 seconds
Started Mar 12 02:56:51 PM PDT 24
Finished Mar 12 02:56:58 PM PDT 24
Peak memory 203040 kb
Host smart-1b1ceb22-7f9d-4af2-98fb-8f1a389587f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19786
364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.19786364
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1216316174
Short name T59
Test name
Test status
Simulation time 157156722 ps
CPU time 1.09 seconds
Started Mar 12 02:57:02 PM PDT 24
Finished Mar 12 02:57:04 PM PDT 24
Peak memory 218584 kb
Host smart-169c56c1-7830-43a7-b836-f25f5aaca4ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1216316174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1216316174
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2979060812
Short name T630
Test name
Test status
Simulation time 8357549223 ps
CPU time 7.59 seconds
Started Mar 12 02:56:59 PM PDT 24
Finished Mar 12 02:57:07 PM PDT 24
Peak memory 202908 kb
Host smart-c071d8ba-b857-4adb-a025-3bae11cfa361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29790
60812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2979060812
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2943106595
Short name T612
Test name
Test status
Simulation time 8479897670 ps
CPU time 9.52 seconds
Started Mar 12 02:56:48 PM PDT 24
Finished Mar 12 02:56:57 PM PDT 24
Peak memory 203036 kb
Host smart-412e21a7-4dfb-4fa5-bbc5-bf7fac1fcce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29431
06595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2943106595
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2801438841
Short name T321
Test name
Test status
Simulation time 8367893832 ps
CPU time 7.78 seconds
Started Mar 12 02:58:43 PM PDT 24
Finished Mar 12 02:58:52 PM PDT 24
Peak memory 202932 kb
Host smart-2e709c05-3cc3-497c-886d-d16b2f99a378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28014
38841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2801438841
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2770763370
Short name T650
Test name
Test status
Simulation time 8391682953 ps
CPU time 7.54 seconds
Started Mar 12 02:58:25 PM PDT 24
Finished Mar 12 02:58:33 PM PDT 24
Peak memory 203012 kb
Host smart-1fe56cde-c541-4f73-a928-230952f75d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27707
63370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2770763370
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2110043564
Short name T269
Test name
Test status
Simulation time 8410537027 ps
CPU time 7.95 seconds
Started Mar 12 02:58:20 PM PDT 24
Finished Mar 12 02:58:28 PM PDT 24
Peak memory 203008 kb
Host smart-9d9c4164-90c8-4ea7-8bf5-2e5e033a4b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21100
43564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2110043564
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3471027173
Short name T493
Test name
Test status
Simulation time 8364472792 ps
CPU time 7.27 seconds
Started Mar 12 02:58:29 PM PDT 24
Finished Mar 12 02:58:36 PM PDT 24
Peak memory 203024 kb
Host smart-1207d414-9d4c-439f-be08-9c32935cf01a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34710
27173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3471027173
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2100369675
Short name T82
Test name
Test status
Simulation time 8392447428 ps
CPU time 7.97 seconds
Started Mar 12 02:58:21 PM PDT 24
Finished Mar 12 02:58:29 PM PDT 24
Peak memory 203008 kb
Host smart-06971dcb-80bd-4d85-817f-1abafa96641e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21003
69675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2100369675
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2692069287
Short name T472
Test name
Test status
Simulation time 8379027212 ps
CPU time 7.38 seconds
Started Mar 12 02:58:28 PM PDT 24
Finished Mar 12 02:58:35 PM PDT 24
Peak memory 203024 kb
Host smart-b28ee30c-a885-41d1-851e-1d402449c254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26920
69287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2692069287
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1150175978
Short name T282
Test name
Test status
Simulation time 8401019417 ps
CPU time 7.3 seconds
Started Mar 12 02:58:27 PM PDT 24
Finished Mar 12 02:58:34 PM PDT 24
Peak memory 203012 kb
Host smart-d1fdb7de-994f-4408-9f07-cd3d5dc92821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11501
75978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1150175978
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2219444678
Short name T514
Test name
Test status
Simulation time 26125457 ps
CPU time 0.63 seconds
Started Mar 12 02:58:22 PM PDT 24
Finished Mar 12 02:58:23 PM PDT 24
Peak memory 202920 kb
Host smart-eef1dc1c-c9ff-4240-b0e5-503512c67554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22194
44678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2219444678
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.2355089347
Short name T622
Test name
Test status
Simulation time 8367997446 ps
CPU time 8.07 seconds
Started Mar 12 02:58:23 PM PDT 24
Finished Mar 12 02:58:31 PM PDT 24
Peak memory 203024 kb
Host smart-932b7e7a-a666-4b66-b8b0-beaa0acbcc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23550
89347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.2355089347
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1913036234
Short name T289
Test name
Test status
Simulation time 8358089216 ps
CPU time 7.4 seconds
Started Mar 12 02:58:26 PM PDT 24
Finished Mar 12 02:58:33 PM PDT 24
Peak memory 202972 kb
Host smart-06c38de5-cf97-484d-8770-3edac02ba5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19130
36234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1913036234
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3831878920
Short name T25
Test name
Test status
Simulation time 8477548941 ps
CPU time 8.11 seconds
Started Mar 12 02:58:26 PM PDT 24
Finished Mar 12 02:58:34 PM PDT 24
Peak memory 203048 kb
Host smart-293b00ac-7415-4871-a377-b8d97ef87fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38318
78920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3831878920
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3153268506
Short name T668
Test name
Test status
Simulation time 8371130082 ps
CPU time 8.53 seconds
Started Mar 12 02:58:30 PM PDT 24
Finished Mar 12 02:58:39 PM PDT 24
Peak memory 202924 kb
Host smart-c57ab76a-92e4-4397-9164-612b8e442c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31532
68506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3153268506
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2417595935
Short name T181
Test name
Test status
Simulation time 148823469 ps
CPU time 1.72 seconds
Started Mar 12 02:58:22 PM PDT 24
Finished Mar 12 02:58:23 PM PDT 24
Peak memory 203032 kb
Host smart-9f84f6c3-9c08-4e97-b33f-5f9b46380e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24175
95935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2417595935
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2837552820
Short name T113
Test name
Test status
Simulation time 8376278857 ps
CPU time 9.3 seconds
Started Mar 12 02:58:21 PM PDT 24
Finished Mar 12 02:58:30 PM PDT 24
Peak memory 203028 kb
Host smart-5bd8d752-dd81-4b5b-b3b3-880c7849a4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28375
52820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2837552820
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.278829574
Short name T433
Test name
Test status
Simulation time 8410117383 ps
CPU time 7.51 seconds
Started Mar 12 02:58:25 PM PDT 24
Finished Mar 12 02:58:33 PM PDT 24
Peak memory 202992 kb
Host smart-0441262f-5009-4bd4-9223-cdf572ee0740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27882
9574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.278829574
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.400744751
Short name T185
Test name
Test status
Simulation time 8361869963 ps
CPU time 9.59 seconds
Started Mar 12 02:58:22 PM PDT 24
Finished Mar 12 02:58:32 PM PDT 24
Peak memory 202988 kb
Host smart-b0f967ee-2226-490d-8d3b-d7c1a91d5d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40074
4751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.400744751
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1942955395
Short name T546
Test name
Test status
Simulation time 8431161714 ps
CPU time 8.06 seconds
Started Mar 12 02:58:23 PM PDT 24
Finished Mar 12 02:58:31 PM PDT 24
Peak memory 202968 kb
Host smart-86969629-680a-416c-878a-788d6cb198bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19429
55395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1942955395
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3418606886
Short name T18
Test name
Test status
Simulation time 8374458076 ps
CPU time 7.64 seconds
Started Mar 12 02:58:27 PM PDT 24
Finished Mar 12 02:58:35 PM PDT 24
Peak memory 203012 kb
Host smart-9191ef97-c9a8-4656-9cb7-b6b67549fb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34186
06886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3418606886
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.970186214
Short name T354
Test name
Test status
Simulation time 8373338689 ps
CPU time 8.19 seconds
Started Mar 12 02:58:29 PM PDT 24
Finished Mar 12 02:58:37 PM PDT 24
Peak memory 203024 kb
Host smart-32f3abd8-2962-4461-83a9-d5e9a1d03c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97018
6214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.970186214
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3511530464
Short name T528
Test name
Test status
Simulation time 30914623 ps
CPU time 0.65 seconds
Started Mar 12 02:58:21 PM PDT 24
Finished Mar 12 02:58:21 PM PDT 24
Peak memory 202812 kb
Host smart-1d9be000-5224-4d7a-8481-0e1a78a984ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35115
30464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3511530464
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1403216111
Short name T116
Test name
Test status
Simulation time 8402081330 ps
CPU time 8.09 seconds
Started Mar 12 02:58:29 PM PDT 24
Finished Mar 12 02:58:37 PM PDT 24
Peak memory 203032 kb
Host smart-2af01b80-cb68-4b59-845b-438b6d0de528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14032
16111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1403216111
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.4157588141
Short name T498
Test name
Test status
Simulation time 8394805245 ps
CPU time 7.07 seconds
Started Mar 12 02:58:19 PM PDT 24
Finished Mar 12 02:58:27 PM PDT 24
Peak memory 203032 kb
Host smart-c494aa50-fc9d-4f68-96ca-75c81917bfb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41575
88141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.4157588141
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2656428697
Short name T491
Test name
Test status
Simulation time 8362017066 ps
CPU time 7.64 seconds
Started Mar 12 02:58:21 PM PDT 24
Finished Mar 12 02:58:29 PM PDT 24
Peak memory 202980 kb
Host smart-0d95cbd4-eb1f-4adf-a9a7-76fe0c02be56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26564
28697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2656428697
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3337912853
Short name T516
Test name
Test status
Simulation time 8480462995 ps
CPU time 7.73 seconds
Started Mar 12 02:58:21 PM PDT 24
Finished Mar 12 02:58:34 PM PDT 24
Peak memory 202972 kb
Host smart-4174ee69-53eb-46c6-9324-2a6d799fe823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33379
12853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3337912853
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.295353018
Short name T398
Test name
Test status
Simulation time 8369961158 ps
CPU time 7.52 seconds
Started Mar 12 02:58:27 PM PDT 24
Finished Mar 12 02:58:34 PM PDT 24
Peak memory 202984 kb
Host smart-d3b1f177-3a05-47c3-9c48-db7916e1ff66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29535
3018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.295353018
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1742250105
Short name T605
Test name
Test status
Simulation time 47146004 ps
CPU time 1.13 seconds
Started Mar 12 02:58:29 PM PDT 24
Finished Mar 12 02:58:30 PM PDT 24
Peak memory 203036 kb
Host smart-6f047164-3b02-40b4-8e20-7636938b0106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17422
50105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1742250105
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.24984343
Short name T240
Test name
Test status
Simulation time 8388138521 ps
CPU time 8.34 seconds
Started Mar 12 02:58:25 PM PDT 24
Finished Mar 12 02:58:34 PM PDT 24
Peak memory 202992 kb
Host smart-0e6f9793-5d28-4433-b95a-c48e2b5e7dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24984
343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.24984343
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1716391409
Short name T455
Test name
Test status
Simulation time 8405410305 ps
CPU time 7.03 seconds
Started Mar 12 02:58:18 PM PDT 24
Finished Mar 12 02:58:26 PM PDT 24
Peak memory 202984 kb
Host smart-95324a68-2a3e-40be-80a0-58d5308d3649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17163
91409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1716391409
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2920414031
Short name T397
Test name
Test status
Simulation time 8364543474 ps
CPU time 7.99 seconds
Started Mar 12 02:58:27 PM PDT 24
Finished Mar 12 02:58:35 PM PDT 24
Peak memory 203012 kb
Host smart-9c995fb5-ae59-4e63-b67b-f8ce06d2bd23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29204
14031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2920414031
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1477833935
Short name T91
Test name
Test status
Simulation time 8431207545 ps
CPU time 8.51 seconds
Started Mar 12 02:58:40 PM PDT 24
Finished Mar 12 02:58:50 PM PDT 24
Peak memory 202936 kb
Host smart-7dab3240-cd95-469f-89e9-1e98e94ec282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14778
33935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1477833935
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3735455061
Short name T603
Test name
Test status
Simulation time 8386165099 ps
CPU time 7.33 seconds
Started Mar 12 02:58:22 PM PDT 24
Finished Mar 12 02:58:29 PM PDT 24
Peak memory 202916 kb
Host smart-f8dc0dc9-0deb-46df-a777-19b87ffd9b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37354
55061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3735455061
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1220851081
Short name T224
Test name
Test status
Simulation time 8403753780 ps
CPU time 8.13 seconds
Started Mar 12 02:58:29 PM PDT 24
Finished Mar 12 02:58:37 PM PDT 24
Peak memory 203032 kb
Host smart-c50f4429-3c2d-4a85-97c2-8b0a166bc39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12208
51081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1220851081
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3734055124
Short name T330
Test name
Test status
Simulation time 30186529 ps
CPU time 0.63 seconds
Started Mar 12 02:58:35 PM PDT 24
Finished Mar 12 02:58:35 PM PDT 24
Peak memory 202916 kb
Host smart-eb3cbf13-fce0-4404-9375-79b160161304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37340
55124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3734055124
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3648358140
Short name T456
Test name
Test status
Simulation time 8458793943 ps
CPU time 8.57 seconds
Started Mar 12 02:58:20 PM PDT 24
Finished Mar 12 02:58:29 PM PDT 24
Peak memory 203036 kb
Host smart-01152a78-413b-4fe9-a1c5-1c5b72abfc1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36483
58140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3648358140
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.442982580
Short name T501
Test name
Test status
Simulation time 8388775931 ps
CPU time 7 seconds
Started Mar 12 02:58:25 PM PDT 24
Finished Mar 12 02:58:32 PM PDT 24
Peak memory 202992 kb
Host smart-4bb7f23b-f4a9-4710-8ca1-ced2fae1da88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44298
2580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.442982580
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1916693074
Short name T696
Test name
Test status
Simulation time 8361247281 ps
CPU time 7.75 seconds
Started Mar 12 02:58:22 PM PDT 24
Finished Mar 12 02:58:30 PM PDT 24
Peak memory 202988 kb
Host smart-87de49f3-6d85-4d8f-ba63-b272e36a60a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19166
93074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1916693074
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.880483821
Short name T99
Test name
Test status
Simulation time 8471622870 ps
CPU time 7.6 seconds
Started Mar 12 02:58:21 PM PDT 24
Finished Mar 12 02:58:29 PM PDT 24
Peak memory 203032 kb
Host smart-688ef1e0-8d5d-4c5d-b86e-842963d35a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88048
3821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.880483821
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1755623233
Short name T429
Test name
Test status
Simulation time 8365216072 ps
CPU time 8.66 seconds
Started Mar 12 02:58:25 PM PDT 24
Finished Mar 12 02:58:34 PM PDT 24
Peak memory 202944 kb
Host smart-98c029f9-8f0a-49d4-946b-05ef4b6e9554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17556
23233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1755623233
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1053242859
Short name T229
Test name
Test status
Simulation time 229676792 ps
CPU time 1.92 seconds
Started Mar 12 02:58:39 PM PDT 24
Finished Mar 12 02:58:42 PM PDT 24
Peak memory 203000 kb
Host smart-caf45873-bb7f-448d-ac12-d19b073ed1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10532
42859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1053242859
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.360082748
Short name T664
Test name
Test status
Simulation time 8385544705 ps
CPU time 7.95 seconds
Started Mar 12 02:58:28 PM PDT 24
Finished Mar 12 02:58:36 PM PDT 24
Peak memory 202996 kb
Host smart-e6af393d-acc5-41a3-aae1-8e0951f77bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36008
2748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.360082748
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1577439504
Short name T567
Test name
Test status
Simulation time 8411106233 ps
CPU time 7.27 seconds
Started Mar 12 02:58:22 PM PDT 24
Finished Mar 12 02:58:30 PM PDT 24
Peak memory 202964 kb
Host smart-54548fa4-89d1-4cc1-9351-c0f669d308e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15774
39504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1577439504
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2891548799
Short name T699
Test name
Test status
Simulation time 8367883528 ps
CPU time 7.92 seconds
Started Mar 12 02:58:34 PM PDT 24
Finished Mar 12 02:58:48 PM PDT 24
Peak memory 202988 kb
Host smart-d8006d7a-7642-4636-a3d3-e9ff3efba563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28915
48799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2891548799
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3055322391
Short name T77
Test name
Test status
Simulation time 8397664729 ps
CPU time 8.15 seconds
Started Mar 12 02:58:23 PM PDT 24
Finished Mar 12 02:58:32 PM PDT 24
Peak memory 202980 kb
Host smart-fdd0fad8-8e09-4ada-8c88-41802e7d2149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30553
22391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3055322391
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3764713890
Short name T565
Test name
Test status
Simulation time 8402994194 ps
CPU time 7.72 seconds
Started Mar 12 02:58:22 PM PDT 24
Finished Mar 12 02:58:30 PM PDT 24
Peak memory 202988 kb
Host smart-0d0b720d-9e39-442c-8f48-bc424966d0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37647
13890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3764713890
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2569022411
Short name T626
Test name
Test status
Simulation time 8391925193 ps
CPU time 7.18 seconds
Started Mar 12 02:58:26 PM PDT 24
Finished Mar 12 02:58:33 PM PDT 24
Peak memory 202988 kb
Host smart-62bc0f9c-9726-4922-af7d-14ea9ee2c7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25690
22411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2569022411
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1280063238
Short name T677
Test name
Test status
Simulation time 21396705 ps
CPU time 0.62 seconds
Started Mar 12 02:58:23 PM PDT 24
Finished Mar 12 02:58:24 PM PDT 24
Peak memory 202908 kb
Host smart-09932956-ad91-4a66-92f7-7b258a66e0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12800
63238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1280063238
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.1110742620
Short name T389
Test name
Test status
Simulation time 8394949249 ps
CPU time 9.63 seconds
Started Mar 12 02:58:26 PM PDT 24
Finished Mar 12 02:58:36 PM PDT 24
Peak memory 202992 kb
Host smart-0db6afe0-b8d7-4045-818b-54a64d5bb122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11107
42620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.1110742620
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.4849521
Short name T576
Test name
Test status
Simulation time 8361077364 ps
CPU time 8.68 seconds
Started Mar 12 02:58:28 PM PDT 24
Finished Mar 12 02:58:37 PM PDT 24
Peak memory 202988 kb
Host smart-b50c92ef-5d0e-44d0-9ef0-9e320fadb68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48495
21 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.4849521
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.129325195
Short name T583
Test name
Test status
Simulation time 8374743391 ps
CPU time 7.51 seconds
Started Mar 12 02:58:33 PM PDT 24
Finished Mar 12 02:58:41 PM PDT 24
Peak memory 202964 kb
Host smart-f0b36f5e-0e58-4d5c-aae0-9e63d5024a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12932
5195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.129325195
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.71667521
Short name T400
Test name
Test status
Simulation time 181675892 ps
CPU time 1.56 seconds
Started Mar 12 02:58:29 PM PDT 24
Finished Mar 12 02:58:30 PM PDT 24
Peak memory 203016 kb
Host smart-f695c296-ae08-4310-ad0a-5f671ff6d938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71667
521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.71667521
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2871276793
Short name T582
Test name
Test status
Simulation time 8452378041 ps
CPU time 7.86 seconds
Started Mar 12 02:58:51 PM PDT 24
Finished Mar 12 02:58:59 PM PDT 24
Peak memory 203040 kb
Host smart-ba0f8b4f-d5e2-48a4-8dc3-910702258b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28712
76793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2871276793
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3977941638
Short name T402
Test name
Test status
Simulation time 8402839796 ps
CPU time 8.96 seconds
Started Mar 12 02:58:28 PM PDT 24
Finished Mar 12 02:58:37 PM PDT 24
Peak memory 202996 kb
Host smart-17e14242-37e0-49ce-a7f9-74f2b2336424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39779
41638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3977941638
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2276232851
Short name T251
Test name
Test status
Simulation time 8366187182 ps
CPU time 7.76 seconds
Started Mar 12 02:58:44 PM PDT 24
Finished Mar 12 02:58:52 PM PDT 24
Peak memory 203024 kb
Host smart-9d153adb-59e0-44b4-afde-9a58ed60b3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22762
32851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2276232851
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.692420926
Short name T88
Test name
Test status
Simulation time 8434869096 ps
CPU time 7.6 seconds
Started Mar 12 02:58:28 PM PDT 24
Finished Mar 12 02:58:36 PM PDT 24
Peak memory 203024 kb
Host smart-2951bbe2-095a-41e8-b338-88f3bc9fb332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69242
0926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.692420926
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3215667141
Short name T645
Test name
Test status
Simulation time 8374073807 ps
CPU time 7.13 seconds
Started Mar 12 02:58:47 PM PDT 24
Finished Mar 12 02:58:54 PM PDT 24
Peak memory 202956 kb
Host smart-8ffa88ca-05ea-40ec-acbc-66c57f45c8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32156
67141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3215667141
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1617033444
Short name T579
Test name
Test status
Simulation time 8393154157 ps
CPU time 9.77 seconds
Started Mar 12 02:58:36 PM PDT 24
Finished Mar 12 02:58:46 PM PDT 24
Peak memory 202996 kb
Host smart-115199b2-3feb-4934-95c7-45c3192db852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16170
33444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1617033444
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3706418696
Short name T517
Test name
Test status
Simulation time 25069309 ps
CPU time 0.62 seconds
Started Mar 12 02:58:43 PM PDT 24
Finished Mar 12 02:58:45 PM PDT 24
Peak memory 202836 kb
Host smart-af4b8730-e4ff-4eef-8bab-f8a131e02971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37064
18696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3706418696
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.3428621909
Short name T299
Test name
Test status
Simulation time 8395986389 ps
CPU time 7.18 seconds
Started Mar 12 02:58:37 PM PDT 24
Finished Mar 12 02:58:44 PM PDT 24
Peak memory 202940 kb
Host smart-cd0c7c9b-1d8a-4c00-8e2b-ac50abec5275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34286
21909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.3428621909
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.4033211394
Short name T401
Test name
Test status
Simulation time 8357723892 ps
CPU time 9.25 seconds
Started Mar 12 02:58:31 PM PDT 24
Finished Mar 12 02:58:40 PM PDT 24
Peak memory 203000 kb
Host smart-bbcbc034-7303-4d31-9198-0b742fc3e5ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40332
11394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.4033211394
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3353979810
Short name T129
Test name
Test status
Simulation time 8470656243 ps
CPU time 7.73 seconds
Started Mar 12 02:58:48 PM PDT 24
Finished Mar 12 02:58:56 PM PDT 24
Peak memory 203012 kb
Host smart-05b50670-9fc4-4caa-b276-524ba395fa3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33539
79810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3353979810
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.4162820163
Short name T590
Test name
Test status
Simulation time 8369243992 ps
CPU time 9.98 seconds
Started Mar 12 02:58:34 PM PDT 24
Finished Mar 12 02:58:44 PM PDT 24
Peak memory 202952 kb
Host smart-a318e0a2-a254-44bb-811e-1e45519af1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41628
20163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.4162820163
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1950976899
Short name T560
Test name
Test status
Simulation time 47042240 ps
CPU time 1.37 seconds
Started Mar 12 02:58:28 PM PDT 24
Finished Mar 12 02:58:29 PM PDT 24
Peak memory 203000 kb
Host smart-b361b854-beab-483b-8086-d6a07450bffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19509
76899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1950976899
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1694084570
Short name T250
Test name
Test status
Simulation time 8406076788 ps
CPU time 7.34 seconds
Started Mar 12 02:58:30 PM PDT 24
Finished Mar 12 02:58:38 PM PDT 24
Peak memory 202984 kb
Host smart-c1171efb-f9ed-4485-b012-786202ff7bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16940
84570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1694084570
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1911289222
Short name T479
Test name
Test status
Simulation time 8364761126 ps
CPU time 8.59 seconds
Started Mar 12 02:58:45 PM PDT 24
Finished Mar 12 02:58:53 PM PDT 24
Peak memory 203016 kb
Host smart-d4bc06cc-2198-4db0-8de9-95b30a527fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19112
89222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1911289222
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2347932138
Short name T78
Test name
Test status
Simulation time 8446614757 ps
CPU time 8.85 seconds
Started Mar 12 02:58:32 PM PDT 24
Finished Mar 12 02:58:41 PM PDT 24
Peak memory 202960 kb
Host smart-dc7bb7aa-9a41-47be-9110-1e4856381669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23479
32138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2347932138
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1508065682
Short name T2
Test name
Test status
Simulation time 8376130447 ps
CPU time 7.42 seconds
Started Mar 12 02:58:54 PM PDT 24
Finished Mar 12 02:59:02 PM PDT 24
Peak memory 203004 kb
Host smart-09575af7-032c-404d-999a-2206999a8343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15080
65682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1508065682
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3036584615
Short name T338
Test name
Test status
Simulation time 8375362055 ps
CPU time 9.61 seconds
Started Mar 12 02:58:36 PM PDT 24
Finished Mar 12 02:58:46 PM PDT 24
Peak memory 203032 kb
Host smart-b85f8133-9c18-49ee-8f98-499dd1f39395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30365
84615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3036584615
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2727708922
Short name T323
Test name
Test status
Simulation time 21808294 ps
CPU time 0.62 seconds
Started Mar 12 02:58:43 PM PDT 24
Finished Mar 12 02:58:45 PM PDT 24
Peak memory 202916 kb
Host smart-8a046033-4181-4d99-9df2-8c95b6d173ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27277
08922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2727708922
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.4240938475
Short name T356
Test name
Test status
Simulation time 8461549587 ps
CPU time 8.25 seconds
Started Mar 12 02:58:38 PM PDT 24
Finished Mar 12 02:58:47 PM PDT 24
Peak memory 202996 kb
Host smart-4d9bd16a-1bcd-4905-9d08-29b4b8ffea2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42409
38475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.4240938475
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.1598715697
Short name T511
Test name
Test status
Simulation time 8398347895 ps
CPU time 7.58 seconds
Started Mar 12 02:58:28 PM PDT 24
Finished Mar 12 02:58:36 PM PDT 24
Peak memory 202996 kb
Host smart-5e37c164-405a-445b-ba0c-664d0664ab19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15987
15697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.1598715697
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1181470044
Short name T702
Test name
Test status
Simulation time 8360227731 ps
CPU time 7.83 seconds
Started Mar 12 02:58:30 PM PDT 24
Finished Mar 12 02:58:38 PM PDT 24
Peak memory 202984 kb
Host smart-d7df79ee-83f8-4a64-8709-845b72d09d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11814
70044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1181470044
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3671574116
Short name T378
Test name
Test status
Simulation time 8371065986 ps
CPU time 7.87 seconds
Started Mar 12 02:58:35 PM PDT 24
Finished Mar 12 02:58:43 PM PDT 24
Peak memory 203008 kb
Host smart-4262676d-4166-4d2c-920d-67c4efb3eff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36715
74116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3671574116
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2344337046
Short name T556
Test name
Test status
Simulation time 8450792378 ps
CPU time 7.94 seconds
Started Mar 12 02:58:31 PM PDT 24
Finished Mar 12 02:58:39 PM PDT 24
Peak memory 202972 kb
Host smart-55cec0e1-ab8e-4dc7-9e82-3269a2304aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23443
37046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2344337046
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1450313730
Short name T303
Test name
Test status
Simulation time 8408138611 ps
CPU time 7.19 seconds
Started Mar 12 02:58:35 PM PDT 24
Finished Mar 12 02:58:43 PM PDT 24
Peak memory 203016 kb
Host smart-999ff80c-8a31-4770-8f4f-36dfc43f59a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14503
13730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1450313730
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2636364478
Short name T638
Test name
Test status
Simulation time 8363267363 ps
CPU time 7.44 seconds
Started Mar 12 02:58:34 PM PDT 24
Finished Mar 12 02:58:41 PM PDT 24
Peak memory 203000 kb
Host smart-20051676-2b8d-493b-8251-30ab46c84f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26363
64478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2636364478
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1994016029
Short name T438
Test name
Test status
Simulation time 8362555202 ps
CPU time 7.44 seconds
Started Mar 12 02:58:33 PM PDT 24
Finished Mar 12 02:58:41 PM PDT 24
Peak memory 202972 kb
Host smart-f6938e8e-1945-408d-8e13-b3b07452e450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19940
16029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1994016029
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.197096519
Short name T276
Test name
Test status
Simulation time 8386784529 ps
CPU time 7.33 seconds
Started Mar 12 02:58:35 PM PDT 24
Finished Mar 12 02:58:43 PM PDT 24
Peak memory 202872 kb
Host smart-f21b1993-29be-474c-b853-2d82e43b1adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19709
6519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.197096519
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.357099910
Short name T492
Test name
Test status
Simulation time 23339667 ps
CPU time 0.63 seconds
Started Mar 12 02:58:36 PM PDT 24
Finished Mar 12 02:58:37 PM PDT 24
Peak memory 202936 kb
Host smart-3eb98286-3de5-4df0-a273-70946d2fa8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35709
9910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.357099910
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3954000569
Short name T118
Test name
Test status
Simulation time 8388164000 ps
CPU time 9.37 seconds
Started Mar 12 02:58:28 PM PDT 24
Finished Mar 12 02:58:38 PM PDT 24
Peak memory 203000 kb
Host smart-55f6b336-dfa7-4eef-8429-e6b057690b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39540
00569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3954000569
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.3625579470
Short name T445
Test name
Test status
Simulation time 8375870766 ps
CPU time 7.44 seconds
Started Mar 12 02:58:45 PM PDT 24
Finished Mar 12 02:58:53 PM PDT 24
Peak memory 202988 kb
Host smart-66ea6da9-9193-4d6f-be60-2bdbdc27b064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36255
79470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.3625579470
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2982618170
Short name T530
Test name
Test status
Simulation time 8360283201 ps
CPU time 7.48 seconds
Started Mar 12 02:58:45 PM PDT 24
Finished Mar 12 02:58:53 PM PDT 24
Peak memory 202936 kb
Host smart-4483e7fd-2de1-41e9-8eff-3062484c6b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29826
18170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2982618170
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3985698138
Short name T320
Test name
Test status
Simulation time 8367357054 ps
CPU time 7.64 seconds
Started Mar 12 02:58:33 PM PDT 24
Finished Mar 12 02:58:41 PM PDT 24
Peak memory 202972 kb
Host smart-3b9a459d-6b01-4c66-932b-852b2083a325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39856
98138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3985698138
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1559905814
Short name T616
Test name
Test status
Simulation time 46065679 ps
CPU time 1.3 seconds
Started Mar 12 02:58:35 PM PDT 24
Finished Mar 12 02:58:37 PM PDT 24
Peak memory 203020 kb
Host smart-9c08b2e3-23a2-4320-b7cd-e41cf2f8a631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15599
05814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1559905814
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1294114337
Short name T705
Test name
Test status
Simulation time 8457145527 ps
CPU time 7.33 seconds
Started Mar 12 02:58:35 PM PDT 24
Finished Mar 12 02:58:43 PM PDT 24
Peak memory 202824 kb
Host smart-1265f390-f501-4485-b211-f9aeb693e1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12941
14337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1294114337
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.811588811
Short name T232
Test name
Test status
Simulation time 8406725266 ps
CPU time 8.6 seconds
Started Mar 12 02:58:42 PM PDT 24
Finished Mar 12 02:58:51 PM PDT 24
Peak memory 203040 kb
Host smart-2db34ce1-33ef-4e42-ac3d-94cce39e633c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81158
8811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.811588811
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.828172719
Short name T452
Test name
Test status
Simulation time 8363204789 ps
CPU time 7.95 seconds
Started Mar 12 02:58:49 PM PDT 24
Finished Mar 12 02:58:57 PM PDT 24
Peak memory 203000 kb
Host smart-60556263-30c5-42c8-8dfe-56a6db4a2479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82817
2719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.828172719
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3321802037
Short name T667
Test name
Test status
Simulation time 8440546304 ps
CPU time 7.89 seconds
Started Mar 12 02:58:37 PM PDT 24
Finished Mar 12 02:58:46 PM PDT 24
Peak memory 203012 kb
Host smart-b94cf235-496b-478d-abd8-117de9168d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33218
02037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3321802037
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.769507539
Short name T483
Test name
Test status
Simulation time 8377733005 ps
CPU time 7.72 seconds
Started Mar 12 02:58:42 PM PDT 24
Finished Mar 12 02:58:51 PM PDT 24
Peak memory 202984 kb
Host smart-8556d397-fd9d-4c85-8374-bb417431e3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76950
7539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.769507539
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2976922001
Short name T268
Test name
Test status
Simulation time 8395794609 ps
CPU time 8.97 seconds
Started Mar 12 02:58:45 PM PDT 24
Finished Mar 12 02:58:54 PM PDT 24
Peak memory 202944 kb
Host smart-fa49210c-af8c-4739-85bb-4fb1a1976820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29769
22001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2976922001
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2559011523
Short name T459
Test name
Test status
Simulation time 27701586 ps
CPU time 0.7 seconds
Started Mar 12 02:58:40 PM PDT 24
Finished Mar 12 02:58:41 PM PDT 24
Peak memory 202940 kb
Host smart-3a1d6ee2-df3f-4987-b3e5-e41eebfd89db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25590
11523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2559011523
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1330252226
Short name T390
Test name
Test status
Simulation time 8420896304 ps
CPU time 9.39 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:12 PM PDT 24
Peak memory 203020 kb
Host smart-0cc99f09-9390-4f38-991d-bba3c5582e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13302
52226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1330252226
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.3671931804
Short name T704
Test name
Test status
Simulation time 8402865893 ps
CPU time 9.44 seconds
Started Mar 12 02:58:50 PM PDT 24
Finished Mar 12 02:59:00 PM PDT 24
Peak memory 203020 kb
Host smart-74fc7390-b0eb-4278-9d61-73bebad17e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36719
31804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.3671931804
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.3646037143
Short name T489
Test name
Test status
Simulation time 8354381285 ps
CPU time 7.25 seconds
Started Mar 12 02:58:39 PM PDT 24
Finished Mar 12 02:58:47 PM PDT 24
Peak memory 203004 kb
Host smart-06b64ec4-cdff-4387-ae0f-0c9ac5048a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36460
37143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.3646037143
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.254951488
Short name T122
Test name
Test status
Simulation time 8473378651 ps
CPU time 8.46 seconds
Started Mar 12 02:58:53 PM PDT 24
Finished Mar 12 02:59:01 PM PDT 24
Peak memory 203032 kb
Host smart-0e1d35cc-6a49-4ca1-bc4e-65b2bf270478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25495
1488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.254951488
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.4294369453
Short name T298
Test name
Test status
Simulation time 8368099901 ps
CPU time 7.47 seconds
Started Mar 12 02:58:46 PM PDT 24
Finished Mar 12 02:58:53 PM PDT 24
Peak memory 203032 kb
Host smart-16f6fadb-0b2e-4cd8-b90f-7cdfa274f0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42943
69453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.4294369453
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2490364944
Short name T191
Test name
Test status
Simulation time 177481361 ps
CPU time 1.66 seconds
Started Mar 12 02:58:43 PM PDT 24
Finished Mar 12 02:58:45 PM PDT 24
Peak memory 203076 kb
Host smart-c34592fc-8525-4014-ad67-40fa64f3ae9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24903
64944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2490364944
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1997397053
Short name T653
Test name
Test status
Simulation time 8452146299 ps
CPU time 9.8 seconds
Started Mar 12 02:58:46 PM PDT 24
Finished Mar 12 02:58:56 PM PDT 24
Peak memory 202996 kb
Host smart-f2607afd-d4f2-4765-a220-6e4db85d6620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19973
97053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1997397053
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1687140677
Short name T406
Test name
Test status
Simulation time 8406301647 ps
CPU time 7.41 seconds
Started Mar 12 02:58:40 PM PDT 24
Finished Mar 12 02:58:48 PM PDT 24
Peak memory 203024 kb
Host smart-a2b4ea52-948e-46d6-8192-6450e0b53919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16871
40677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1687140677
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1399600212
Short name T480
Test name
Test status
Simulation time 8366601112 ps
CPU time 7.44 seconds
Started Mar 12 02:58:44 PM PDT 24
Finished Mar 12 02:58:52 PM PDT 24
Peak memory 202992 kb
Host smart-5dcaa707-893c-448a-b8e7-bf8450f60e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13996
00212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1399600212
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.577403355
Short name T81
Test name
Test status
Simulation time 8422923038 ps
CPU time 7.76 seconds
Started Mar 12 02:58:46 PM PDT 24
Finished Mar 12 02:58:54 PM PDT 24
Peak memory 202860 kb
Host smart-c9a43ab9-c13c-403e-aa85-7ed6b0360bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57740
3355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.577403355
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.1664991446
Short name T255
Test name
Test status
Simulation time 8397611773 ps
CPU time 7.3 seconds
Started Mar 12 02:58:47 PM PDT 24
Finished Mar 12 02:58:55 PM PDT 24
Peak memory 203036 kb
Host smart-eb5f45ee-a511-47c6-9ad4-ca3e36ea093e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16649
91446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1664991446
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1802437415
Short name T532
Test name
Test status
Simulation time 8384626410 ps
CPU time 7.16 seconds
Started Mar 12 02:58:40 PM PDT 24
Finished Mar 12 02:58:48 PM PDT 24
Peak memory 203020 kb
Host smart-3ba84d99-2401-42a7-971d-7ea35547935d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18024
37415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1802437415
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.261902971
Short name T29
Test name
Test status
Simulation time 28213075 ps
CPU time 0.66 seconds
Started Mar 12 02:58:39 PM PDT 24
Finished Mar 12 02:58:41 PM PDT 24
Peak memory 202872 kb
Host smart-a1e22f30-1fde-42fd-acd5-8e827d52cc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26190
2971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.261902971
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2891386875
Short name T178
Test name
Test status
Simulation time 8390395759 ps
CPU time 7.21 seconds
Started Mar 12 02:58:37 PM PDT 24
Finished Mar 12 02:58:45 PM PDT 24
Peak memory 202952 kb
Host smart-b194fd4b-6cd8-497a-95a3-3ffadf4e07bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28913
86875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2891386875
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.4092280236
Short name T228
Test name
Test status
Simulation time 8368914767 ps
CPU time 7.43 seconds
Started Mar 12 02:58:55 PM PDT 24
Finished Mar 12 02:59:02 PM PDT 24
Peak memory 202988 kb
Host smart-9715bf4a-af49-49ff-9cee-5ba8490e6c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40922
80236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.4092280236
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1419514123
Short name T477
Test name
Test status
Simulation time 8357267635 ps
CPU time 7.54 seconds
Started Mar 12 02:58:54 PM PDT 24
Finished Mar 12 02:59:01 PM PDT 24
Peak memory 203020 kb
Host smart-cac40c06-dfe6-418c-bcb3-489a4e6a95d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14195
14123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1419514123
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1353158521
Short name T7
Test name
Test status
Simulation time 8473713746 ps
CPU time 7.39 seconds
Started Mar 12 02:58:39 PM PDT 24
Finished Mar 12 02:58:48 PM PDT 24
Peak memory 203052 kb
Host smart-ea14db84-62e8-4d39-ac7b-0bac5a5b4dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13531
58521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1353158521
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.4271726999
Short name T362
Test name
Test status
Simulation time 8368609616 ps
CPU time 7.32 seconds
Started Mar 12 02:58:41 PM PDT 24
Finished Mar 12 02:58:49 PM PDT 24
Peak memory 202980 kb
Host smart-fe9bf8d9-c163-4ffd-8c15-178b8cfe1c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42717
26999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.4271726999
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2475126033
Short name T632
Test name
Test status
Simulation time 142864675 ps
CPU time 1.31 seconds
Started Mar 12 02:58:50 PM PDT 24
Finished Mar 12 02:58:52 PM PDT 24
Peak memory 203040 kb
Host smart-739a87ff-2ce8-4856-b57c-91322ba25031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24751
26033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2475126033
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.428115579
Short name T262
Test name
Test status
Simulation time 8416232706 ps
CPU time 8.27 seconds
Started Mar 12 02:58:48 PM PDT 24
Finished Mar 12 02:58:56 PM PDT 24
Peak memory 203028 kb
Host smart-2f90569b-554c-4178-a2c1-dd9ae954e3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42811
5579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.428115579
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.648485091
Short name T549
Test name
Test status
Simulation time 8408909146 ps
CPU time 7.64 seconds
Started Mar 12 02:58:55 PM PDT 24
Finished Mar 12 02:59:03 PM PDT 24
Peak memory 202840 kb
Host smart-7241685e-91ec-46ac-9afc-130b251af2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64848
5091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.648485091
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.447265870
Short name T564
Test name
Test status
Simulation time 8363459127 ps
CPU time 8.35 seconds
Started Mar 12 02:58:50 PM PDT 24
Finished Mar 12 02:58:58 PM PDT 24
Peak memory 202876 kb
Host smart-9fdcb372-0816-47b8-bdda-c55f8f8c937f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44726
5870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.447265870
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3453893264
Short name T75
Test name
Test status
Simulation time 8446092280 ps
CPU time 7.79 seconds
Started Mar 12 02:58:46 PM PDT 24
Finished Mar 12 02:58:54 PM PDT 24
Peak memory 203032 kb
Host smart-53d9c412-bf40-4fe0-96a9-3850feae90ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34538
93264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3453893264
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1184749054
Short name T281
Test name
Test status
Simulation time 8380675892 ps
CPU time 7.29 seconds
Started Mar 12 02:58:43 PM PDT 24
Finished Mar 12 02:58:51 PM PDT 24
Peak memory 203008 kb
Host smart-5c94f511-ff15-4117-adfb-407a7e4cce16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11847
49054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1184749054
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.970257061
Short name T432
Test name
Test status
Simulation time 8374680666 ps
CPU time 7.39 seconds
Started Mar 12 02:58:40 PM PDT 24
Finished Mar 12 02:58:49 PM PDT 24
Peak memory 202972 kb
Host smart-f8cd09ae-f1a1-4e87-b93b-749b9752edcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97025
7061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.970257061
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1753074486
Short name T476
Test name
Test status
Simulation time 22927518 ps
CPU time 0.62 seconds
Started Mar 12 02:58:58 PM PDT 24
Finished Mar 12 02:58:58 PM PDT 24
Peak memory 202928 kb
Host smart-a98d55bd-5fce-4a49-81c1-4f3a8d24dc7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17530
74486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1753074486
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1428215211
Short name T105
Test name
Test status
Simulation time 8379737473 ps
CPU time 7.59 seconds
Started Mar 12 02:58:53 PM PDT 24
Finished Mar 12 02:59:01 PM PDT 24
Peak memory 202936 kb
Host smart-33e0eb64-c160-43a6-bf89-21ae7f9adf24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14282
15211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1428215211
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.4062749386
Short name T292
Test name
Test status
Simulation time 8381499997 ps
CPU time 8.36 seconds
Started Mar 12 02:58:53 PM PDT 24
Finished Mar 12 02:59:02 PM PDT 24
Peak memory 203032 kb
Host smart-c6cf53e9-a1ab-4f6c-92cd-a864ce30cd61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40627
49386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.4062749386
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.387161378
Short name T420
Test name
Test status
Simulation time 8354016526 ps
CPU time 9.61 seconds
Started Mar 12 02:58:54 PM PDT 24
Finished Mar 12 02:59:04 PM PDT 24
Peak memory 202980 kb
Host smart-4632107f-0f69-4287-acd1-93bc81aa5398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38716
1378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.387161378
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3061849930
Short name T231
Test name
Test status
Simulation time 8473355855 ps
CPU time 7.38 seconds
Started Mar 12 02:58:49 PM PDT 24
Finished Mar 12 02:58:56 PM PDT 24
Peak memory 202988 kb
Host smart-df1c01bb-60be-4f6e-8834-f18107009fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30618
49930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3061849930
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.746439968
Short name T344
Test name
Test status
Simulation time 8368267669 ps
CPU time 7.9 seconds
Started Mar 12 02:56:58 PM PDT 24
Finished Mar 12 02:57:07 PM PDT 24
Peak memory 202980 kb
Host smart-3333a3d8-c0e8-4915-aba7-623a20f42dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74643
9968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.746439968
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.232315535
Short name T188
Test name
Test status
Simulation time 77079367 ps
CPU time 2.16 seconds
Started Mar 12 02:57:02 PM PDT 24
Finished Mar 12 02:57:05 PM PDT 24
Peak memory 203024 kb
Host smart-fd1cd015-6737-4740-97be-c5a410f6765b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23231
5535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.232315535
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1670535137
Short name T485
Test name
Test status
Simulation time 8411674376 ps
CPU time 7.69 seconds
Started Mar 12 02:56:58 PM PDT 24
Finished Mar 12 02:57:07 PM PDT 24
Peak memory 202968 kb
Host smart-1d5c4ae4-9d7e-48af-b1ab-395cff8c6311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16705
35137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1670535137
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2218962404
Short name T625
Test name
Test status
Simulation time 8367529009 ps
CPU time 7.96 seconds
Started Mar 12 02:57:02 PM PDT 24
Finished Mar 12 02:57:10 PM PDT 24
Peak memory 203032 kb
Host smart-08a94c31-48e8-4456-9af1-1ba194e45f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22189
62404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2218962404
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2120138338
Short name T19
Test name
Test status
Simulation time 8376085353 ps
CPU time 10.08 seconds
Started Mar 12 02:56:57 PM PDT 24
Finished Mar 12 02:57:09 PM PDT 24
Peak memory 202992 kb
Host smart-6eea7b99-4f20-4988-8171-99dc70a0a448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21201
38338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2120138338
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.641349393
Short name T521
Test name
Test status
Simulation time 8375508241 ps
CPU time 9.09 seconds
Started Mar 12 02:56:59 PM PDT 24
Finished Mar 12 02:57:09 PM PDT 24
Peak memory 203040 kb
Host smart-54f75004-15e7-49ed-b278-9e506da83bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64134
9393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.641349393
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2104136689
Short name T513
Test name
Test status
Simulation time 8429473082 ps
CPU time 7.39 seconds
Started Mar 12 02:57:02 PM PDT 24
Finished Mar 12 02:57:09 PM PDT 24
Peak memory 203004 kb
Host smart-c036156f-4726-4ff6-90f1-8f94c2ef5d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21041
36689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2104136689
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.601414976
Short name T683
Test name
Test status
Simulation time 8390720415 ps
CPU time 7.33 seconds
Started Mar 12 02:56:59 PM PDT 24
Finished Mar 12 02:57:07 PM PDT 24
Peak memory 203024 kb
Host smart-34667209-e238-42a1-a745-6a5fdb05407c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60141
4976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.601414976
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2505305281
Short name T183
Test name
Test status
Simulation time 8362228447 ps
CPU time 8.09 seconds
Started Mar 12 02:56:59 PM PDT 24
Finished Mar 12 02:57:08 PM PDT 24
Peak memory 202964 kb
Host smart-ca89df0f-71f2-4ff2-aee3-85ac5032fc6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25053
05281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2505305281
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2934263757
Short name T62
Test name
Test status
Simulation time 8479143169 ps
CPU time 7.97 seconds
Started Mar 12 02:56:59 PM PDT 24
Finished Mar 12 02:57:08 PM PDT 24
Peak memory 203028 kb
Host smart-2e9adc5d-3a6c-4e47-9f06-35c2905bcc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29342
63757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2934263757
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2034174600
Short name T36
Test name
Test status
Simulation time 8364492129 ps
CPU time 8.71 seconds
Started Mar 12 02:59:00 PM PDT 24
Finished Mar 12 02:59:09 PM PDT 24
Peak memory 202916 kb
Host smart-90e8ee1c-73d2-4d4d-9935-45c58055fcd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20341
74600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2034174600
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2753186959
Short name T570
Test name
Test status
Simulation time 212664222 ps
CPU time 1.83 seconds
Started Mar 12 02:58:54 PM PDT 24
Finished Mar 12 02:58:56 PM PDT 24
Peak memory 203044 kb
Host smart-72645a64-0554-40f8-9ccc-79f2293c3ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27531
86959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2753186959
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1301819301
Short name T112
Test name
Test status
Simulation time 8430445530 ps
CPU time 9.84 seconds
Started Mar 12 02:58:56 PM PDT 24
Finished Mar 12 02:59:06 PM PDT 24
Peak memory 202940 kb
Host smart-93c3922c-de41-4278-90ef-16c23dfade6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13018
19301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1301819301
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1786751881
Short name T416
Test name
Test status
Simulation time 8403771627 ps
CPU time 7.86 seconds
Started Mar 12 02:58:52 PM PDT 24
Finished Mar 12 02:59:00 PM PDT 24
Peak memory 203016 kb
Host smart-3c2c4166-207f-42e7-bba8-b91f5a49d78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17867
51881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1786751881
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.226294418
Short name T523
Test name
Test status
Simulation time 8364915602 ps
CPU time 8.55 seconds
Started Mar 12 02:58:55 PM PDT 24
Finished Mar 12 02:59:04 PM PDT 24
Peak memory 202908 kb
Host smart-81e7bae6-5c03-4832-b166-fdc904fb7dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22629
4418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.226294418
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1719492306
Short name T94
Test name
Test status
Simulation time 8419493262 ps
CPU time 7.56 seconds
Started Mar 12 02:58:49 PM PDT 24
Finished Mar 12 02:58:57 PM PDT 24
Peak memory 202988 kb
Host smart-0b7203ec-9584-4827-a947-6cd510aeebab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17194
92306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1719492306
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3156853153
Short name T328
Test name
Test status
Simulation time 8395077569 ps
CPU time 7.43 seconds
Started Mar 12 02:58:53 PM PDT 24
Finished Mar 12 02:59:01 PM PDT 24
Peak memory 203008 kb
Host smart-9a9d8dd1-9f7a-4951-a488-43ec6b9482a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31568
53153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3156853153
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3152110495
Short name T314
Test name
Test status
Simulation time 8391730013 ps
CPU time 7.61 seconds
Started Mar 12 02:58:52 PM PDT 24
Finished Mar 12 02:59:00 PM PDT 24
Peak memory 203020 kb
Host smart-1d24c7dc-8bda-4646-a553-76c42828dbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31521
10495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3152110495
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3387654578
Short name T361
Test name
Test status
Simulation time 27588790 ps
CPU time 0.65 seconds
Started Mar 12 02:58:46 PM PDT 24
Finished Mar 12 02:58:47 PM PDT 24
Peak memory 202916 kb
Host smart-5084ab52-4ee8-49fe-94bf-4bf518b83d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33876
54578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3387654578
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.396303727
Short name T640
Test name
Test status
Simulation time 8448900784 ps
CPU time 7.8 seconds
Started Mar 12 02:58:53 PM PDT 24
Finished Mar 12 02:59:01 PM PDT 24
Peak memory 203004 kb
Host smart-a9e503cd-dbf1-4903-8257-a22635f29b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39630
3727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.396303727
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.653809389
Short name T700
Test name
Test status
Simulation time 8395710767 ps
CPU time 9.29 seconds
Started Mar 12 02:58:48 PM PDT 24
Finished Mar 12 02:58:57 PM PDT 24
Peak memory 202952 kb
Host smart-1f7d66e2-45d7-4e50-b48f-d883efd07f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65380
9389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.653809389
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.1548133169
Short name T673
Test name
Test status
Simulation time 8357808657 ps
CPU time 7.52 seconds
Started Mar 12 02:58:50 PM PDT 24
Finished Mar 12 02:58:58 PM PDT 24
Peak memory 202972 kb
Host smart-ad6466de-f18a-4cad-af0d-0883bcef13b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15481
33169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.1548133169
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1582356190
Short name T134
Test name
Test status
Simulation time 8476279747 ps
CPU time 7.64 seconds
Started Mar 12 02:58:50 PM PDT 24
Finished Mar 12 02:58:58 PM PDT 24
Peak memory 203060 kb
Host smart-7a19c4fa-3ce1-4c5a-b7ff-ef3febb6a99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15823
56190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1582356190
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2945174141
Short name T233
Test name
Test status
Simulation time 8365893069 ps
CPU time 7.97 seconds
Started Mar 12 02:58:59 PM PDT 24
Finished Mar 12 02:59:07 PM PDT 24
Peak memory 203008 kb
Host smart-d9301ef8-069b-49d7-8a04-29ba736d06a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29451
74141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2945174141
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.4110571374
Short name T169
Test name
Test status
Simulation time 113902720 ps
CPU time 1.31 seconds
Started Mar 12 02:58:47 PM PDT 24
Finished Mar 12 02:58:49 PM PDT 24
Peak memory 203032 kb
Host smart-b5717c11-bda4-4627-8d9b-5d1657f7462b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41105
71374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.4110571374
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1865938318
Short name T566
Test name
Test status
Simulation time 8425902647 ps
CPU time 7.28 seconds
Started Mar 12 02:58:53 PM PDT 24
Finished Mar 12 02:59:00 PM PDT 24
Peak memory 203016 kb
Host smart-b7f14ce0-33af-4569-9fc5-793f232d4b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18659
38318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1865938318
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2847510209
Short name T496
Test name
Test status
Simulation time 8404605642 ps
CPU time 7.26 seconds
Started Mar 12 02:58:54 PM PDT 24
Finished Mar 12 02:59:01 PM PDT 24
Peak memory 203000 kb
Host smart-e7f7c151-9c83-4257-a6c8-feed90ce2fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28475
10209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2847510209
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.501500471
Short name T652
Test name
Test status
Simulation time 8366452345 ps
CPU time 8.31 seconds
Started Mar 12 02:58:49 PM PDT 24
Finished Mar 12 02:58:58 PM PDT 24
Peak memory 203040 kb
Host smart-c17ed2bb-352d-4f16-84b5-566fff1266bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50150
0471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.501500471
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1945335628
Short name T291
Test name
Test status
Simulation time 8410339589 ps
CPU time 9.2 seconds
Started Mar 12 02:59:00 PM PDT 24
Finished Mar 12 02:59:10 PM PDT 24
Peak memory 202936 kb
Host smart-2c99486e-bab6-408b-bece-9d2558ed5a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453
35628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1945335628
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3296915507
Short name T368
Test name
Test status
Simulation time 8389479145 ps
CPU time 8.77 seconds
Started Mar 12 02:58:48 PM PDT 24
Finished Mar 12 02:58:57 PM PDT 24
Peak memory 203028 kb
Host smart-8c64879e-57f9-4c48-83d7-dcc2362c1a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32969
15507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3296915507
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.4155603104
Short name T11
Test name
Test status
Simulation time 22994359 ps
CPU time 0.66 seconds
Started Mar 12 02:58:53 PM PDT 24
Finished Mar 12 02:58:54 PM PDT 24
Peak memory 202940 kb
Host smart-9acbd139-437e-4316-8316-b52dd97b5cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41556
03104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.4155603104
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2763187214
Short name T510
Test name
Test status
Simulation time 8373253948 ps
CPU time 8.69 seconds
Started Mar 12 02:58:55 PM PDT 24
Finished Mar 12 02:59:04 PM PDT 24
Peak memory 202980 kb
Host smart-cb876bf6-e56e-4e77-8d18-e75ff38027fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27631
87214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2763187214
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.2595463292
Short name T180
Test name
Test status
Simulation time 8406346911 ps
CPU time 8.05 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:10 PM PDT 24
Peak memory 202944 kb
Host smart-92872dd9-071b-45c1-bcdc-a3d93a22e98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25954
63292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.2595463292
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.4218126351
Short name T337
Test name
Test status
Simulation time 8361543552 ps
CPU time 7.46 seconds
Started Mar 12 02:58:48 PM PDT 24
Finished Mar 12 02:58:55 PM PDT 24
Peak memory 203016 kb
Host smart-bf8b59ef-dd9a-4495-add4-222740dd0052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42181
26351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.4218126351
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2787048914
Short name T35
Test name
Test status
Simulation time 8473102565 ps
CPU time 7.94 seconds
Started Mar 12 02:58:46 PM PDT 24
Finished Mar 12 02:58:54 PM PDT 24
Peak memory 203024 kb
Host smart-a51e476a-eec6-4dcd-b462-e5479562b400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27870
48914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2787048914
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1743883140
Short name T259
Test name
Test status
Simulation time 8368791239 ps
CPU time 8.09 seconds
Started Mar 12 02:58:47 PM PDT 24
Finished Mar 12 02:58:55 PM PDT 24
Peak memory 203000 kb
Host smart-19019229-2b13-4668-8b1a-f62e070a342d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17438
83140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1743883140
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.1444158
Short name T478
Test name
Test status
Simulation time 8388848452 ps
CPU time 8.26 seconds
Started Mar 12 02:58:55 PM PDT 24
Finished Mar 12 02:59:03 PM PDT 24
Peak memory 202944 kb
Host smart-b2d4887e-9d24-4ad1-b934-5f9d051eb363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14441
58 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.1444158
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.171494055
Short name T379
Test name
Test status
Simulation time 8408407624 ps
CPU time 7.46 seconds
Started Mar 12 02:58:55 PM PDT 24
Finished Mar 12 02:59:03 PM PDT 24
Peak memory 203000 kb
Host smart-810fe7a4-05b1-4b4a-8281-915f478a03c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17149
4055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.171494055
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.589917325
Short name T194
Test name
Test status
Simulation time 8360320696 ps
CPU time 7.75 seconds
Started Mar 12 02:58:52 PM PDT 24
Finished Mar 12 02:59:00 PM PDT 24
Peak memory 203008 kb
Host smart-fd0da6da-93ba-468e-b751-8a026cb92f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58991
7325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.589917325
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.582804779
Short name T586
Test name
Test status
Simulation time 8448174343 ps
CPU time 8.17 seconds
Started Mar 12 02:58:55 PM PDT 24
Finished Mar 12 02:59:04 PM PDT 24
Peak memory 203028 kb
Host smart-fe2ee2d5-3317-4376-8c58-f2d942dfa797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58280
4779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.582804779
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3004971307
Short name T176
Test name
Test status
Simulation time 8382537130 ps
CPU time 7.52 seconds
Started Mar 12 02:58:58 PM PDT 24
Finished Mar 12 02:59:05 PM PDT 24
Peak memory 202956 kb
Host smart-6025d692-2281-4f98-8f28-b82e05678b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30049
71307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3004971307
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.4180243158
Short name T534
Test name
Test status
Simulation time 8379254870 ps
CPU time 7.65 seconds
Started Mar 12 02:59:00 PM PDT 24
Finished Mar 12 02:59:08 PM PDT 24
Peak memory 202884 kb
Host smart-cfe961e8-c3f8-4b3a-b9b9-a343882589ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41802
43158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.4180243158
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.4003312903
Short name T23
Test name
Test status
Simulation time 26221789 ps
CPU time 0.66 seconds
Started Mar 12 02:58:56 PM PDT 24
Finished Mar 12 02:58:57 PM PDT 24
Peak memory 202908 kb
Host smart-6fa8d377-86a1-47b8-bf48-5cd1691f1f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033
12903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.4003312903
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3933534747
Short name T179
Test name
Test status
Simulation time 8400660106 ps
CPU time 8.59 seconds
Started Mar 12 02:58:52 PM PDT 24
Finished Mar 12 02:59:01 PM PDT 24
Peak memory 202968 kb
Host smart-b220db38-a64f-4045-8a4c-5eab8111b4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39335
34747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3933534747
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.724901439
Short name T434
Test name
Test status
Simulation time 8375145404 ps
CPU time 8.4 seconds
Started Mar 12 02:58:55 PM PDT 24
Finished Mar 12 02:59:03 PM PDT 24
Peak memory 203028 kb
Host smart-c17ff59b-83c0-425b-8121-6f0abec7088d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72490
1439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.724901439
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1061714142
Short name T14
Test name
Test status
Simulation time 8364055360 ps
CPU time 7.21 seconds
Started Mar 12 02:58:59 PM PDT 24
Finished Mar 12 02:59:06 PM PDT 24
Peak memory 202936 kb
Host smart-40bba978-1f38-481b-bc1f-f95ff6fae162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10617
14142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1061714142
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1358923749
Short name T693
Test name
Test status
Simulation time 8478471447 ps
CPU time 8.07 seconds
Started Mar 12 02:58:58 PM PDT 24
Finished Mar 12 02:59:06 PM PDT 24
Peak memory 203016 kb
Host smart-448e406a-b233-49cc-8746-b239ca1af05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13589
23749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1358923749
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3030606957
Short name T393
Test name
Test status
Simulation time 8371275590 ps
CPU time 7.42 seconds
Started Mar 12 02:58:52 PM PDT 24
Finished Mar 12 02:59:00 PM PDT 24
Peak memory 202988 kb
Host smart-80942fa9-e9b6-448a-838d-a933a77a012a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30306
06957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3030606957
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.4116301253
Short name T182
Test name
Test status
Simulation time 216532533 ps
CPU time 1.89 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:04 PM PDT 24
Peak memory 203056 kb
Host smart-7faef588-fdd4-43ad-bfa7-1251f9ea650e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41163
01253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.4116301253
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.400682247
Short name T410
Test name
Test status
Simulation time 8419312837 ps
CPU time 8.17 seconds
Started Mar 12 02:58:52 PM PDT 24
Finished Mar 12 02:59:01 PM PDT 24
Peak memory 202956 kb
Host smart-b164608a-73fb-4436-adc8-c296aa521771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40068
2247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.400682247
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.345897012
Short name T428
Test name
Test status
Simulation time 8405640476 ps
CPU time 7.49 seconds
Started Mar 12 02:58:59 PM PDT 24
Finished Mar 12 02:59:06 PM PDT 24
Peak memory 203036 kb
Host smart-4811f3fb-3bdf-43fe-8ccc-9253dddc232a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34589
7012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.345897012
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2848452349
Short name T168
Test name
Test status
Simulation time 8363441348 ps
CPU time 7.24 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:09 PM PDT 24
Peak memory 203016 kb
Host smart-13419245-034c-496b-b76a-abf39bf62c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28484
52349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2848452349
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2498283381
Short name T706
Test name
Test status
Simulation time 8394672407 ps
CPU time 8.51 seconds
Started Mar 12 02:59:10 PM PDT 24
Finished Mar 12 02:59:21 PM PDT 24
Peak memory 202868 kb
Host smart-7d5c8c28-ede2-49a2-9049-fa33d862c75c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24982
83381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2498283381
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1519810608
Short name T422
Test name
Test status
Simulation time 8399565876 ps
CPU time 9.43 seconds
Started Mar 12 02:59:01 PM PDT 24
Finished Mar 12 02:59:10 PM PDT 24
Peak memory 203036 kb
Host smart-83050b4d-9d5d-4743-b251-8f6abda5327e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15198
10608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1519810608
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.611944388
Short name T348
Test name
Test status
Simulation time 8362739366 ps
CPU time 9.28 seconds
Started Mar 12 02:59:03 PM PDT 24
Finished Mar 12 02:59:12 PM PDT 24
Peak memory 203008 kb
Host smart-8225a2ac-80d0-4faa-a568-1e7fe03d94b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61194
4388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.611944388
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.637097809
Short name T541
Test name
Test status
Simulation time 31047089 ps
CPU time 0.64 seconds
Started Mar 12 02:58:58 PM PDT 24
Finished Mar 12 02:58:59 PM PDT 24
Peak memory 202956 kb
Host smart-31b55f5b-080b-4756-b1f7-b0f0b05ae004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63709
7809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.637097809
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.115402700
Short name T20
Test name
Test status
Simulation time 8406166508 ps
CPU time 7.64 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:10 PM PDT 24
Peak memory 203024 kb
Host smart-2a86c91e-558e-4243-95ac-254825dfff33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11540
2700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.115402700
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.3315170249
Short name T307
Test name
Test status
Simulation time 8390262422 ps
CPU time 7.58 seconds
Started Mar 12 02:59:04 PM PDT 24
Finished Mar 12 02:59:12 PM PDT 24
Peak memory 202928 kb
Host smart-0a241513-853c-4a6b-aab1-5615255a0d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33151
70249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.3315170249
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3497961674
Short name T319
Test name
Test status
Simulation time 8362579145 ps
CPU time 7.59 seconds
Started Mar 12 02:58:55 PM PDT 24
Finished Mar 12 02:59:03 PM PDT 24
Peak memory 202968 kb
Host smart-db079c5f-8690-4ca5-beba-4a896e14e558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34979
61674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3497961674
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3533301778
Short name T104
Test name
Test status
Simulation time 8473626069 ps
CPU time 7.72 seconds
Started Mar 12 02:58:52 PM PDT 24
Finished Mar 12 02:59:00 PM PDT 24
Peak memory 203052 kb
Host smart-3e7eeb7e-eba5-4d06-9b44-2966d61bc81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35333
01778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3533301778
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3324479248
Short name T318
Test name
Test status
Simulation time 8374945534 ps
CPU time 7.89 seconds
Started Mar 12 02:58:53 PM PDT 24
Finished Mar 12 02:59:02 PM PDT 24
Peak memory 202980 kb
Host smart-3373226f-1068-46bf-b9db-1615042dfa06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33244
79248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3324479248
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1886571648
Short name T39
Test name
Test status
Simulation time 163778488 ps
CPU time 1.96 seconds
Started Mar 12 02:58:59 PM PDT 24
Finished Mar 12 02:59:01 PM PDT 24
Peak memory 202996 kb
Host smart-cfdadc95-f2d9-4bc8-b80f-05446606c49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18865
71648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1886571648
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2831562803
Short name T121
Test name
Test status
Simulation time 8420919134 ps
CPU time 9.45 seconds
Started Mar 12 02:59:09 PM PDT 24
Finished Mar 12 02:59:20 PM PDT 24
Peak memory 203032 kb
Host smart-ba5910d2-03fd-4c08-8872-9d8e93827eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28315
62803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2831562803
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1507143585
Short name T274
Test name
Test status
Simulation time 8411089106 ps
CPU time 7.34 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:09 PM PDT 24
Peak memory 202924 kb
Host smart-431c4a5d-0299-40be-bd6e-cab34dba1fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15071
43585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1507143585
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.332157539
Short name T60
Test name
Test status
Simulation time 8366946532 ps
CPU time 9.43 seconds
Started Mar 12 02:58:59 PM PDT 24
Finished Mar 12 02:59:08 PM PDT 24
Peak memory 203008 kb
Host smart-30044512-e957-43c8-9cfb-1f62528a2386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33215
7539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.332157539
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1941432748
Short name T98
Test name
Test status
Simulation time 8407192937 ps
CPU time 7.64 seconds
Started Mar 12 02:58:54 PM PDT 24
Finished Mar 12 02:59:01 PM PDT 24
Peak memory 203024 kb
Host smart-68ba0605-a4a4-49b9-aef4-4800e3853b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19414
32748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1941432748
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3733966924
Short name T334
Test name
Test status
Simulation time 8400387934 ps
CPU time 7.47 seconds
Started Mar 12 02:58:52 PM PDT 24
Finished Mar 12 02:59:00 PM PDT 24
Peak memory 202892 kb
Host smart-f050ee4d-6c8f-4977-89c7-d0f245ca9987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37339
66924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3733966924
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3068327134
Short name T588
Test name
Test status
Simulation time 8382984761 ps
CPU time 8.3 seconds
Started Mar 12 02:58:57 PM PDT 24
Finished Mar 12 02:59:05 PM PDT 24
Peak memory 203036 kb
Host smart-fab70d56-b98f-4f80-933f-31102a41cacf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30683
27134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3068327134
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3004532986
Short name T351
Test name
Test status
Simulation time 27946528 ps
CPU time 0.65 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:03 PM PDT 24
Peak memory 202864 kb
Host smart-651ce396-8a3c-4862-9fee-72a15fa8ff5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30045
32986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3004532986
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2195650478
Short name T284
Test name
Test status
Simulation time 8399255191 ps
CPU time 9.24 seconds
Started Mar 12 02:58:52 PM PDT 24
Finished Mar 12 02:59:02 PM PDT 24
Peak memory 202952 kb
Host smart-c3c29bd4-a380-4d69-95a6-02e651865a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21956
50478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2195650478
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.63561000
Short name T633
Test name
Test status
Simulation time 8376171430 ps
CPU time 7.59 seconds
Started Mar 12 02:59:11 PM PDT 24
Finished Mar 12 02:59:21 PM PDT 24
Peak memory 203000 kb
Host smart-33bff355-b248-444a-aded-eb926ec5de5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63561
000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.63561000
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3797464922
Short name T412
Test name
Test status
Simulation time 8358564349 ps
CPU time 7.36 seconds
Started Mar 12 02:58:56 PM PDT 24
Finished Mar 12 02:59:04 PM PDT 24
Peak memory 202964 kb
Host smart-164ffd0d-1eea-4e10-b9cf-c7cccfae04cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37974
64922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3797464922
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3390030888
Short name T125
Test name
Test status
Simulation time 8474842740 ps
CPU time 7.96 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:10 PM PDT 24
Peak memory 203048 kb
Host smart-bb0ec384-e553-4d44-b111-a41b699a7aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33900
30888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3390030888
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.274409752
Short name T600
Test name
Test status
Simulation time 8368832844 ps
CPU time 9.81 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:13 PM PDT 24
Peak memory 202916 kb
Host smart-48cdfeff-8ed4-43cd-8162-7fcec92bd67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27440
9752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.274409752
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3574949778
Short name T193
Test name
Test status
Simulation time 58173232 ps
CPU time 1.68 seconds
Started Mar 12 02:58:54 PM PDT 24
Finished Mar 12 02:58:56 PM PDT 24
Peak memory 202996 kb
Host smart-06a29f50-8951-4b41-8aec-638ae87a3fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35749
49778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3574949778
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3206574962
Short name T474
Test name
Test status
Simulation time 8454237438 ps
CPU time 7.55 seconds
Started Mar 12 02:59:01 PM PDT 24
Finished Mar 12 02:59:08 PM PDT 24
Peak memory 202936 kb
Host smart-f47acb47-dc0a-4f94-baca-f30c2d3c0158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32065
74962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3206574962
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.4115925660
Short name T283
Test name
Test status
Simulation time 8403148806 ps
CPU time 8.81 seconds
Started Mar 12 02:59:01 PM PDT 24
Finished Mar 12 02:59:10 PM PDT 24
Peak memory 202932 kb
Host smart-8c34b1d9-a20b-4cf1-898f-e94a49f2ce12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41159
25660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.4115925660
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1197895608
Short name T308
Test name
Test status
Simulation time 8368103847 ps
CPU time 9.1 seconds
Started Mar 12 02:58:57 PM PDT 24
Finished Mar 12 02:59:07 PM PDT 24
Peak memory 202852 kb
Host smart-707828dd-a0de-4abc-95a7-ee1d7a313510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11978
95608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1197895608
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.877787563
Short name T93
Test name
Test status
Simulation time 8430340831 ps
CPU time 7.82 seconds
Started Mar 12 02:58:58 PM PDT 24
Finished Mar 12 02:59:06 PM PDT 24
Peak memory 202924 kb
Host smart-9baf42e8-48e9-4140-817f-cab3c4f2f847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87778
7563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.877787563
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.309901754
Short name T373
Test name
Test status
Simulation time 8384121895 ps
CPU time 7.39 seconds
Started Mar 12 02:59:04 PM PDT 24
Finished Mar 12 02:59:11 PM PDT 24
Peak memory 203000 kb
Host smart-42757505-5da2-4009-bad7-5455bfce3082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30990
1754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.309901754
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1664015518
Short name T360
Test name
Test status
Simulation time 8375810718 ps
CPU time 8.64 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:10 PM PDT 24
Peak memory 203004 kb
Host smart-78217483-bef5-4df4-ace5-709a527ff5af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16640
15518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1664015518
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1312343020
Short name T679
Test name
Test status
Simulation time 27437275 ps
CPU time 0.68 seconds
Started Mar 12 02:59:01 PM PDT 24
Finished Mar 12 02:59:02 PM PDT 24
Peak memory 202936 kb
Host smart-8e31d071-e1b4-42f5-8948-9fc1bc43da7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13123
43020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1312343020
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1171059511
Short name T614
Test name
Test status
Simulation time 8433742108 ps
CPU time 8.84 seconds
Started Mar 12 02:59:01 PM PDT 24
Finished Mar 12 02:59:10 PM PDT 24
Peak memory 202920 kb
Host smart-3b90a239-e2e0-4e3a-b4e0-ea1c8f8f1ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11710
59511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1171059511
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.1585265256
Short name T9
Test name
Test status
Simulation time 8398186778 ps
CPU time 7.42 seconds
Started Mar 12 02:59:01 PM PDT 24
Finished Mar 12 02:59:08 PM PDT 24
Peak memory 202860 kb
Host smart-9a9f9e9f-a08a-420f-b94d-655c362591c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15852
65256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.1585265256
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.4185573278
Short name T518
Test name
Test status
Simulation time 8355072550 ps
CPU time 7.74 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:10 PM PDT 24
Peak memory 203016 kb
Host smart-ae800420-f0a7-4897-a6ef-37d27460936f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41855
73278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.4185573278
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1801202026
Short name T189
Test name
Test status
Simulation time 8370900864 ps
CPU time 7.6 seconds
Started Mar 12 02:59:04 PM PDT 24
Finished Mar 12 02:59:12 PM PDT 24
Peak memory 202960 kb
Host smart-e65143db-d97a-4d17-a676-ae796d3342e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18012
02026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1801202026
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.580363868
Short name T481
Test name
Test status
Simulation time 149782912 ps
CPU time 1.8 seconds
Started Mar 12 02:59:07 PM PDT 24
Finished Mar 12 02:59:11 PM PDT 24
Peak memory 203012 kb
Host smart-1402f08f-eea8-48a5-8018-c4c6710fb66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58036
3868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.580363868
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3847600215
Short name T536
Test name
Test status
Simulation time 8384630985 ps
CPU time 8.37 seconds
Started Mar 12 02:59:04 PM PDT 24
Finished Mar 12 02:59:14 PM PDT 24
Peak memory 202932 kb
Host smart-aafed5c6-0032-49f5-8b3a-e95e767633b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38476
00215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3847600215
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1961617787
Short name T430
Test name
Test status
Simulation time 8411419479 ps
CPU time 7.64 seconds
Started Mar 12 02:59:07 PM PDT 24
Finished Mar 12 02:59:16 PM PDT 24
Peak memory 203012 kb
Host smart-a00cf879-afda-4a18-9229-fa6f513b322b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19616
17787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1961617787
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3864552638
Short name T617
Test name
Test status
Simulation time 8361089866 ps
CPU time 7.66 seconds
Started Mar 12 02:59:08 PM PDT 24
Finished Mar 12 02:59:17 PM PDT 24
Peak memory 202976 kb
Host smart-7624c47e-cccf-4d12-83ef-fd87e5fc4547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38645
52638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3864552638
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.34814023
Short name T545
Test name
Test status
Simulation time 8400262707 ps
CPU time 7.26 seconds
Started Mar 12 02:59:05 PM PDT 24
Finished Mar 12 02:59:13 PM PDT 24
Peak memory 202956 kb
Host smart-be576404-d3fb-4304-9896-903762e2e131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34814
023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.34814023
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2011411389
Short name T355
Test name
Test status
Simulation time 8396114631 ps
CPU time 7.43 seconds
Started Mar 12 02:59:08 PM PDT 24
Finished Mar 12 02:59:17 PM PDT 24
Peak memory 203008 kb
Host smart-9a29303e-c425-4aa3-b4a9-ddceedbc813b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20114
11389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2011411389
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.760297041
Short name T569
Test name
Test status
Simulation time 30295996 ps
CPU time 0.66 seconds
Started Mar 12 02:59:01 PM PDT 24
Finished Mar 12 02:59:02 PM PDT 24
Peak memory 202952 kb
Host smart-eb19c330-6117-4128-8b69-16c248c8fc51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76029
7041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.760297041
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3598290924
Short name T391
Test name
Test status
Simulation time 8414235414 ps
CPU time 7.43 seconds
Started Mar 12 02:59:04 PM PDT 24
Finished Mar 12 02:59:11 PM PDT 24
Peak memory 202944 kb
Host smart-795a2d33-bf6c-4a73-a5ac-07b971631285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35982
90924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3598290924
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3354816696
Short name T261
Test name
Test status
Simulation time 8374557466 ps
CPU time 7.37 seconds
Started Mar 12 02:59:03 PM PDT 24
Finished Mar 12 02:59:11 PM PDT 24
Peak memory 202948 kb
Host smart-a87aa955-2972-4338-a689-12df04dbfa12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33548
16696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3354816696
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3152388818
Short name T381
Test name
Test status
Simulation time 8361206868 ps
CPU time 7.13 seconds
Started Mar 12 02:59:08 PM PDT 24
Finished Mar 12 02:59:16 PM PDT 24
Peak memory 203024 kb
Host smart-405e5c91-3f10-4b79-ad88-b5957c23b5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31523
88818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3152388818
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2091907995
Short name T526
Test name
Test status
Simulation time 8372079926 ps
CPU time 9.03 seconds
Started Mar 12 02:59:00 PM PDT 24
Finished Mar 12 02:59:09 PM PDT 24
Peak memory 202980 kb
Host smart-ef86745c-a408-4bb8-afe1-ec01470d0964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20919
07995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2091907995
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3520858889
Short name T502
Test name
Test status
Simulation time 308200817 ps
CPU time 2.37 seconds
Started Mar 12 02:59:03 PM PDT 24
Finished Mar 12 02:59:05 PM PDT 24
Peak memory 202892 kb
Host smart-a874ed3e-27ed-45b7-a338-774489e63cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35208
58889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3520858889
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1948821289
Short name T446
Test name
Test status
Simulation time 8439123830 ps
CPU time 7.58 seconds
Started Mar 12 02:59:06 PM PDT 24
Finished Mar 12 02:59:14 PM PDT 24
Peak memory 203004 kb
Host smart-f5fe6554-1afc-4713-a252-f993de3fb42b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19488
21289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1948821289
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.703490825
Short name T277
Test name
Test status
Simulation time 8403982856 ps
CPU time 7.86 seconds
Started Mar 12 02:59:06 PM PDT 24
Finished Mar 12 02:59:15 PM PDT 24
Peak memory 202736 kb
Host smart-8946618d-0278-43c1-ab25-b56f18afe968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70349
0825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.703490825
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2675818893
Short name T688
Test name
Test status
Simulation time 8364245896 ps
CPU time 7.07 seconds
Started Mar 12 02:59:07 PM PDT 24
Finished Mar 12 02:59:15 PM PDT 24
Peak memory 203056 kb
Host smart-4be896e6-394b-487f-b054-dbc96487dba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26758
18893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2675818893
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.698060301
Short name T409
Test name
Test status
Simulation time 8378102852 ps
CPU time 7.77 seconds
Started Mar 12 02:59:04 PM PDT 24
Finished Mar 12 02:59:12 PM PDT 24
Peak memory 202984 kb
Host smart-8608624c-98fd-4320-8ada-b360ac77474a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69806
0301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.698060301
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1544585071
Short name T394
Test name
Test status
Simulation time 8370593148 ps
CPU time 7.78 seconds
Started Mar 12 02:59:02 PM PDT 24
Finished Mar 12 02:59:09 PM PDT 24
Peak memory 203016 kb
Host smart-d3982389-36ff-4f22-afe1-30393d749ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15445
85071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1544585071
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2677640940
Short name T190
Test name
Test status
Simulation time 26241916 ps
CPU time 0.66 seconds
Started Mar 12 02:59:13 PM PDT 24
Finished Mar 12 02:59:15 PM PDT 24
Peak memory 202932 kb
Host smart-9421fadc-1f24-4d94-b7da-85d76f2c4ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26776
40940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2677640940
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3617070913
Short name T300
Test name
Test status
Simulation time 8384532285 ps
CPU time 7.7 seconds
Started Mar 12 02:59:04 PM PDT 24
Finished Mar 12 02:59:12 PM PDT 24
Peak memory 202996 kb
Host smart-fae13009-aa3f-4889-a67d-0a2f7a1f0693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36170
70913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3617070913
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.3767159047
Short name T527
Test name
Test status
Simulation time 8384187606 ps
CPU time 8.73 seconds
Started Mar 12 02:59:03 PM PDT 24
Finished Mar 12 02:59:12 PM PDT 24
Peak memory 203008 kb
Host smart-2b976003-9b1f-4202-8d06-17c0709c11d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37671
59047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.3767159047
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2619678027
Short name T639
Test name
Test status
Simulation time 8360399450 ps
CPU time 7.6 seconds
Started Mar 12 02:59:04 PM PDT 24
Finished Mar 12 02:59:12 PM PDT 24
Peak memory 202964 kb
Host smart-9538a875-1a0f-4a5f-9736-578421aa1441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26196
78027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2619678027
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.723305927
Short name T133
Test name
Test status
Simulation time 8474763975 ps
CPU time 8.21 seconds
Started Mar 12 02:59:06 PM PDT 24
Finished Mar 12 02:59:15 PM PDT 24
Peak memory 203060 kb
Host smart-535c7f7b-3343-40f0-867a-72af7632a724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72330
5927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.723305927
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.977700078
Short name T543
Test name
Test status
Simulation time 8371885153 ps
CPU time 7.62 seconds
Started Mar 12 02:59:14 PM PDT 24
Finished Mar 12 02:59:22 PM PDT 24
Peak memory 203040 kb
Host smart-6c856267-913c-415e-8514-33cff07f2636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97770
0078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.977700078
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2080813414
Short name T465
Test name
Test status
Simulation time 59656994 ps
CPU time 1.51 seconds
Started Mar 12 02:59:15 PM PDT 24
Finished Mar 12 02:59:17 PM PDT 24
Peak memory 203092 kb
Host smart-d6ed2406-73d7-4afb-84d2-c9a35c48e7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20808
13414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2080813414
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3907458498
Short name T21
Test name
Test status
Simulation time 8433825456 ps
CPU time 7.35 seconds
Started Mar 12 02:59:13 PM PDT 24
Finished Mar 12 02:59:21 PM PDT 24
Peak memory 203004 kb
Host smart-a3e3b478-0ff8-4c30-9be8-2dee51b4a779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39074
58498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3907458498
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2467934914
Short name T249
Test name
Test status
Simulation time 8403480386 ps
CPU time 7.55 seconds
Started Mar 12 02:59:15 PM PDT 24
Finished Mar 12 02:59:24 PM PDT 24
Peak memory 203016 kb
Host smart-87d0f614-70a5-4534-8f7e-713bc974fb5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24679
34914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2467934914
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1043848279
Short name T654
Test name
Test status
Simulation time 8362068558 ps
CPU time 8.22 seconds
Started Mar 12 02:59:15 PM PDT 24
Finished Mar 12 02:59:25 PM PDT 24
Peak memory 202992 kb
Host smart-f09f8d77-34ca-4cbb-a2ff-7e703e0267d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10438
48279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1043848279
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2277356833
Short name T85
Test name
Test status
Simulation time 8428220887 ps
CPU time 8.75 seconds
Started Mar 12 02:59:19 PM PDT 24
Finished Mar 12 02:59:28 PM PDT 24
Peak memory 202948 kb
Host smart-c06c29fe-b815-46c1-93b3-7474e32789df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22773
56833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2277356833
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3668036866
Short name T311
Test name
Test status
Simulation time 8367147207 ps
CPU time 7.25 seconds
Started Mar 12 02:59:10 PM PDT 24
Finished Mar 12 02:59:18 PM PDT 24
Peak memory 203012 kb
Host smart-ed1dc1db-8061-4823-8fb6-9654583a1273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36680
36866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3668036866
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.4209631418
Short name T341
Test name
Test status
Simulation time 8380513438 ps
CPU time 8.76 seconds
Started Mar 12 02:59:11 PM PDT 24
Finished Mar 12 02:59:22 PM PDT 24
Peak memory 202908 kb
Host smart-0b95004a-e36b-46a7-bbf5-af3b6a08336f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42096
31418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.4209631418
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.603982881
Short name T657
Test name
Test status
Simulation time 29453680 ps
CPU time 0.64 seconds
Started Mar 12 02:59:12 PM PDT 24
Finished Mar 12 02:59:14 PM PDT 24
Peak memory 202944 kb
Host smart-e2b4e046-ac80-4f47-b48b-2b0a12434c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60398
2881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.603982881
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1438884163
Short name T647
Test name
Test status
Simulation time 8398451180 ps
CPU time 7.46 seconds
Started Mar 12 02:59:11 PM PDT 24
Finished Mar 12 02:59:21 PM PDT 24
Peak memory 203032 kb
Host smart-6ddb4165-0a19-46e3-b173-7c8fc95dc35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14388
84163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1438884163
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.2388033546
Short name T254
Test name
Test status
Simulation time 8398517307 ps
CPU time 7.38 seconds
Started Mar 12 02:59:09 PM PDT 24
Finished Mar 12 02:59:18 PM PDT 24
Peak memory 203028 kb
Host smart-1651720d-7be8-419d-a2ba-36e3aaeec4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23880
33546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.2388033546
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2040773113
Short name T454
Test name
Test status
Simulation time 8363363118 ps
CPU time 7.29 seconds
Started Mar 12 02:59:13 PM PDT 24
Finished Mar 12 02:59:21 PM PDT 24
Peak memory 202992 kb
Host smart-e2fc08e5-b153-4af8-a985-b3a96d702326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20407
73113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2040773113
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.472174248
Short name T386
Test name
Test status
Simulation time 8480009761 ps
CPU time 9.69 seconds
Started Mar 12 02:59:11 PM PDT 24
Finished Mar 12 02:59:23 PM PDT 24
Peak memory 203048 kb
Host smart-980447b7-cf04-4858-b0df-a89acdcac014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47217
4248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.472174248
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3116504718
Short name T537
Test name
Test status
Simulation time 8373379981 ps
CPU time 7.58 seconds
Started Mar 12 02:59:11 PM PDT 24
Finished Mar 12 02:59:21 PM PDT 24
Peak memory 203000 kb
Host smart-c23c5fb1-ea93-4e15-b330-c644f95bdb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
04718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3116504718
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2340888098
Short name T553
Test name
Test status
Simulation time 67635278 ps
CPU time 2.04 seconds
Started Mar 12 02:59:13 PM PDT 24
Finished Mar 12 02:59:16 PM PDT 24
Peak memory 203024 kb
Host smart-57879402-2121-453e-9ff4-ec6052219e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23408
88098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2340888098
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3692748829
Short name T106
Test name
Test status
Simulation time 8384002177 ps
CPU time 7.26 seconds
Started Mar 12 02:59:11 PM PDT 24
Finished Mar 12 02:59:21 PM PDT 24
Peak memory 203028 kb
Host smart-5a5a0484-a21d-4d0b-8df7-0d240d9219e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36927
48829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3692748829
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.656642840
Short name T295
Test name
Test status
Simulation time 8408744669 ps
CPU time 9 seconds
Started Mar 12 02:59:17 PM PDT 24
Finished Mar 12 02:59:26 PM PDT 24
Peak memory 202992 kb
Host smart-eaf85f13-11a4-4c21-b46e-db97161eebb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65664
2840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.656642840
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3214363571
Short name T436
Test name
Test status
Simulation time 8366546996 ps
CPU time 7.84 seconds
Started Mar 12 02:59:11 PM PDT 24
Finished Mar 12 02:59:21 PM PDT 24
Peak memory 203008 kb
Host smart-d21f4e7f-346a-427b-b08c-f7502096396b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32143
63571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3214363571
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1196103323
Short name T631
Test name
Test status
Simulation time 8404058514 ps
CPU time 8.15 seconds
Started Mar 12 02:59:34 PM PDT 24
Finished Mar 12 02:59:42 PM PDT 24
Peak memory 203000 kb
Host smart-37eb56e2-fe57-4522-b70b-b951a9bd74b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11961
03323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1196103323
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3305760547
Short name T310
Test name
Test status
Simulation time 8407446160 ps
CPU time 7.11 seconds
Started Mar 12 02:59:11 PM PDT 24
Finished Mar 12 02:59:20 PM PDT 24
Peak memory 202988 kb
Host smart-14af1568-1d44-4a59-be4e-e132fa086e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33057
60547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3305760547
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3893472990
Short name T316
Test name
Test status
Simulation time 8398572948 ps
CPU time 9.78 seconds
Started Mar 12 02:59:13 PM PDT 24
Finished Mar 12 02:59:24 PM PDT 24
Peak memory 203000 kb
Host smart-d2882947-d975-446a-8b1a-2a2f944a81c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38934
72990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3893472990
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1915290695
Short name T458
Test name
Test status
Simulation time 26663470 ps
CPU time 0.63 seconds
Started Mar 12 02:59:11 PM PDT 24
Finished Mar 12 02:59:14 PM PDT 24
Peak memory 202940 kb
Host smart-bdf089e4-ed42-4a37-ac47-ca303f319e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19152
90695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1915290695
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.258035324
Short name T419
Test name
Test status
Simulation time 8452892906 ps
CPU time 7.77 seconds
Started Mar 12 02:59:12 PM PDT 24
Finished Mar 12 02:59:22 PM PDT 24
Peak memory 202940 kb
Host smart-171c14f6-7743-4917-ac42-89a37c73f3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25803
5324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.258035324
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.1175279856
Short name T234
Test name
Test status
Simulation time 8383828227 ps
CPU time 6.98 seconds
Started Mar 12 02:59:12 PM PDT 24
Finished Mar 12 02:59:21 PM PDT 24
Peak memory 202944 kb
Host smart-c6ae1523-44d4-418d-a7c3-81d60eb1d737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11752
79856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.1175279856
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.373488058
Short name T482
Test name
Test status
Simulation time 8361190055 ps
CPU time 7.62 seconds
Started Mar 12 02:59:11 PM PDT 24
Finished Mar 12 02:59:21 PM PDT 24
Peak memory 203008 kb
Host smart-29243bae-2737-413c-8fd0-f6ba2c663503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37348
8058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.373488058
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.4230360736
Short name T439
Test name
Test status
Simulation time 8473695961 ps
CPU time 7.58 seconds
Started Mar 12 02:59:11 PM PDT 24
Finished Mar 12 02:59:21 PM PDT 24
Peak memory 203056 kb
Host smart-03a427c3-9504-4119-9173-bc52634780df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42303
60736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.4230360736
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2604410815
Short name T235
Test name
Test status
Simulation time 8370761864 ps
CPU time 7.67 seconds
Started Mar 12 02:56:59 PM PDT 24
Finished Mar 12 02:57:07 PM PDT 24
Peak memory 202988 kb
Host smart-a1121614-9530-48c6-a9b8-520cfb11041b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26044
10815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2604410815
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.4274030586
Short name T170
Test name
Test status
Simulation time 44334972 ps
CPU time 1.34 seconds
Started Mar 12 02:57:00 PM PDT 24
Finished Mar 12 02:57:01 PM PDT 24
Peak memory 203008 kb
Host smart-36540dae-d14f-4986-9288-a8549806b43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42740
30586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4274030586
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2194250844
Short name T515
Test name
Test status
Simulation time 8421889143 ps
CPU time 8.47 seconds
Started Mar 12 02:56:57 PM PDT 24
Finished Mar 12 02:57:08 PM PDT 24
Peak memory 203028 kb
Host smart-8ed0e39e-6d5d-4ccb-b04c-2a5ad701b2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21942
50844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2194250844
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2147259729
Short name T463
Test name
Test status
Simulation time 8406647172 ps
CPU time 7.33 seconds
Started Mar 12 02:56:56 PM PDT 24
Finished Mar 12 02:57:04 PM PDT 24
Peak memory 202952 kb
Host smart-b0ccc8f1-c59f-40a3-b384-8b76bb10b04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21472
59729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2147259729
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3635701104
Short name T424
Test name
Test status
Simulation time 8368160810 ps
CPU time 7.14 seconds
Started Mar 12 02:56:57 PM PDT 24
Finished Mar 12 02:57:06 PM PDT 24
Peak memory 203012 kb
Host smart-491b8ce1-552b-43bd-8aec-c7337b84eb2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36357
01104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3635701104
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2352706668
Short name T708
Test name
Test status
Simulation time 8406771836 ps
CPU time 7.98 seconds
Started Mar 12 02:57:02 PM PDT 24
Finished Mar 12 02:57:10 PM PDT 24
Peak memory 203004 kb
Host smart-0b6baa99-0714-4fed-944a-46584a4f7505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23527
06668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2352706668
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2307880760
Short name T651
Test name
Test status
Simulation time 8387192007 ps
CPU time 7.66 seconds
Started Mar 12 02:57:04 PM PDT 24
Finished Mar 12 02:57:12 PM PDT 24
Peak memory 203024 kb
Host smart-d3da8106-32db-403f-a7fd-7bc9e927583c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23078
80760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2307880760
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.4203983495
Short name T293
Test name
Test status
Simulation time 8370191228 ps
CPU time 8.23 seconds
Started Mar 12 02:56:58 PM PDT 24
Finished Mar 12 02:57:07 PM PDT 24
Peak memory 202984 kb
Host smart-2b29f849-9c60-4d5d-93c7-d1348603548f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42039
83495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.4203983495
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.4012132899
Short name T31
Test name
Test status
Simulation time 29951295 ps
CPU time 0.7 seconds
Started Mar 12 02:57:02 PM PDT 24
Finished Mar 12 02:57:03 PM PDT 24
Peak memory 202940 kb
Host smart-3cf99aa1-0471-4b99-b96e-4461d8e275cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40121
32899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.4012132899
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3430982863
Short name T413
Test name
Test status
Simulation time 8407395638 ps
CPU time 8.89 seconds
Started Mar 12 02:56:59 PM PDT 24
Finished Mar 12 02:57:09 PM PDT 24
Peak memory 202992 kb
Host smart-bbe01f7f-cea6-4a35-a8a9-81ba7ff0f374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34309
82863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3430982863
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.237669396
Short name T271
Test name
Test status
Simulation time 8399299683 ps
CPU time 7.72 seconds
Started Mar 12 02:57:01 PM PDT 24
Finished Mar 12 02:57:09 PM PDT 24
Peak memory 203008 kb
Host smart-879f6d1e-466a-4b88-b87b-9dd95b167984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23766
9396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.237669396
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1343831387
Short name T287
Test name
Test status
Simulation time 8359737459 ps
CPU time 9.04 seconds
Started Mar 12 02:56:58 PM PDT 24
Finished Mar 12 02:57:08 PM PDT 24
Peak memory 203024 kb
Host smart-57d60e97-e6ae-4ad2-856c-b3b646d994f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13438
31387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1343831387
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.833517545
Short name T662
Test name
Test status
Simulation time 8469922138 ps
CPU time 7.24 seconds
Started Mar 12 02:56:59 PM PDT 24
Finished Mar 12 02:57:07 PM PDT 24
Peak memory 203032 kb
Host smart-dd951b6f-5991-4085-a506-48ff432d35db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83351
7545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.833517545
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1887835090
Short name T184
Test name
Test status
Simulation time 8369171144 ps
CPU time 7.36 seconds
Started Mar 12 02:57:02 PM PDT 24
Finished Mar 12 02:57:10 PM PDT 24
Peak memory 203008 kb
Host smart-3523582a-715d-43c7-967e-d27f80d21b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18878
35090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1887835090
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3995599997
Short name T604
Test name
Test status
Simulation time 144568568 ps
CPU time 1.41 seconds
Started Mar 12 02:57:08 PM PDT 24
Finished Mar 12 02:57:10 PM PDT 24
Peak memory 203044 kb
Host smart-10be0ecb-e6ee-4f24-a508-41c6cf8266c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39955
99997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3995599997
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.4072684727
Short name T585
Test name
Test status
Simulation time 8404215481 ps
CPU time 7.33 seconds
Started Mar 12 02:57:14 PM PDT 24
Finished Mar 12 02:57:22 PM PDT 24
Peak memory 203004 kb
Host smart-d2ea6f50-ac4d-47c3-a998-7fa7635da056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40726
84727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.4072684727
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.4029683801
Short name T525
Test name
Test status
Simulation time 8362500184 ps
CPU time 9.45 seconds
Started Mar 12 02:57:10 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 202988 kb
Host smart-4294965a-9e78-4738-a51b-abb26def2cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40296
83801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.4029683801
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2442885549
Short name T72
Test name
Test status
Simulation time 8405582684 ps
CPU time 7.24 seconds
Started Mar 12 02:57:13 PM PDT 24
Finished Mar 12 02:57:21 PM PDT 24
Peak memory 202992 kb
Host smart-675fc3e0-e53a-49f1-a8ce-3ffbf9bdab54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24428
85549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2442885549
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1828854535
Short name T177
Test name
Test status
Simulation time 8371879285 ps
CPU time 7.43 seconds
Started Mar 12 02:57:12 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 203016 kb
Host smart-bc287775-2750-449e-9f74-9925cad7caf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18288
54535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1828854535
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1025272887
Short name T663
Test name
Test status
Simulation time 8390603231 ps
CPU time 7.6 seconds
Started Mar 12 02:57:12 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 203016 kb
Host smart-d4d02d44-f4e0-448e-85c0-02e7f970dd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10252
72887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1025272887
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2410846936
Short name T32
Test name
Test status
Simulation time 25159159 ps
CPU time 0.65 seconds
Started Mar 12 02:57:13 PM PDT 24
Finished Mar 12 02:57:14 PM PDT 24
Peak memory 202928 kb
Host smart-def58e35-aee4-4aa3-b7c3-0416b14a12c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24108
46936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2410846936
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1778548301
Short name T380
Test name
Test status
Simulation time 8396720354 ps
CPU time 7.77 seconds
Started Mar 12 02:57:13 PM PDT 24
Finished Mar 12 02:57:21 PM PDT 24
Peak memory 203036 kb
Host smart-58cf5bed-67cf-48e3-8f17-c31d8e46d9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17785
48301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1778548301
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.921981872
Short name T408
Test name
Test status
Simulation time 8383143783 ps
CPU time 7.81 seconds
Started Mar 12 02:57:12 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 202984 kb
Host smart-2232b0b0-b43c-44c0-b830-23fec803a9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92198
1872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.921981872
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1916919994
Short name T370
Test name
Test status
Simulation time 8355089467 ps
CPU time 6.99 seconds
Started Mar 12 02:57:10 PM PDT 24
Finished Mar 12 02:57:17 PM PDT 24
Peak memory 203024 kb
Host smart-1aadeeae-e33d-44ff-802a-50cf9d89b872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19169
19994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1916919994
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1657166119
Short name T110
Test name
Test status
Simulation time 8481054327 ps
CPU time 8.12 seconds
Started Mar 12 02:57:01 PM PDT 24
Finished Mar 12 02:57:09 PM PDT 24
Peak memory 203052 kb
Host smart-259120a3-1364-4692-b308-c62eab92da64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16571
66119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1657166119
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3693511765
Short name T687
Test name
Test status
Simulation time 8373138518 ps
CPU time 9.1 seconds
Started Mar 12 02:57:09 PM PDT 24
Finished Mar 12 02:57:18 PM PDT 24
Peak memory 203000 kb
Host smart-9673a97f-d2bb-410a-a543-0ba1024c9982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36935
11765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3693511765
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2771742711
Short name T343
Test name
Test status
Simulation time 147508538 ps
CPU time 1.76 seconds
Started Mar 12 02:57:11 PM PDT 24
Finished Mar 12 02:57:13 PM PDT 24
Peak memory 203012 kb
Host smart-8a652c2d-cdbd-4609-970d-d7d3a9322e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27717
42711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2771742711
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.708094860
Short name T550
Test name
Test status
Simulation time 8430105974 ps
CPU time 7.4 seconds
Started Mar 12 02:57:11 PM PDT 24
Finished Mar 12 02:57:19 PM PDT 24
Peak memory 202996 kb
Host smart-7b03b2e7-6fb4-4dc1-b3d4-8ca8d40e23ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70809
4860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.708094860
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.205066734
Short name T608
Test name
Test status
Simulation time 8408393527 ps
CPU time 7.9 seconds
Started Mar 12 02:57:12 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 203048 kb
Host smart-b3a0e2eb-c409-4b55-81a3-856195091bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20506
6734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.205066734
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2373978338
Short name T540
Test name
Test status
Simulation time 8368286580 ps
CPU time 7.18 seconds
Started Mar 12 02:57:14 PM PDT 24
Finished Mar 12 02:57:22 PM PDT 24
Peak memory 202992 kb
Host smart-377844a5-8f2f-4b2b-b536-b584c2555740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23739
78338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2373978338
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.4142311699
Short name T627
Test name
Test status
Simulation time 8431959807 ps
CPU time 7.97 seconds
Started Mar 12 02:57:12 PM PDT 24
Finished Mar 12 02:57:21 PM PDT 24
Peak memory 203004 kb
Host smart-e6e28468-d245-4c36-8f7c-6e35925f439b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41423
11699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.4142311699
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3754683747
Short name T707
Test name
Test status
Simulation time 8383142187 ps
CPU time 9.13 seconds
Started Mar 12 02:57:14 PM PDT 24
Finished Mar 12 02:57:24 PM PDT 24
Peak memory 202920 kb
Host smart-086277e9-cbad-460d-afaf-64410ad61437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37546
83747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3754683747
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1490439939
Short name T665
Test name
Test status
Simulation time 8388652346 ps
CPU time 7.51 seconds
Started Mar 12 02:57:15 PM PDT 24
Finished Mar 12 02:57:22 PM PDT 24
Peak memory 203008 kb
Host smart-4b1b7e19-872b-4f35-b1f2-58afcc2aa337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14904
39939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1490439939
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2513251114
Short name T648
Test name
Test status
Simulation time 31346557 ps
CPU time 0.65 seconds
Started Mar 12 02:57:08 PM PDT 24
Finished Mar 12 02:57:09 PM PDT 24
Peak memory 202956 kb
Host smart-ec061ca6-870b-49b7-820a-0f0fa50beb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25132
51114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2513251114
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1073670204
Short name T606
Test name
Test status
Simulation time 8422099304 ps
CPU time 9.07 seconds
Started Mar 12 02:57:11 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 202936 kb
Host smart-7e608f18-02cc-4828-acfe-960e67ab0e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10736
70204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1073670204
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.1657648006
Short name T244
Test name
Test status
Simulation time 8390792099 ps
CPU time 8.24 seconds
Started Mar 12 02:57:09 PM PDT 24
Finished Mar 12 02:57:18 PM PDT 24
Peak memory 203000 kb
Host smart-b03cc793-fc96-4c35-9ecf-d53c8dbe7f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16576
48006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.1657648006
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.705176230
Short name T449
Test name
Test status
Simulation time 8357300486 ps
CPU time 9.4 seconds
Started Mar 12 02:57:11 PM PDT 24
Finished Mar 12 02:57:21 PM PDT 24
Peak memory 203024 kb
Host smart-f47eea90-4685-4d40-97a3-2dced649f9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70517
6230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.705176230
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.620641194
Short name T34
Test name
Test status
Simulation time 8472297823 ps
CPU time 8.36 seconds
Started Mar 12 02:57:14 PM PDT 24
Finished Mar 12 02:57:23 PM PDT 24
Peak memory 202948 kb
Host smart-9a2f81c5-5e87-4604-ae2d-fbdac9c5cdd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62064
1194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.620641194
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.4101416931
Short name T642
Test name
Test status
Simulation time 8368424198 ps
CPU time 7.5 seconds
Started Mar 12 02:57:14 PM PDT 24
Finished Mar 12 02:57:22 PM PDT 24
Peak memory 202916 kb
Host smart-58e8ed76-971e-4ec2-b36f-d003354bcf7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41014
16931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.4101416931
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3701639658
Short name T163
Test name
Test status
Simulation time 44663045 ps
CPU time 1.24 seconds
Started Mar 12 02:57:10 PM PDT 24
Finished Mar 12 02:57:12 PM PDT 24
Peak memory 203020 kb
Host smart-51dfa632-9960-4f90-a588-e150fd6e00cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37016
39658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3701639658
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3759007072
Short name T712
Test name
Test status
Simulation time 8407836129 ps
CPU time 7.59 seconds
Started Mar 12 02:57:11 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 202992 kb
Host smart-1654bd43-39c0-43ba-afb0-034370d0d57a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37590
07072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3759007072
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.857755530
Short name T315
Test name
Test status
Simulation time 8404705475 ps
CPU time 8.79 seconds
Started Mar 12 02:57:12 PM PDT 24
Finished Mar 12 02:57:21 PM PDT 24
Peak memory 202992 kb
Host smart-3ba80d31-f725-4cfc-af4f-4150781e2b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85775
5530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.857755530
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1847803573
Short name T257
Test name
Test status
Simulation time 8360515776 ps
CPU time 9.28 seconds
Started Mar 12 02:57:13 PM PDT 24
Finished Mar 12 02:57:22 PM PDT 24
Peak memory 203048 kb
Host smart-c30f41f8-cebc-49a7-bac7-bf337b084344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18478
03573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1847803573
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2875536886
Short name T79
Test name
Test status
Simulation time 8442304017 ps
CPU time 7.89 seconds
Started Mar 12 02:57:10 PM PDT 24
Finished Mar 12 02:57:18 PM PDT 24
Peak memory 202972 kb
Host smart-7c0f0397-a229-4955-aa66-e5b6869a283c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755
36886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2875536886
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1002514016
Short name T435
Test name
Test status
Simulation time 8379816824 ps
CPU time 7.16 seconds
Started Mar 12 02:57:14 PM PDT 24
Finished Mar 12 02:57:22 PM PDT 24
Peak memory 202956 kb
Host smart-300be9e1-07d3-48df-9890-cb9f6174ba04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10025
14016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1002514016
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2042567034
Short name T595
Test name
Test status
Simulation time 8403079799 ps
CPU time 8.05 seconds
Started Mar 12 02:57:10 PM PDT 24
Finished Mar 12 02:57:19 PM PDT 24
Peak memory 203036 kb
Host smart-cbf6e9f1-cfd9-4a03-a552-7a84365ef09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20425
67034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2042567034
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2882217061
Short name T507
Test name
Test status
Simulation time 27997749 ps
CPU time 0.63 seconds
Started Mar 12 02:57:11 PM PDT 24
Finished Mar 12 02:57:12 PM PDT 24
Peak memory 202912 kb
Host smart-99886ac0-07b4-4c34-9b60-840c0ab715ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28822
17061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2882217061
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.398929759
Short name T691
Test name
Test status
Simulation time 8369795001 ps
CPU time 7.26 seconds
Started Mar 12 02:57:11 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 202996 kb
Host smart-bf9e623f-d819-49a1-996e-8ceca3fb2b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39892
9759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.398929759
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.3511573679
Short name T164
Test name
Test status
Simulation time 8401985784 ps
CPU time 9.51 seconds
Started Mar 12 02:57:09 PM PDT 24
Finished Mar 12 02:57:19 PM PDT 24
Peak memory 202980 kb
Host smart-861f0610-a62b-49fd-b008-24f04892c083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35115
73679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.3511573679
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1573111098
Short name T340
Test name
Test status
Simulation time 8354385240 ps
CPU time 7.55 seconds
Started Mar 12 02:57:12 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 203008 kb
Host smart-101f4257-2586-47f9-a493-662b50bc3dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15731
11098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1573111098
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1589078220
Short name T130
Test name
Test status
Simulation time 8481910137 ps
CPU time 7.49 seconds
Started Mar 12 02:57:12 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 203024 kb
Host smart-3779c2eb-798d-4412-89ba-3251787418da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15890
78220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1589078220
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1660001911
Short name T266
Test name
Test status
Simulation time 8373909277 ps
CPU time 7.49 seconds
Started Mar 12 02:57:12 PM PDT 24
Finished Mar 12 02:57:20 PM PDT 24
Peak memory 202960 kb
Host smart-bfa29ad1-30bc-497f-9972-97bfe0cf977d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16600
01911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1660001911
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3378397734
Short name T468
Test name
Test status
Simulation time 104214898 ps
CPU time 1.37 seconds
Started Mar 12 02:57:16 PM PDT 24
Finished Mar 12 02:57:18 PM PDT 24
Peak memory 203072 kb
Host smart-78c97105-e509-4781-9c91-909a05200ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33783
97734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3378397734
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2135199561
Short name T119
Test name
Test status
Simulation time 8441574696 ps
CPU time 7.55 seconds
Started Mar 12 02:57:13 PM PDT 24
Finished Mar 12 02:57:21 PM PDT 24
Peak memory 202876 kb
Host smart-c9264759-e9bf-491e-a65d-08c417af5ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21351
99561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2135199561
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.114117137
Short name T682
Test name
Test status
Simulation time 8405170587 ps
CPU time 8.26 seconds
Started Mar 12 02:57:21 PM PDT 24
Finished Mar 12 02:57:30 PM PDT 24
Peak memory 202944 kb
Host smart-5f8fb2bc-ea4a-48ed-aeeb-3d4c5d256b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11411
7137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.114117137
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2522684245
Short name T613
Test name
Test status
Simulation time 8366841498 ps
CPU time 7.84 seconds
Started Mar 12 02:57:21 PM PDT 24
Finished Mar 12 02:57:29 PM PDT 24
Peak memory 203004 kb
Host smart-e53109a7-f6ee-4781-a980-f3c7a707b882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25226
84245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2522684245
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1680559510
Short name T80
Test name
Test status
Simulation time 8447792418 ps
CPU time 8.8 seconds
Started Mar 12 02:57:16 PM PDT 24
Finished Mar 12 02:57:25 PM PDT 24
Peak memory 202988 kb
Host smart-1368c908-b3fe-4e35-aff0-2b6be23f3093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16805
59510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1680559510
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.78719660
Short name T497
Test name
Test status
Simulation time 8384339661 ps
CPU time 7.81 seconds
Started Mar 12 02:57:13 PM PDT 24
Finished Mar 12 02:57:21 PM PDT 24
Peak memory 203012 kb
Host smart-8a04f927-2eb9-4c28-a28c-4f74d14bd350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78719
660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.78719660
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.330057590
Short name T572
Test name
Test status
Simulation time 8391907105 ps
CPU time 7.13 seconds
Started Mar 12 02:57:26 PM PDT 24
Finished Mar 12 02:57:34 PM PDT 24
Peak memory 202992 kb
Host smart-20326a92-ba0f-45b8-9b6f-deb43b8b2063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33005
7590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.330057590
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2319341964
Short name T364
Test name
Test status
Simulation time 32430316 ps
CPU time 0.63 seconds
Started Mar 12 02:57:26 PM PDT 24
Finished Mar 12 02:57:28 PM PDT 24
Peak memory 202956 kb
Host smart-67724bb4-064f-47fc-a856-61f575ff2268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23193
41964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2319341964
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.640669300
Short name T580
Test name
Test status
Simulation time 8413435632 ps
CPU time 7.66 seconds
Started Mar 12 02:57:13 PM PDT 24
Finished Mar 12 02:57:21 PM PDT 24
Peak memory 202900 kb
Host smart-e4f33ac0-9c7c-40c5-b374-cfdc571f8e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64066
9300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.640669300
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.531382606
Short name T252
Test name
Test status
Simulation time 8407807918 ps
CPU time 8.09 seconds
Started Mar 12 02:57:12 PM PDT 24
Finished Mar 12 02:57:21 PM PDT 24
Peak memory 203004 kb
Host smart-6a1ce9bc-7de1-4986-91c2-ceb00eab81a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53138
2606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.531382606
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1057593867
Short name T686
Test name
Test status
Simulation time 8359452151 ps
CPU time 8.36 seconds
Started Mar 12 02:57:22 PM PDT 24
Finished Mar 12 02:57:31 PM PDT 24
Peak memory 202940 kb
Host smart-15b12892-1c56-4962-9459-2100f98d1840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10575
93867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1057593867
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.4191254808
Short name T128
Test name
Test status
Simulation time 8469433817 ps
CPU time 7.53 seconds
Started Mar 12 02:57:14 PM PDT 24
Finished Mar 12 02:57:22 PM PDT 24
Peak memory 202972 kb
Host smart-4eef0d62-2931-491f-8e7e-816f5b9d3ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41912
54808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.4191254808
Directory /workspace/9.usbdev_smoke/latest
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