USBDEV Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: bc285b7382

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 10.060s 8.474ms 50 50 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.900s 52.656us 5 5 100.00
V1 csr_rw usbdev_csr_rw 1.110s 81.650us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 8.130s 363.073us 3 5 60.00
V1 csr_aliasing usbdev_csr_aliasing 3.910s 335.352us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 2.650s 92.345us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 1.110s 81.650us 20 20 100.00
usbdev_csr_aliasing 3.910s 335.352us 5 5 100.00
V1 mem_walk usbdev_mem_walk 4.240s 477.949us 4 5 80.00
V1 mem_partial_access usbdev_mem_partial_access 2.270s 154.288us 5 5 100.00
V1 TOTAL 112 115 97.39
V2 in_trans usbdev_in_trans 10.140s 8.376ms 46 50 92.00
V2 data_toggle_clear data_toggle_clear 0 0 --
V2 phy_pins_sense phy_pins_sense 0 0 --
V2 wake_events wake_events 0 0 --
V2 av_buffer usbdev_av_buffer 10.010s 8.373ms 50 50 100.00
V2 rx_fifo rx_fifo 0 0 --
V2 phy_config_tx_osc_test_mode phy_config_tx_osc_test_mode 0 0 --
V2 phy_config_eop_single_bit_handling phy_config_eop_single_bit_handling 0 0 --
V2 phy_config_pinflip phy_config_pinflip 0 0 --
V2 phy_config_usb_ref_disable phy_config_usb_ref_disable 0 0 --
V2 max_length_out_transaction usbdev_max_length_out_transaction 9.930s 8.407ms 50 50 100.00
V2 max_length_in_transaction max_length_in_transaction 0 0 --
V2 min_length_out_transaction usbdev_min_length_out_transaction 9.790s 8.361ms 50 50 100.00
V2 min_length_in_transaction min_length_in_transaction 0 0 --
V2 random_length_out_trans usbdev_random_length_out_trans 9.630s 8.395ms 50 50 100.00
V2 random_length_in_trans random_length_in_trans 0 0 --
V2 out_stall usbdev_out_stall 10.080s 8.376ms 50 50 100.00
V2 in_stall in_stall 0 0 --
V2 out_iso out_iso 0 0 --
V2 in_iso in_iso 0 0 --
V2 pkt_received usbdev_pkt_received 10.190s 8.384ms 0 50 0.00
V2 pkt_sent usbdev_pkt_sent 9.590s 8.378ms 47 50 94.00
V2 disconnected disconnected 0 0 --
V2 host_lost host_lost 0 0 --
V2 link_reset link_reset 0 0 --
V2 link_suspend link_suspend 0 0 --
V2 link_resume link_resume 0 0 --
V2 av_empty av_empty 0 0 --
V2 rx_full rx_full 0 0 --
V2 av_overflow av_overflow 0 0 --
V2 enable usbdev_enable 9.690s 8.352ms 0 50 0.00
V2 resume_link_active resume_link_active 0 0 --
V2 device_address device_address 0 0 --
V2 link_in_err link_in_err 0 0 --
V2 rx_crc_err rx_crc_err 0 0 --
V2 rx_pid_err rx_pid_err 0 0 --
V2 rx_bitstuff_err rx_bitstuff_err 0 0 --
V2 link_out_err link_out_err 0 0 --
V2 invalid_data1_data0_toggle_test invalid_data1_data0_toggle_test 0 0 --
V2 setup_stage setup_stage 0 0 --
V2 in_data_stage in_data_stage 0 0 --
V2 out_data_stage out_data_stage 0 0 --
V2 out_status_stage out_status_stage 0 0 --
V2 in_status_stage in_status_stage 0 0 --
V2 endpoint_access endpoint_access 0 0 --
V2 disable_endpoint disable_endpoint 0 0 --
V2 out_trans_nak usbdev_out_trans_nak 10.020s 8.384ms 50 50 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 9.910s 8.357ms 50 50 100.00
V2 nak_trans usbdev_nak_trans 10.050s 8.396ms 44 50 88.00
V2 stall_trans stall_trans 0 0 --
V2 setup_priority_over_stall_response setup_priority_over_stall_response 0 0 --
V2 stall_priority_over_NAK stall_priority_over_NAK 0 0 --
V2 pending_in_trans pending_in_trans 0 0 --
V2 streaming_test streaming_test 0 0 --
V2 max_clock_error_untracked max_clock_error_untracked 0 0 --
V2 max_clock_error_tracking max_clock_error_tracking 0 0 --
V2 max_phase_error max_phase_error 0 0 --
V2 min_inter_pkt_delay min_inter_pkt_delay 0 0 --
V2 max_inter_pkt_delay max_inter_pkt_delay 0 0 --
V2 device_timeout_missing_host_handshake device_timeout_missing_host_handshake 0 0 --
V2 device_timeout device_timeout 0 0 --
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0 0 --
V2 aon_wake_resume aon_wake_resume 0 0 --
V2 aon_wake_reset aon_wake_reset 0 0 --
V2 aon_wake_disconnect aon_wake_disconnect 0 0 --
V2 invalid_sync invalid_sync 0 0 --
V2 spurious_tokens_ignored spurious_tokens_ignored 0 0 --
V2 low_speed_traffic low_speed_traffic 0 0 --
V2 rand_bus_resets rand_bus_resets 0 0 --
V2 rand_disconnects rand_disconnects 0 0 --
V2 max_usb_traffic max_usb_traffic 0 0 --
V2 stress_usb_traffic stress_usb_traffic 0 0 --
V2 in_packet_retraction in_packet_retraction 0 0 --
V2 data_toggle_restore data_toggle_restore 0 0 --
V2 setup_priority setup_priority 0 0 --
V2 fifo_resets usbdev_fifo_rst 2.370s 308.201us 50 50 100.00
V2 intr_test usbdev_intr_test 0.680s 26.858us 41 50 82.00
V2 alert_test usbdev_alert_test 0 0 --
V2 tl_d_oob_addr_access usbdev_tl_errors 3.080s 239.972us 20 20 100.00
V2 tl_d_illegal_access usbdev_tl_errors 3.080s 239.972us 20 20 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.900s 52.656us 5 5 100.00
usbdev_csr_rw 1.110s 81.650us 20 20 100.00
usbdev_csr_aliasing 3.910s 335.352us 5 5 100.00
usbdev_same_csr_outstanding 1.650s 157.573us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.900s 52.656us 5 5 100.00
usbdev_csr_rw 1.110s 81.650us 20 20 100.00
usbdev_csr_aliasing 3.910s 335.352us 5 5 100.00
usbdev_same_csr_outstanding 1.650s 157.573us 20 20 100.00
V2 TOTAL 618 740 83.51
V2S tl_intg_err usbdev_sec_cm 1.170s 265.357us 5 5 100.00
usbdev_tl_intg_err 4.840s 501.647us 16 20 80.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 4.840s 501.647us 16 20 80.00
V2S TOTAL 21 25 84.00
V3 TOTAL 0 0 --
Unmapped tests usbdev_phy_pins_sense 0.700s 29.951us 50 50 100.00
usbdev_stress_all_with_rand_reset 0.650s 5.483us 0 50 0.00
usbdev_stress_all 0.610s 0 50 0.00
TOTAL 801 1030 77.77

Testplan Progress

Items Total Written Passing Progress
N.A. 3 3 1 33.33
V1 8 8 6 75.00
V2 80 16 10 12.50
V2S 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
87.91 96.34 88.43 97.17 45.31 94.22 97.36 96.58

Failure Buckets

Past Results