Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51293	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	64816	1		T1	9		T2	6		T3	27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	44050	1		T1	8		T2	2		T3	26
values[0x0]	35761	1		T1	9		T2	3		T3	6
values[0x1]	36298	1		T1	3		T2	2		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41142	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	74967	1		T1	11		T2	6		T3	31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	452	1		T6	6		T10	5		T45	5
valid_sources[0x01]	550	1		T6	3		T10	2		T45	7
valid_sources[0x02]	444	1		T6	7		T10	4		T45	3
valid_sources[0x03]	414	1		T6	4		T10	5		T45	3
valid_sources[0x04]	548	1		T6	3		T10	4		T45	3
valid_sources[0x05]	414	1		T6	3		T10	2		T45	6
valid_sources[0x06]	368	1		T3	1		T6	4		T10	6
valid_sources[0x07]	414	1		T6	7		T10	5		T45	4
valid_sources[0x08]	438	1		T6	3		T10	2		T45	1
valid_sources[0x09]	515	1		T2	1		T6	7		T10	6
valid_sources[0x0a]	412	1		T3	1		T6	6		T10	5
valid_sources[0x0b]	412	1		T6	8		T10	4		T45	3
valid_sources[0x0c]	423	1		T6	3		T10	4		T45	7
valid_sources[0x0d]	433	1		T6	9		T10	4		T45	18
valid_sources[0x0e]	484	1		T6	7		T10	4		T45	3
valid_sources[0x0f]	384	1		T6	8		T10	2		T71	9
valid_sources[0x10]	416	1		T6	6		T10	1		T45	11
valid_sources[0x11]	435	1		T6	4		T10	4		T45	6
valid_sources[0x12]	1100	1		T6	6		T10	5		T45	6
valid_sources[0x13]	451	1		T6	7		T10	3		T45	2
valid_sources[0x14]	631	1		T2	1		T6	6		T10	4
valid_sources[0x15]	491	1		T6	1		T9	13		T10	2
valid_sources[0x16]	362	1		T6	8		T7	1		T10	3
valid_sources[0x17]	455	1		T6	6		T10	4		T45	1
valid_sources[0x18]	518	1		T6	4		T10	3		T45	7
valid_sources[0x19]	397	1		T6	8		T10	6		T45	10
valid_sources[0x1a]	405	1		T6	10		T10	3		T71	3
valid_sources[0x1b]	467	1		T6	3		T10	6		T45	6
valid_sources[0x1c]	422	1		T6	5		T10	3		T71	2
valid_sources[0x1d]	473	1		T6	6		T10	2		T45	2
valid_sources[0x1e]	434	1		T6	3		T10	3		T45	9
valid_sources[0x1f]	434	1		T6	5		T10	4		T45	5
valid_sources[0x20]	348	1		T3	1		T6	5		T10	5
valid_sources[0x21]	365	1		T6	4		T10	4		T45	5
valid_sources[0x22]	549	1		T6	4		T10	2		T45	1
valid_sources[0x23]	622	1		T6	4		T10	3		T45	3
valid_sources[0x24]	491	1		T5	2		T6	7		T10	8
valid_sources[0x25]	397	1		T6	3		T10	6		T45	6
valid_sources[0x26]	369	1		T6	7		T10	8		T45	5
valid_sources[0x27]	408	1		T6	3		T10	7		T45	6
valid_sources[0x28]	376	1		T6	3		T10	9		T45	3
valid_sources[0x29]	359	1		T6	6		T45	1		T71	15
valid_sources[0x2a]	410	1		T6	14		T10	3		T45	6
valid_sources[0x2b]	413	1		T3	1		T6	12		T10	6
valid_sources[0x2c]	406	1		T6	8		T10	5		T45	3
valid_sources[0x2d]	406	1		T3	1		T10	7		T45	12
valid_sources[0x2e]	378	1		T6	7		T10	3		T45	8
valid_sources[0x2f]	356	1		T6	2		T7	2		T10	2
valid_sources[0x30]	568	1		T6	5		T10	5		T45	4
valid_sources[0x31]	430	1		T6	10		T10	2		T45	1
valid_sources[0x32]	311	1		T6	2		T10	1		T45	1
valid_sources[0x33]	387	1		T3	2		T6	5		T10	1
valid_sources[0x34]	463	1		T6	1		T9	4		T10	2
valid_sources[0x35]	450	1		T6	2		T10	1		T45	11
valid_sources[0x36]	416	1		T6	7		T10	2		T45	4
valid_sources[0x37]	1092	1		T6	5		T10	3		T45	3
valid_sources[0x38]	485	1		T6	3		T10	7		T45	1
valid_sources[0x39]	552	1		T6	8		T10	4		T45	16
valid_sources[0x3a]	348	1		T6	4		T10	7		T45	1
valid_sources[0x3b]	361	1		T6	4		T10	3		T45	2
valid_sources[0x3c]	359	1		T6	5		T10	4		T45	2
valid_sources[0x3d]	1038	1		T6	6		T10	1		T71	12
valid_sources[0x3e]	368	1		T6	3		T10	2		T45	4
valid_sources[0x3f]	504	1		T5	1		T6	16		T10	5
valid_sources[0x40]	405	1		T1	20		T6	2		T10	4
valid_sources[0x41]	308	1		T3	1		T6	6		T10	4
valid_sources[0x42]	625	1		T6	4		T10	4		T45	4
valid_sources[0x43]	483	1		T6	2		T10	3		T45	3
valid_sources[0x44]	484	1		T6	10		T10	2		T45	5
valid_sources[0x45]	385	1		T6	9		T10	5		T45	1
valid_sources[0x46]	427	1		T6	2		T10	3		T45	24
valid_sources[0x47]	401	1		T3	1		T6	4		T10	2
valid_sources[0x48]	383	1		T6	5		T10	5		T45	7
valid_sources[0x49]	361	1		T6	3		T10	5		T45	3
valid_sources[0x4a]	429	1		T6	8		T10	3		T45	3
valid_sources[0x4b]	457	1		T10	6		T45	7		T25	2
valid_sources[0x4c]	479	1		T6	2		T10	1		T45	1
valid_sources[0x4d]	463	1		T6	8		T10	1		T45	2
valid_sources[0x4e]	399	1		T6	3		T10	3		T45	3
valid_sources[0x4f]	442	1		T6	3		T10	5		T71	5
valid_sources[0x50]	407	1		T6	5		T10	8		T45	2
valid_sources[0x51]	370	1		T6	5		T10	9		T45	14
valid_sources[0x52]	451	1		T6	7		T10	2		T45	2
valid_sources[0x53]	444	1		T3	1		T6	6		T10	4
valid_sources[0x54]	389	1		T6	6		T45	4		T20	1
valid_sources[0x55]	431	1		T6	1		T10	2		T45	5
valid_sources[0x56]	551	1		T6	6		T10	3		T45	8
valid_sources[0x57]	409	1		T6	5		T10	2		T45	5
valid_sources[0x58]	424	1		T6	1		T10	4		T45	2
valid_sources[0x59]	385	1		T6	5		T10	3		T45	7
valid_sources[0x5a]	1681	1		T3	1		T6	6		T10	1
valid_sources[0x5b]	589	1		T6	5		T10	2		T25	1
valid_sources[0x5c]	539	1		T6	5		T10	5		T45	1
valid_sources[0x5d]	469	1		T6	7		T10	7		T45	4
valid_sources[0x5e]	400	1		T6	6		T10	5		T45	11
valid_sources[0x5f]	377	1		T6	10		T10	2		T45	4
valid_sources[0x60]	419	1		T6	5		T10	2		T45	2
valid_sources[0x61]	446	1		T6	5		T10	8		T45	15
valid_sources[0x62]	442	1		T3	1		T6	4		T10	4
valid_sources[0x63]	470	1		T6	7		T10	1		T67	1
valid_sources[0x64]	365	1		T3	1		T6	6		T10	1
valid_sources[0x65]	291	1		T3	3		T6	1		T10	4
valid_sources[0x66]	451	1		T3	2		T6	6		T10	3
valid_sources[0x67]	458	1		T6	9		T10	9		T45	2
valid_sources[0x68]	343	1		T6	1		T10	4		T45	5
valid_sources[0x69]	441	1		T6	4		T10	2		T45	2
valid_sources[0x6a]	396	1		T6	5		T10	3		T45	8
valid_sources[0x6b]	403	1		T6	4		T10	3		T71	3
valid_sources[0x6c]	470	1		T6	7		T10	8		T71	6
valid_sources[0x6d]	379	1		T6	8		T10	3		T20	2
valid_sources[0x6e]	349	1		T6	3		T10	5		T45	3
valid_sources[0x6f]	403	1		T6	2		T10	5		T71	3
valid_sources[0x70]	377	1		T6	6		T10	2		T45	1
valid_sources[0x71]	366	1		T6	3		T10	1		T45	1
valid_sources[0x72]	372	1		T6	2		T10	2		T45	5
valid_sources[0x73]	461	1		T6	4		T10	8		T45	3
valid_sources[0x74]	527	1		T6	11		T10	2		T45	3
valid_sources[0x75]	446	1		T5	1		T6	5		T10	2
valid_sources[0x76]	480	1		T6	5		T45	1		T14	5
valid_sources[0x77]	410	1		T6	5		T10	5		T45	5
valid_sources[0x78]	451	1		T6	3		T10	6		T45	2
valid_sources[0x79]	342	1		T6	3		T10	2		T45	6
valid_sources[0x7a]	420	1		T6	4		T10	3		T45	4
valid_sources[0x7b]	430	1		T6	3		T10	2		T45	3
valid_sources[0x7c]	387	1		T5	1		T6	5		T10	4
valid_sources[0x7d]	412	1		T6	7		T45	4		T71	4
valid_sources[0x7e]	329	1		T6	3		T10	2		T45	13
valid_sources[0x7f]	401	1		T6	3		T10	5		T71	6
valid_sources[0x80]	465	1		T6	9		T10	5		T45	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24954

1

T1

2

T2

2

T3

18

values[0x0]

all_enables

biggest_size

22303

1

T1

5

T2

2

T3

5

values[0x1]

all_enables

biggest_size

17559

1

T1

2

T2

2

T3

4