Unified Coverage Report :: Module :: prim_fifo_sync_cnt

Module : prim_fifo_sync_cnt

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.48	92.96				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt	70.00	80.00				60.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00
tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt	92.50	95.00				90.00
tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt	92.50	95.00				90.00

---

Module Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.00	80.00				60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.00	80.00				60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.38	100.00	61.54			80.00	100.00	usbdev_rxfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.77	100.00	73.08			90.00	100.00	u_reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.81	100.00	69.23			90.00	100.00	u_sramreqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.94	88.89				75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.03	100.00	76.47			91.67	100.00	u_rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	95.00				90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	95.00				90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.58	100.00	70.83			87.50	100.00	usbdev_avsetupfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	95.00				90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.50	95.00				90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.58	100.00	70.83			87.50	100.00	usbdev_avoutfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=4,Width=3,Secure=0 )
Line Coverage for Module self-instances :

SCORE	LINE
92.50	95.00

tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	19	95.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	76	8	8	100.00
ALWAYS	88	8	7	87.50

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
			MISSING_ELSE
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	0	1
94	1	1
95	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=8,Width=4,Secure=0 )
Line Coverage for Module self-instances :

SCORE	LINE
92.50	95.00

tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
70.00	80.00

tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	19	95.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	76	8	8	100.00
ALWAYS	88	8	7	87.50

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
			MISSING_ELSE
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	0	1
94	1	1
95	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 )
Line Coverage for Module self-instances :

SCORE	LINE
81.94	88.89

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
81.94	88.89

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
81.94	88.89

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	76	7	6	85.71
ALWAYS	88	7	6	85.71

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
76	1	1
77	1	1
78	1	1
79		unreachable
80	1	1
81	1	1
82	1	1
83	0	1
			MISSING_ELSE
88	1	1
89	1	1
90	1	1
91		unreachable
92	1	1
93	1	1
94	1	1
95	0	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_fifo_sync_cnt

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	76	5	5	100.00
IF	88	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T6,T10,T45
0	0	1	-	Covered	T3,T6,T4
0	0	0	1	Covered	T1,T3,T5
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T6,T10,T45
0	0	1	-	Covered	T3,T4,T36
0	0	0	1	Covered	T1,T3,T5
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	16	80.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	76	8	6	75.00
ALWAYS	88	8	6	75.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
76	1	1
77	1	1
78	1	1
79	0	1
80	1	1
81	0	1
82	1	1
83	1	1
			MISSING_ELSE
88	1	1
89	1	1
90	1	1
91	0	1
92	1	1
93	0	1
94	1	1
95	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
IF	76	5	3	60.00
IF	88	5	3	60.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Covered	T1,T3,T5
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Covered	T1,T3,T5
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	76	7	6	85.71
ALWAYS	88	7	6	85.71

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
76	1	1
77	1	1
78	1	1
79		unreachable
80	1	1
81	1	1
82	1	1
83	0	1
			MISSING_ELSE
88	1	1
89	1	1
90	1	1
91		unreachable
92	1	1
93	1	1
94	1	1
95	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	76	4	3	75.00
IF	88	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T3,T4,T36
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T3,T4,T36
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	76	7	6	85.71
ALWAYS	88	7	6	85.71

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
76	1	1
77	1	1
78	1	1
79		unreachable
80	1	1
81	1	1
82	1	1
83	0	1
			MISSING_ELSE
88	1	1
89	1	1
90	1	1
91		unreachable
92	1	1
93	1	1
94	1	1
95	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	76	4	3	75.00
IF	88	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T3,T4,T36
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T3,T4,T36
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	16	88.89
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	76	7	6	85.71
ALWAYS	88	7	6	85.71

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
76	1	1
77	1	1
78	1	1
79		unreachable
80	1	1
81	1	1
82	1	1
83	0	1
			MISSING_ELSE
88	1	1
89	1	1
90	1	1
91		unreachable
92	1	1
93	1	1
94	1	1
95	0	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	6	75.00
IF	76	4	3	75.00
IF	88	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T3,T4,T36
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Unreachable
0	0	1	-	Covered	T3,T4,T36
0	0	0	1	Not Covered
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	19	95.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	76	8	8	100.00
ALWAYS	88	8	7	87.50

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
			MISSING_ELSE
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	0	1
94	1	1
95	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
IF	76	5	5	100.00
IF	88	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T6,T10,T45
0	0	1	-	Covered	T6,T10,T45
0	0	0	1	Covered	T3,T6,T10
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T6,T10,T45
0	0	1	-	Not Covered
0	0	0	1	Covered	T3,T14,T15
0	0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	19	95.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	76	8	8	100.00
ALWAYS	88	8	7	87.50

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
30	1	1
32	1	1
33	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
			MISSING_ELSE
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	0	1
94	1	1
95	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
IF	76	5	5	100.00
IF	88	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T6,T10,T45
0	0	1	-	Covered	T6,T10,T45
0	0	0	1	Covered	T1,T3,T5
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T6,T10,T45
0	0	1	-	Not Covered
0	0	0	1	Covered	T1,T3,T5
0	0	0	0	Covered	T1,T2,T3