Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.25	96.75	68.07	93.93		87.50	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	238672165	12503	0	0
ep_in_enable_rd_A	238672165	516	0	0
ep_out_enable_rd_A	238672165	432	0	0
in_iso_rd_A	238672165	439	0	0
intr_enable_rd_A	238672165	798	0	0
out_iso_rd_A	238672165	396	0	0
phy_config_rd_A	238672165	393	0	0
phy_pins_drive_rd_A	238672165	505	0	0
rxenable_setup_rd_A	238672165	432	0	0
set_nak_out_rd_A	238672165	524	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	12503	0	0
T46	9202	691	0	0
T47	8353	727	0	0
T48	8037	426	0	0
T55	6863	13	0	0
T56	3549	9	0	0
T74	3707	10	0	0
T184	12643	1019	0	0
T185	10714	954	0	0
T186	3238	22	0	0
T187	9929	762	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	516	0	0
T55	6863	62	0	0
T73	2439	24	0	0
T74	3707	2	0	0
T196	17830	127	0	0
T232	4097	10	0	0
T233	7312	58	0	0
T234	7117	62	0	0
T235	4432	31	0	0
T236	6278	15	0	0
T237	7093	67	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	432	0	0
T55	6863	42	0	0
T73	2439	16	0	0
T74	3707	8	0	0
T75	2170	21	0	0
T184	12643	3	0	0
T196	17830	122	0	0
T232	4097	2	0	0
T233	7312	51	0	0
T234	7117	8	0	0
T235	4432	41	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	439	0	0
T55	6863	62	0	0
T73	2439	33	0	0
T74	3707	45	0	0
T75	2170	19	0	0
T196	17830	114	0	0
T232	4097	19	0	0
T233	7312	27	0	0
T234	7117	23	0	0
T235	4432	7	0	0
T236	6278	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	798	0	0
T48	8037	1	0	0
T55	6863	66	0	0
T62	1107	11	0	0
T73	2439	29	0	0
T75	2170	7	0	0
T187	9929	3	0	0
T232	4097	48	0	0
T233	7312	45	0	0
T238	1459	20	0	0
T239	1165	26	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	396	0	0
T55	6863	11	0	0
T73	2439	33	0	0
T74	3707	26	0	0
T184	12643	1	0	0
T196	17830	100	0	0
T232	4097	14	0	0
T233	7312	29	0	0
T234	7117	55	0	0
T235	4432	1	0	0
T240	10761	5	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	393	0	0
T55	6863	30	0	0
T73	2439	8	0	0
T74	3707	3	0	0
T75	2170	17	0	0
T184	12643	10	0	0
T196	17830	157	0	0
T232	4097	3	0	0
T233	7312	18	0	0
T234	7117	24	0	0
T235	4432	20	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	505	0	0
T55	6863	10	0	0
T73	2439	25	0	0
T74	3707	12	0	0
T75	2170	6	0	0
T196	17830	107	0	0
T232	4097	52	0	0
T233	7312	39	0	0
T234	7117	87	0	0
T235	4432	27	0	0
T240	10761	2	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	432	0	0
T55	6863	47	0	0
T74	3707	12	0	0
T75	2170	7	0	0
T196	17830	130	0	0
T232	4097	11	0	0
T233	7312	52	0	0
T234	7117	45	0	0
T236	6278	27	0	0
T237	7093	77	0	0
T241	7399	24	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238672165	524	0	0
T55	6863	77	0	0
T73	2439	28	0	0
T196	17830	103	0	0
T232	4097	4	0	0
T233	7312	45	0	0
T234	7117	48	0	0
T235	4432	32	0	0
T236	6278	25	0	0
T237	7093	103	0	0
T241	7399	59	0	0